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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id g69sm6824842pje.34.2020.03.12.12.42.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 12:42:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YjtJPrBKwGIvW5n3TsllLnWEtrw5AerlDizUV5C1Mio=; b=m4FT5zQa3+2PDG4aTJr/jboc8d20BX16tFdynHRW64k3e+NcDanVhWydFLIHECq4r3 6zL55z1NS+6MDbP0DC4Epz6NJn9poq8ZFF2JsKNq5PcVR3jimQPVtm+0tHGOlvHzEMYN gbGSJacz4VvS4f+9oXIIu5N4O/tjqyAf/Wh0ouYFhp43o28itwkUMJcWx6GhCe4A3iDe +0yZJ919GGm6N8WnrgYg5ubcM0osfsvG4AtXLLT5Z23xPoJwvUOuSxzfsiCZNmSPAQid eEjzq+ev9H5iZZZ49DHt+TbJDkqoYqXY3KmYm9vbRl+3Wsz6ZWbi5rVbttRPkJT8Lbjg lwvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YjtJPrBKwGIvW5n3TsllLnWEtrw5AerlDizUV5C1Mio=; b=HJhnazvGgslXhEg5VCnTYtMDzWIdTkY5THNgZBzmh9GuEMbNkXT6SS93yjCJP+9sg4 bhnrMEnpkXFWpwuuJXaKJ1ccfrUCBqjgMO8g+5KJSz0qjgAbmk8ri82ciYxacVhpSv/3 +noHvybxPCVty/rI6Fkcgec9y8t7IMd9kXpuoo45oYNgYDgceT+goC+eIiku0RmzF77o /ApG3cmsC2pVKC1kqltX/xYXArktxWH9oYu1bM7vqAObA0s3wfgmSjdcza2NXc2Wsvow 4ciWF56GsXLas6irRy1VFqbAHqpkXLPJMrrbTHMulqwruKNPeVmUYRLkE9pG9hbRfBpD ns7A== X-Gm-Message-State: ANhLgQ303QsmaLNte1aRvZpiwhV3F7c6YHlIAVcz0sN+4VLlEAGmuNNN n1KS7nYPS9GmlBJossAx+7XaeLbArI4= X-Google-Smtp-Source: ADFU+vvi+YFkyWTEp07dU9Wrw07CRP+KH+fQFpTxhNofPmPZMFVaipfPsihnsLBqHZlagtau/52AJQ== X-Received: by 2002:a17:902:9a06:: with SMTP id v6mr9797215plp.304.1584042168194; Thu, 12 Mar 2020 12:42:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 20/42] target/arm: Implement the access tag cache flushes Date: Thu, 12 Mar 2020 12:41:57 -0700 Message-Id: <20200312194219.24406-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200312194219.24406-1-richard.henderson@linaro.org> References: <20200312194219.24406-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Like the regular data cache flushes, these are nops within qemu. Signed-off-by: Richard Henderson --- v6: Split out and handle el0 cache ops properly. --- target/arm/helper.c | 65 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 01d2fcf2e3..f9daeec1f4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6914,6 +6914,32 @@ static const ARMCPRegInfo mte_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 7, .type =3D ARM_CP_NO_RAW, .access =3D PL0_RW, .readfn =3D tco_read, .writefn =3D tco_write }, + { .name =3D "DC_IGVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL1_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_IGSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DC_IGDVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL1_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_IGDSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 6, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DC_CGSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DC_CGDSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 6, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DC_CIGSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 4, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, + { .name =3D "DC_CIGDSW", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 6, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, REGINFO_SENTINEL }; =20 @@ -6923,6 +6949,43 @@ static const ARMCPRegInfo mte_tco_ro_reginfo[] =3D { .type =3D ARM_CP_CONST, .access =3D PL0_RW, }, REGINFO_SENTINEL }; + +static const ARMCPRegInfo mte_el0_cacheop_reginfo[] =3D { + { .name =3D "DC_CGVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CGDVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CGVAP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CGDVAP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CGVADP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CGDVADP", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CIGVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 3, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_CIGDVAC", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 5, + .type =3D ARM_CP_NOP, .access =3D PL0_W, + .accessfn =3D aa64_cacheop_poc_access }, + REGINFO_SENTINEL +}; + #endif =20 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, @@ -8048,8 +8111,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) */ if (cpu_isar_feature(aa64_mte, cpu)) { define_arm_cp_regs(cpu, mte_reginfo); + define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); } else if (cpu_isar_feature(aa64_mte_insn_reg, cpu)) { define_arm_cp_regs(cpu, mte_tco_ro_reginfo); + define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); } #endif =20 --=20 2.20.1