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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id g69sm6824842pje.34.2020.03.12.12.42.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 12:42:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vOc7ZuIgleZgJxOlgoEqlYtRf9AKklvLS59uoi/QsS0=; b=IFlOqtGfWq1iMqXTuyU+3m+mptLlC2hlRPuPsNrGog1gzbkUfb5GrqXKWOdGFXhFtR CS3dEV1SDG1POMqJyfNr4YxNdTgRd/hKwrm0rSZ8S0s/Oe5h6tPvJWPzVqsC0X2A55Dg YjhYUjr4VcBD4F0T7ZCBGsIDhCRxB6/OBIua4JRZp0O/TGetRmEIsTGF5mYFxIsffClg WPFnbDIQIG3DauiIUaM8/NK/EIis+nILn60G0z+/wDt7OHWIkjEOXKFB7sLB/1d1PllH 78ma0/nXlNv68oCzM5bc6SkIhaAA5f+H9ogHB/hXEAByooSrGTkDNxfCx0vbS2Css1R5 Xq8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vOc7ZuIgleZgJxOlgoEqlYtRf9AKklvLS59uoi/QsS0=; b=sXmFRYqXICS1Er15XwTYsoC7wmZ/Rbv42gGBN5bMiHSK5+Z9hiDOtthhJhWCzkD/cN 7Ryn+Z7kJRGYxLj4PAsPApea50/2L63UtrnByHaruV+5TPKClxEQcqFABFQFOjJlglOc yn1G2ICWS3kjsp5JYVnMm47/dSUOnPVV4tu0n51oiRbULNv75l9HhBnYAhoQOs2y2SDa i+S0SSUXEKnxSCV29T0Je9ykLY0xq3lSI9bMW92RbTswuhZMuz2Q5GnQjduFAH9cfF0c 8JyYcX6w1Ee29pUY97hPwkQ7lQHIq8gJYhL9NuG/ahHJeC0LKPHL6i6KQq2H+DyiLXy0 qB1A== X-Gm-Message-State: ANhLgQ1zKBbp9Q21Bc+VtQgS3I/N9dPPehUx1iBB53igFSIigx+V8x/a H76JPnL1/rCKL5hVyzfG2g+bTqkmxtA= X-Google-Smtp-Source: ADFU+vvZLD+z2DX3O7qKjJAFWxPaKaLsyNkrst8CU0ENJUUsbShw3K7LCngI4kznaQ9t9Ea9KPgt7w== X-Received: by 2002:a17:90a:8403:: with SMTP id j3mr5886357pjn.8.1584042158178; Thu, 12 Mar 2020 12:42:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 13/42] target/arm: Define arm_cpu_do_unaligned_access for user-only Date: Thu, 12 Mar 2020 12:41:50 -0700 Message-Id: <20200312194219.24406-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200312194219.24406-1-richard.henderson@linaro.org> References: <20200312194219.24406-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We need this to raise unaligned exceptions from user mode. Signed-off-by: Richard Henderson --- v6: Use EXCP_UNALIGNED for user-only and update cpu_loop.c. --- linux-user/aarch64/cpu_loop.c | 7 ++++++ linux-user/arm/cpu_loop.c | 7 ++++++ target/arm/cpu.c | 2 +- target/arm/tlb_helper.c | 41 ++++++++++++++++++++++------------- 4 files changed, 41 insertions(+), 16 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index bbe9fefca8..3cca637bb9 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -121,6 +121,13 @@ void cpu_loop(CPUARMState *env) info._sifields._sigfault._addr =3D env->exception.vaddress; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); break; + case EXCP_UNALIGNED: + info.si_signo =3D TARGET_SIGBUS; + info.si_errno =3D 0; + info.si_code =3D TARGET_BUS_ADRALN; + info._sifields._sigfault._addr =3D env->exception.vaddress; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; case EXCP_DEBUG: case EXCP_BKPT: info.si_signo =3D TARGET_SIGTRAP; diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index cf618daa1c..d2ce78ae73 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -395,6 +395,13 @@ void cpu_loop(CPUARMState *env) queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); } break; + case EXCP_UNALIGNED: + info.si_signo =3D TARGET_SIGBUS; + info.si_errno =3D 0; + info.si_code =3D TARGET_BUS_ADRALN; + info._sifields._sigfault._addr =3D env->exception.vaddress; + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); + break; case EXCP_DEBUG: excp_debug: info.si_signo =3D TARGET_SIGTRAP; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3623ecefbd..cb3c3fe8c2 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2831,8 +2831,8 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) cc->tlb_fill =3D arm_cpu_tlb_fill; cc->debug_excp_handler =3D arm_debug_excp_handler; cc->debug_check_watchpoint =3D arm_debug_check_watchpoint; -#if !defined(CONFIG_USER_ONLY) cc->do_unaligned_access =3D arm_cpu_do_unaligned_access; +#if !defined(CONFIG_USER_ONLY) cc->do_transaction_failed =3D arm_cpu_do_transaction_failed; cc->adjust_watchpoint_address =3D arm_adjust_watchpoint_address; #endif /* CONFIG_TCG && !CONFIG_USER_ONLY */ diff --git a/target/arm/tlb_helper.c b/target/arm/tlb_helper.c index e63f8bda29..44d7bcc783 100644 --- a/target/arm/tlb_helper.c +++ b/target/arm/tlb_helper.c @@ -107,21 +107,6 @@ static void QEMU_NORETURN arm_deliver_fault(ARMCPU *cp= u, vaddr addr, raise_exception(env, exc, syn, target_el); } =20 -/* Raise a data fault alignment exception for the specified virtual addres= s */ -void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) -{ - ARMCPU *cpu =3D ARM_CPU(cs); - ARMMMUFaultInfo fi =3D {}; - - /* now we have a real cpu fault */ - cpu_restore_state(cs, retaddr, true); - - fi.type =3D ARMFault_Alignment; - arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); -} - /* * arm_cpu_do_transaction_failed: handle a memory system error response * (eg "no device/memory present at address") by raising an external abort @@ -198,3 +183,29 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int= size, } #endif } + +/* Raise a data fault alignment exception for the specified virtual addres= s */ +void arm_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + +#ifdef CONFIG_USER_ONLY + cpu->env.exception.vaddress =3D vaddr; + /* + * For HW, this is EXCP_DATA_ABORT with a proper syndrome. + * Make it easier for ourselves in linux-user/arm/cpu_loop.c. + */ + cs->exception_index =3D EXCP_UNALIGNED; + cpu_loop_exit_restore(cs, retaddr); +#else + ARMMMUFaultInfo fi =3D {}; + + /* now we have a real cpu fault */ + cpu_restore_state(cs, retaddr, true); + + fi.type =3D ARMFault_Alignment; + arm_deliver_fault(cpu, vaddr, access_type, mmu_idx, &fi); +#endif +} --=20 2.20.1