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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j15sm36838640wrp.85.2020.03.12.09.45.07 for <qemu-devel@nongnu.org> (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 09:45:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/PWbtf8pRZrw4wwB/2VhUgWYgstVtgiipMKB/g1At8o=; b=wTUQYuIsqAntuMi3uFoT0i1uV16vdE67N+C7rFUP0l5Inb/a7EEdVX/uLQp3YOZU9M 2BlDpMIR6Y+jW27o0bOzeXL9N2vMzHIA/L3iyKEJDtl6ywKsFXKEIaoOlKxnkSY6QENi K57dCfYxP4Exbz6Ize/BZhKVa8D6OodJ0VDExq0D30ehooxIvA6afBx7ffq/zVNpvsBt e9WBkiUi72ECFYXZDyragU1ObPMVGpgvohLnHUNFGxW4w8v0Jg+a4UMk1b8gqLoGFnU4 hZYx/CecBnFFDX4QM6tcndCAnHb+jreBUaAMUkVdCAlJhea88RxgNfdMoKszkDSd5K/G PGjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/PWbtf8pRZrw4wwB/2VhUgWYgstVtgiipMKB/g1At8o=; b=JNmasdyKK/xuZ/CjlIWUdmX0qKVx7HapUmNVUAw/c2wvDDMF5SFu4KHtdrJ43tnu2s 2ZmAGFgPcTI7D6c06sQnzGCUgqdkDZdHPHpCfSdqjaJCk2dU0K+AAlMJSpFVDizn4/jw lJB+GhN5hnVdEW/BgHGbKpg2oOL3V966AjfGnLZQe9uSK0rNw4faCdKn9UsiZti1g7Oh +kMH2Elc80SRK3ziDDEr3pYN2foRM2lx5NaarHCIBz6gX3LLM3X8eBcgKIJj2dhNIpU0 pddxwxFw7w0W4+++upEoRqnLyLH1RIRzXc7m17rToFW/Xwyu9911EiLzhBEar3dhRvSo fBIg== X-Gm-Message-State: ANhLgQ3uZ4uw/f0YOhZI1mlCWVhaNylmoAcceimnRXl8gmQdQVoMIkn0 eWWqUc0xMqrJVA2JOVV/XT1624Hh4g0f7g== X-Google-Smtp-Source: ADFU+vtiCaUOGSg9m15kyJ+XTSoCxa5v8TsSGZTe7ivRcoGHE9U+DnjPSp2fRMj7cH5gNQf4vtvwfg== X-Received: by 2002:adf:b19d:: with SMTP id q29mr11745218wra.211.1584031508962; Thu, 12 Mar 2020 09:45:08 -0700 (PDT) From: Peter Maydell <peter.maydell@linaro.org> To: qemu-devel@nongnu.org Subject: [PULL 06/36] aspeed/smc: Fix User mode select/unselect scheme Date: Thu, 12 Mar 2020 16:44:29 +0000 Message-Id: <20200312164459.25924-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200312164459.25924-1-peter.maydell@linaro.org> References: <20200312164459.25924-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::431 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: <qemu-devel.nongnu.org> List-Unsubscribe: <https://lists.nongnu.org/mailman/options/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe> List-Archive: <https://lists.nongnu.org/archive/html/qemu-devel> List-Post: <mailto:qemu-devel@nongnu.org> List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help> List-Subscribe: <https://lists.nongnu.org/mailman/listinfo/qemu-devel>, <mailto:qemu-devel-request@nongnu.org?subject=subscribe> Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+importer=patchew.org@nongnu.org> X-ZohoMail-DKIM: pass (identity @linaro.org) From: C=C3=A9dric Le Goater <clg@kaod.org> The Aspeed SMC Controller can operate in different modes : Read, Fast Read, Write and User modes. When the User mode is configured, it selects automatically the SPI slave device until the CE_STOP_ACTIVE bit is set to 1. When any other modes are configured the device is unselected. The HW logic handles the chip select automatically when the flash is accessed through its AHB window. When configuring the CEx Control Register, the User mode logic to select and unselect the slave is incorrect and data corruption can be seen on machines using two chips, witherspoon and romulus. Rework the handler setting the CEx Control Register to fix this issue. Fixes: 7c1c69bca43c ("ast2400: add SMC controllers (FMC and SPI)") Signed-off-by: C=C3=A9dric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Message-id: 20200206112645.21275-3-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- hw/ssi/aspeed_smc.c | 39 +++++++++++++++++++++++---------------- hw/ssi/trace-events | 1 + 2 files changed, 24 insertions(+), 16 deletions(-) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index e5621bf728c..32be2a02b0e 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -639,27 +639,23 @@ static inline int aspeed_smc_flash_is_4byte(const Asp= eedSMCFlash *fl) } } =20 -static inline bool aspeed_smc_is_ce_stop_active(const AspeedSMCFlash *fl) +static void aspeed_smc_flash_do_select(AspeedSMCFlash *fl, bool unselect) { - const AspeedSMCState *s =3D fl->controller; + AspeedSMCState *s =3D fl->controller; =20 - return s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE; + trace_aspeed_smc_flash_select(fl->id, unselect ? "un" : ""); + + qemu_set_irq(s->cs_lines[fl->id], unselect); } =20 static void aspeed_smc_flash_select(AspeedSMCFlash *fl) { - AspeedSMCState *s =3D fl->controller; - - s->regs[s->r_ctrl0 + fl->id] &=3D ~CTRL_CE_STOP_ACTIVE; - qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl)); + aspeed_smc_flash_do_select(fl, false); } =20 static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl) { - AspeedSMCState *s =3D fl->controller; - - s->regs[s->r_ctrl0 + fl->id] |=3D CTRL_CE_STOP_ACTIVE; - qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl)); + aspeed_smc_flash_do_select(fl, true); } =20 static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl, @@ -911,13 +907,25 @@ static const MemoryRegionOps aspeed_smc_flash_ops =3D= { }, }; =20 -static void aspeed_smc_flash_update_cs(AspeedSMCFlash *fl) +static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t valu= e) { AspeedSMCState *s =3D fl->controller; + bool unselect; =20 - s->snoop_index =3D aspeed_smc_is_ce_stop_active(fl) ? SNOOP_OFF : SNOO= P_START; + /* User mode selects the CS, other modes unselect */ + unselect =3D (value & CTRL_CMD_MODE_MASK) !=3D CTRL_USERMODE; =20 - qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl)); + /* A change of CTRL_CE_STOP_ACTIVE from 0 to 1, unselects the CS */ + if (!(s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE) && + value & CTRL_CE_STOP_ACTIVE) { + unselect =3D true; + } + + s->regs[s->r_ctrl0 + fl->id] =3D value; + + s->snoop_index =3D unselect ? SNOOP_OFF : SNOOP_START; + + aspeed_smc_flash_do_select(fl, unselect); } =20 static void aspeed_smc_reset(DeviceState *d) @@ -1249,8 +1257,7 @@ static void aspeed_smc_write(void *opaque, hwaddr add= r, uint64_t data, s->regs[addr] =3D value; } else if (addr >=3D s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) { int cs =3D addr - s->r_ctrl0; - s->regs[addr] =3D value; - aspeed_smc_flash_update_cs(&s->flashes[cs]); + aspeed_smc_flash_update_ctrl(&s->flashes[cs], value); } else if (addr >=3D R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) { int cs =3D addr - R_SEG_ADDR0; diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events index ffe531a500a..0a70629801a 100644 --- a/hw/ssi/trace-events +++ b/hw/ssi/trace-events @@ -7,3 +7,4 @@ aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t siz= e, uint64_t data, int aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx6= 4 " size %u: 0x%" PRIx64 aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x" aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx= 64 " size %u: 0x%" PRIx64 +aspeed_smc_flash_select(int cs, const char *prefix) "CS%d %sselect" --=20 2.20.1