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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 15/36] hw/arm/allwinner-h3: add USB host controller
Date: Thu, 12 Mar 2020 16:44:38 +0000
Message-Id: <20200312164459.25924-16-peter.maydell@linaro.org>
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From: Niek Linnenbank <nieklinnenbank@gmail.com>
The Allwinner H3 System on Chip contains multiple USB 2.0 bus
connections which provide software access using the Enhanced
Host Controller Interface (EHCI) and Open Host Controller
Interface (OHCI) interfaces. This commit adds support for
both interfaces in the Allwinner H3 System on Chip.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Message-id: 20200311221854.30370-5-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/usb/hcd-ehci.h | 1 +
include/hw/arm/allwinner-h3.h | 8 +++++++
hw/arm/allwinner-h3.c | 44 +++++++++++++++++++++++++++++++++++
hw/usb/hcd-ehci-sysbus.c | 17 ++++++++++++++
hw/arm/Kconfig | 2 ++
5 files changed, 72 insertions(+)
diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h
index 0298238f0b9..edb59311c4e 100644
--- a/hw/usb/hcd-ehci.h
+++ b/hw/usb/hcd-ehci.h
@@ -342,6 +342,7 @@ typedef struct EHCIPCIState {
#define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb"
#define TYPE_PLATFORM_EHCI "platform-ehci-usb"
#define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb"
+#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb"
#define TYPE_TEGRA2_EHCI "tegra2-ehci-usb"
#define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb"
#define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb"
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index abdc20871a6..4f4dcbcd177 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -56,6 +56,14 @@ enum {
AW_H3_SRAM_A1,
AW_H3_SRAM_A2,
AW_H3_SRAM_C,
+ AW_H3_EHCI0,
+ AW_H3_OHCI0,
+ AW_H3_EHCI1,
+ AW_H3_OHCI1,
+ AW_H3_EHCI2,
+ AW_H3_OHCI2,
+ AW_H3_EHCI3,
+ AW_H3_OHCI3,
AW_H3_CCU,
AW_H3_PIT,
AW_H3_UART0,
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index 1fff3c317b4..c205f06738a 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -28,6 +28,7 @@
#include "hw/sysbus.h"
#include "hw/char/serial.h"
#include "hw/misc/unimp.h"
+#include "hw/usb/hcd-ehci.h"
#include "sysemu/sysemu.h"
#include "hw/arm/allwinner-h3.h"
=20
@@ -36,6 +37,14 @@ const hwaddr allwinner_h3_memmap[] =3D {
[AW_H3_SRAM_A1] =3D 0x00000000,
[AW_H3_SRAM_A2] =3D 0x00044000,
[AW_H3_SRAM_C] =3D 0x00010000,
+ [AW_H3_EHCI0] =3D 0x01c1a000,
+ [AW_H3_OHCI0] =3D 0x01c1a400,
+ [AW_H3_EHCI1] =3D 0x01c1b000,
+ [AW_H3_OHCI1] =3D 0x01c1b400,
+ [AW_H3_EHCI2] =3D 0x01c1c000,
+ [AW_H3_OHCI2] =3D 0x01c1c400,
+ [AW_H3_EHCI3] =3D 0x01c1d000,
+ [AW_H3_OHCI3] =3D 0x01c1d400,
[AW_H3_CCU] =3D 0x01c20000,
[AW_H3_PIT] =3D 0x01c20c00,
[AW_H3_UART0] =3D 0x01c28000,
@@ -144,6 +153,14 @@ enum {
AW_H3_GIC_SPI_UART3 =3D 3,
AW_H3_GIC_SPI_TIMER0 =3D 18,
AW_H3_GIC_SPI_TIMER1 =3D 19,
+ AW_H3_GIC_SPI_EHCI0 =3D 72,
+ AW_H3_GIC_SPI_OHCI0 =3D 73,
+ AW_H3_GIC_SPI_EHCI1 =3D 74,
+ AW_H3_GIC_SPI_OHCI1 =3D 75,
+ AW_H3_GIC_SPI_EHCI2 =3D 76,
+ AW_H3_GIC_SPI_OHCI2 =3D 77,
+ AW_H3_GIC_SPI_EHCI3 =3D 78,
+ AW_H3_GIC_SPI_OHCI3 =3D 79,
};
=20
/* Allwinner H3 general constants */
@@ -284,6 +301,33 @@ static void allwinner_h3_realize(DeviceState *dev, Err=
or **errp)
qdev_init_nofail(DEVICE(&s->ccu));
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
=20
+ /* Universal Serial Bus */
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_EHCI0));
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI1],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_EHCI1));
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI2],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_EHCI2));
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI3],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_EHCI3));
+
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI0],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_OHCI0));
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI1],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_OHCI1));
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI2],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_OHCI2));
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI3],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_OHCI3));
+
/* UART0. For future clocktree API: All UARTS are connected to APB2_CL=
K. */
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c
index 5b7991cffe4..3730736540f 100644
--- a/hw/usb/hcd-ehci-sysbus.c
+++ b/hw/usb/hcd-ehci-sysbus.c
@@ -131,6 +131,22 @@ static const TypeInfo ehci_exynos4210_type_info =3D {
.class_init =3D ehci_exynos4210_class_init,
};
=20
+static void ehci_aw_h3_class_init(ObjectClass *oc, void *data)
+{
+ SysBusEHCIClass *sec =3D SYS_BUS_EHCI_CLASS(oc);
+ DeviceClass *dc =3D DEVICE_CLASS(oc);
+
+ sec->capsbase =3D 0x0;
+ sec->opregbase =3D 0x10;
+ set_bit(DEVICE_CATEGORY_USB, dc->categories);
+}
+
+static const TypeInfo ehci_aw_h3_type_info =3D {
+ .name =3D TYPE_AW_H3_EHCI,
+ .parent =3D TYPE_SYS_BUS_EHCI,
+ .class_init =3D ehci_aw_h3_class_init,
+};
+
static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
{
SysBusEHCIClass *sec =3D SYS_BUS_EHCI_CLASS(oc);
@@ -252,6 +268,7 @@ static void ehci_sysbus_register_types(void)
type_register_static(&ehci_type_info);
type_register_static(&ehci_platform_type_info);
type_register_static(&ehci_exynos4210_type_info);
+ type_register_static(&ehci_aw_h3_type_info);
type_register_static(&ehci_tegra2_type_info);
type_register_static(&ehci_ppc4xx_type_info);
type_register_static(&ehci_fusbh200_type_info);
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index fcdc651b73e..f6422d54664 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -304,6 +304,8 @@ config ALLWINNER_H3
select ARM_TIMER
select ARM_GIC
select UNIMP
+ select USB_OHCI
+ select USB_EHCI_SYSBUS
=20
config RASPI
bool
--=20
2.20.1