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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 01/36] hw/intc/armv7m_nvic: Rebuild hflags on reset
Date: Thu, 12 Mar 2020 16:44:24 +0000
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Some of an M-profile CPU's cached hflags state depends on state that's
in our NVIC object. We already do an hflags rebuild when the NVIC
registers are written, but we also need to do this on NVIC reset,
because there's no guarantee that this will happen before the
CPU reset.
This fixes an assertion due to mismatched hflags which happens if
the CPU is reset from inside a HardFault handler.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200303174950.3298-2-peter.maydell@linaro.org
---
hw/intc/armv7m_nvic.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index a62587eb3f0..1ad35e55292 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -2593,6 +2593,12 @@ static void armv7m_nvic_reset(DeviceState *dev)
s->itns[i] =3D true;
}
}
+
+ /*
+ * We updated state that affects the CPU's MMUidx and thus its hflags;
+ * and we can't guarantee that we run before the CPU reset function.
+ */
+ arm_rebuild_hflags(&s->cpu->env);
}
=20
static void nvic_systick_trigger(void *opaque, int n, int level)
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 02/36] target/arm: Update hflags in trans_CPS_v7m()
Date: Thu, 12 Mar 2020 16:44:25 +0000
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For M-profile CPUs, the FAULTMASK value affects the CPU's MMU index
(it changes the NegPri bit). We update the hflags after calls
to the v7m_msr helper in trans_MSR_v7m() but forgot to do so
in trans_CPS_v7m().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200303174950.3298-3-peter.maydell@linaro.org
---
target/arm/translate.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 6259064ea7c..7f0154194cf 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -10590,7 +10590,7 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a)
=20
static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a)
{
- TCGv_i32 tmp, addr;
+ TCGv_i32 tmp, addr, el;
=20
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
return false;
@@ -10613,6 +10613,9 @@ static bool trans_CPS_v7m(DisasContext *s, arg_CPS_=
v7m *a)
gen_helper_v7m_msr(cpu_env, addr, tmp);
tcg_temp_free_i32(addr);
}
+ el =3D tcg_const_i32(s->current_el);
+ gen_helper_rebuild_hflags_m32(cpu_env, el);
+ tcg_temp_free_i32(el);
tcg_temp_free_i32(tmp);
gen_lookup_tb(s);
return true;
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 03/36] target/arm: Recalculate hflags correctly after writes to
CONTROL
Date: Thu, 12 Mar 2020 16:44:26 +0000
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A write to the CONTROL register can change our current EL (by
writing to the nPRIV bit). That means that we can't assume
that s->current_el is still valid in trans_MSR_v7m() when
we try to rebuild the hflags.
Add a new helper rebuild_hflags_m32_newel() which, like the
existing rebuild_hflags_a32_newel(), recalculates the current
EL from scratch, and use it in trans_MSR_v7m().
This fixes an assertion about an hflags mismatch when the
guest changes privilege by writing to CONTROL.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200303174950.3298-4-peter.maydell@linaro.org
---
target/arm/helper.h | 1 +
target/arm/helper.c | 12 ++++++++++++
target/arm/translate.c | 7 +++----
3 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.h b/target/arm/helper.h
index 72eb9e6a1a5..f37b8670a55 100644
--- a/target/arm/helper.h
+++ b/target/arm/helper.h
@@ -90,6 +90,7 @@ DEF_HELPER_4(msr_banked, void, env, i32, i32, i32)
DEF_HELPER_2(get_user_reg, i32, env, i32)
DEF_HELPER_3(set_user_reg, void, env, i32, i32)
=20
+DEF_HELPER_FLAGS_1(rebuild_hflags_m32_newel, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_2(rebuild_hflags_m32, TCG_CALL_NO_RWG, void, env, int)
DEF_HELPER_FLAGS_1(rebuild_hflags_a32_newel, TCG_CALL_NO_RWG, void, env)
DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, int)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f91e5d5345f..bc64077ec7c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12468,6 +12468,18 @@ void arm_rebuild_hflags(CPUARMState *env)
env->hflags =3D rebuild_hflags_internal(env);
}
=20
+/*
+ * If we have triggered a EL state change we can't rely on the
+ * translator having passed it to us, we need to recompute.
+ */
+void HELPER(rebuild_hflags_m32_newel)(CPUARMState *env)
+{
+ int el =3D arm_current_el(env);
+ int fp_el =3D fp_exception_el(env, el);
+ ARMMMUIdx mmu_idx =3D arm_mmu_idx_el(env, el);
+ env->hflags =3D rebuild_hflags_m32(env, fp_el, mmu_idx);
+}
+
void HELPER(rebuild_hflags_m32)(CPUARMState *env, int el)
{
int fp_el =3D fp_exception_el(env, el);
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 7f0154194cf..4715ca0d2ad 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8551,7 +8551,7 @@ static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7=
m *a)
=20
static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7m *a)
{
- TCGv_i32 addr, reg, el;
+ TCGv_i32 addr, reg;
=20
if (!arm_dc_feature(s, ARM_FEATURE_M)) {
return false;
@@ -8561,9 +8561,8 @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7=
m *a)
gen_helper_v7m_msr(cpu_env, addr, reg);
tcg_temp_free_i32(addr);
tcg_temp_free_i32(reg);
- el =3D tcg_const_i32(s->current_el);
- gen_helper_rebuild_hflags_m32(cpu_env, el);
- tcg_temp_free_i32(el);
+ /* If we wrote to CONTROL, the EL might have changed */
+ gen_helper_rebuild_hflags_m32_newel(cpu_env);
gen_lookup_tb(s);
return true;
}
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 04/36] target/arm: Fix some comment typos
Date: Thu, 12 Mar 2020 16:44:27 +0000
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Fix a couple of comment typos.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200303174950.3298-5-peter.maydell@linaro.org
---
target/arm/helper.c | 2 +-
target/arm/translate.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index bc64077ec7c..fc1192d1204 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -12490,7 +12490,7 @@ void HELPER(rebuild_hflags_m32)(CPUARMState *env, i=
nt el)
=20
/*
* If we have triggered a EL state change we can't rely on the
- * translator having passed it too us, we need to recompute.
+ * translator having passed it to us, we need to recompute.
*/
void HELPER(rebuild_hflags_a32_newel)(CPUARMState *env)
{
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 4715ca0d2ad..9f9f4e19e04 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7296,7 +7296,7 @@ static int disas_coproc_insn(DisasContext *s, uint32_=
t insn)
=20
if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) {
/*
- * A write to any coprocessor regiser that ends a TB
+ * A write to any coprocessor register that ends a TB
* must rebuild the hflags for the next TB.
*/
TCGv_i32 tcg_el =3D tcg_const_i32(s->current_el);
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 05/36] aspeed/smc: Add some tracing
Date: Thu, 12 Mar 2020 16:44:28 +0000
Message-Id: <20200312164459.25924-6-peter.maydell@linaro.org>
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From: C=C3=A9dric Le Goater <clg@kaod.org>
Signed-off-by: C=C3=A9dric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Message-id: 20200206112645.21275-2-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
Makefile.objs | 1 +
hw/ssi/aspeed_smc.c | 17 +++++++++++++++++
hw/ssi/trace-events | 9 +++++++++
3 files changed, 27 insertions(+)
create mode 100644 hw/ssi/trace-events
diff --git a/Makefile.objs b/Makefile.objs
index 40d3a1696cb..a7c967633ac 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -175,6 +175,7 @@ trace-events-subdirs +=3D hw/scsi
trace-events-subdirs +=3D hw/sd
trace-events-subdirs +=3D hw/sparc
trace-events-subdirs +=3D hw/sparc64
+trace-events-subdirs +=3D hw/ssi
trace-events-subdirs +=3D hw/timer
trace-events-subdirs +=3D hw/tpm
trace-events-subdirs +=3D hw/usb
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index 23c8d2f0624..e5621bf728c 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -31,6 +31,7 @@
#include "qapi/error.h"
#include "exec/address-spaces.h"
#include "qemu/units.h"
+#include "trace.h"
=20
#include "hw/irq.h"
#include "hw/qdev-properties.h"
@@ -513,6 +514,8 @@ static void aspeed_smc_flash_set_segment(AspeedSMCState=
*s, int cs,
=20
s->ctrl->reg_to_segment(s, new, &seg);
=20
+ trace_aspeed_smc_flash_set_segment(cs, new, seg.addr, seg.addr + seg.s=
ize);
+
/* The start address of CS0 is read-only */
if (cs =3D=3D 0 && seg.addr !=3D s->ctrl->flash_window_base) {
qemu_log_mask(LOG_GUEST_ERROR,
@@ -753,6 +756,8 @@ static uint64_t aspeed_smc_flash_read(void *opaque, hwa=
ddr addr, unsigned size)
__func__, aspeed_smc_flash_mode(fl));
}
=20
+ trace_aspeed_smc_flash_read(fl->id, addr, size, ret,
+ aspeed_smc_flash_mode(fl));
return ret;
}
=20
@@ -808,6 +813,9 @@ static bool aspeed_smc_do_snoop(AspeedSMCFlash *fl, ui=
nt64_t data,
AspeedSMCState *s =3D fl->controller;
uint8_t addr_width =3D aspeed_smc_flash_is_4byte(fl) ? 4 : 3;
=20
+ trace_aspeed_smc_do_snoop(fl->id, s->snoop_index, s->snoop_dummies,
+ (uint8_t) data & 0xff);
+
if (s->snoop_index =3D=3D SNOOP_OFF) {
return false; /* Do nothing */
=20
@@ -858,6 +866,9 @@ static void aspeed_smc_flash_write(void *opaque, hwaddr=
addr, uint64_t data,
AspeedSMCState *s =3D fl->controller;
int i;
=20
+ trace_aspeed_smc_flash_write(fl->id, addr, size, data,
+ aspeed_smc_flash_mode(fl));
+
if (!aspeed_smc_is_writable(fl)) {
qemu_log_mask(LOG_GUEST_ERROR, "%s: flash is not writable at 0x%"
HWADDR_PRIx "\n", __func__, addr);
@@ -972,6 +983,9 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr ad=
dr, unsigned int size)
(s->ctrl->has_dma && addr =3D=3D R_DMA_CHECKSUM) ||
(addr >=3D R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves=
) ||
(addr >=3D s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves))=
{
+
+ trace_aspeed_smc_read(addr, size, s->regs[addr]);
+
return s->regs[addr];
} else {
qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\=
n",
@@ -1091,6 +1105,7 @@ static void aspeed_smc_dma_checksum(AspeedSMCState *s)
__func__, s->regs[R_DMA_FLASH_ADDR]);
return;
}
+ trace_aspeed_smc_dma_checksum(s->regs[R_DMA_FLASH_ADDR], data);
=20
/*
* When the DMA is on-going, the DMA registers are updated
@@ -1225,6 +1240,8 @@ static void aspeed_smc_write(void *opaque, hwaddr add=
r, uint64_t data,
=20
addr >>=3D 2;
=20
+ trace_aspeed_smc_write(addr, size, data);
+
if (addr =3D=3D s->r_conf ||
(addr >=3D s->r_timings &&
addr < s->r_timings + s->ctrl->nregs_timings) ||
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
new file mode 100644
index 00000000000..ffe531a500a
--- /dev/null
+++ b/hw/ssi/trace-events
@@ -0,0 +1,9 @@
+# aspeed_smc.c
+
+aspeed_smc_flash_set_segment(int cs, uint64_t reg, uint64_t start, uint64_=
t end) "CS%d segreg=3D0x%"PRIx64" [ 0x%"PRIx64" - 0x%"PRIx64" ]"
+aspeed_smc_flash_read(int cs, uint64_t addr, uint32_t size, uint64_t data=
, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d"
+aspeed_smc_do_snoop(int cs, int index, int dummies, int data) "CS%d index:=
0x%x dummies:%d data:0x%x"
+aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t size, uint64_t dat=
a, int mode) "CS%d @0x%" PRIx64 " size %u: 0x%" PRIx64" mode:%d"
+aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx6=
4 " size %u: 0x%" PRIx64
+aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x"
+aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx=
64 " size %u: 0x%" PRIx64
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 06/36] aspeed/smc: Fix User mode select/unselect scheme
Date: Thu, 12 Mar 2020 16:44:29 +0000
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From: C=C3=A9dric Le Goater <clg@kaod.org>
The Aspeed SMC Controller can operate in different modes : Read, Fast
Read, Write and User modes. When the User mode is configured, it
selects automatically the SPI slave device until the CE_STOP_ACTIVE
bit is set to 1. When any other modes are configured the device is
unselected. The HW logic handles the chip select automatically when
the flash is accessed through its AHB window.
When configuring the CEx Control Register, the User mode logic to
select and unselect the slave is incorrect and data corruption can be
seen on machines using two chips, witherspoon and romulus.
Rework the handler setting the CEx Control Register to fix this issue.
Fixes: 7c1c69bca43c ("ast2400: add SMC controllers (FMC and SPI)")
Signed-off-by: C=C3=A9dric Le Goater <clg@kaod.org>
Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Message-id: 20200206112645.21275-3-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/ssi/aspeed_smc.c | 39 +++++++++++++++++++++++----------------
hw/ssi/trace-events | 1 +
2 files changed, 24 insertions(+), 16 deletions(-)
diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c
index e5621bf728c..32be2a02b0e 100644
--- a/hw/ssi/aspeed_smc.c
+++ b/hw/ssi/aspeed_smc.c
@@ -639,27 +639,23 @@ static inline int aspeed_smc_flash_is_4byte(const Asp=
eedSMCFlash *fl)
}
}
=20
-static inline bool aspeed_smc_is_ce_stop_active(const AspeedSMCFlash *fl)
+static void aspeed_smc_flash_do_select(AspeedSMCFlash *fl, bool unselect)
{
- const AspeedSMCState *s =3D fl->controller;
+ AspeedSMCState *s =3D fl->controller;
=20
- return s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE;
+ trace_aspeed_smc_flash_select(fl->id, unselect ? "un" : "");
+
+ qemu_set_irq(s->cs_lines[fl->id], unselect);
}
=20
static void aspeed_smc_flash_select(AspeedSMCFlash *fl)
{
- AspeedSMCState *s =3D fl->controller;
-
- s->regs[s->r_ctrl0 + fl->id] &=3D ~CTRL_CE_STOP_ACTIVE;
- qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
+ aspeed_smc_flash_do_select(fl, false);
}
=20
static void aspeed_smc_flash_unselect(AspeedSMCFlash *fl)
{
- AspeedSMCState *s =3D fl->controller;
-
- s->regs[s->r_ctrl0 + fl->id] |=3D CTRL_CE_STOP_ACTIVE;
- qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
+ aspeed_smc_flash_do_select(fl, true);
}
=20
static uint32_t aspeed_smc_check_segment_addr(const AspeedSMCFlash *fl,
@@ -911,13 +907,25 @@ static const MemoryRegionOps aspeed_smc_flash_ops =3D=
{
},
};
=20
-static void aspeed_smc_flash_update_cs(AspeedSMCFlash *fl)
+static void aspeed_smc_flash_update_ctrl(AspeedSMCFlash *fl, uint32_t valu=
e)
{
AspeedSMCState *s =3D fl->controller;
+ bool unselect;
=20
- s->snoop_index =3D aspeed_smc_is_ce_stop_active(fl) ? SNOOP_OFF : SNOO=
P_START;
+ /* User mode selects the CS, other modes unselect */
+ unselect =3D (value & CTRL_CMD_MODE_MASK) !=3D CTRL_USERMODE;
=20
- qemu_set_irq(s->cs_lines[fl->id], aspeed_smc_is_ce_stop_active(fl));
+ /* A change of CTRL_CE_STOP_ACTIVE from 0 to 1, unselects the CS */
+ if (!(s->regs[s->r_ctrl0 + fl->id] & CTRL_CE_STOP_ACTIVE) &&
+ value & CTRL_CE_STOP_ACTIVE) {
+ unselect =3D true;
+ }
+
+ s->regs[s->r_ctrl0 + fl->id] =3D value;
+
+ s->snoop_index =3D unselect ? SNOOP_OFF : SNOOP_START;
+
+ aspeed_smc_flash_do_select(fl, unselect);
}
=20
static void aspeed_smc_reset(DeviceState *d)
@@ -1249,8 +1257,7 @@ static void aspeed_smc_write(void *opaque, hwaddr add=
r, uint64_t data,
s->regs[addr] =3D value;
} else if (addr >=3D s->r_ctrl0 && addr < s->r_ctrl0 + s->num_cs) {
int cs =3D addr - s->r_ctrl0;
- s->regs[addr] =3D value;
- aspeed_smc_flash_update_cs(&s->flashes[cs]);
+ aspeed_smc_flash_update_ctrl(&s->flashes[cs], value);
} else if (addr >=3D R_SEG_ADDR0 &&
addr < R_SEG_ADDR0 + s->ctrl->max_slaves) {
int cs =3D addr - R_SEG_ADDR0;
diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events
index ffe531a500a..0a70629801a 100644
--- a/hw/ssi/trace-events
+++ b/hw/ssi/trace-events
@@ -7,3 +7,4 @@ aspeed_smc_flash_write(int cs, uint64_t addr, uint32_t siz=
e, uint64_t data, int
aspeed_smc_read(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx6=
4 " size %u: 0x%" PRIx64
aspeed_smc_dma_checksum(uint32_t addr, uint32_t data) "0x%08x: 0x%08x"
aspeed_smc_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PRIx=
64 " size %u: 0x%" PRIx64
+aspeed_smc_flash_select(int cs, const char *prefix) "CS%d %sselect"
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 07/36] target/arm: Check addresses for disabled regimes
Date: Thu, 12 Mar 2020 16:44:30 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
We fail to validate the upper bits of a virtual address on a
translation disabled regime, as per AArch64.TranslateAddressS1Off.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200308012946.16303-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 35 ++++++++++++++++++++++++++++++++++-
1 file changed, 34 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index fc1192d1204..b61ee73d18a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11780,7 +11780,40 @@ bool get_phys_addr(CPUARMState *env, target_ulong =
address,
/* Definitely a real MMU, not an MPU */
=20
if (regime_translation_disabled(env, mmu_idx)) {
- /* MMU disabled. */
+ /*
+ * MMU disabled. S1 addresses within aa64 translation regimes are
+ * still checked for bounds -- see AArch64.TranslateAddressS1Off.
+ */
+ if (mmu_idx !=3D ARMMMUIdx_Stage2) {
+ int r_el =3D regime_el(env, mmu_idx);
+ if (arm_el_is_aa64(env, r_el)) {
+ int pamax =3D arm_pamax(env_archcpu(env));
+ uint64_t tcr =3D env->cp15.tcr_el[r_el].raw_tcr;
+ int addrtop, tbi;
+
+ tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx);
+ if (access_type =3D=3D MMU_INST_FETCH) {
+ tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx);
+ }
+ tbi =3D (tbi >> extract64(address, 55, 1)) & 1;
+ addrtop =3D (tbi ? 55 : 63);
+
+ if (extract64(address, pamax, addrtop - pamax + 1) !=3D 0)=
{
+ fi->type =3D ARMFault_AddressSize;
+ fi->level =3D 0;
+ fi->stage2 =3D false;
+ return 1;
+ }
+
+ /*
+ * When TBI is disabled, we've just validated that all of =
the
+ * bits above PAMax are zero, so logically we only need to
+ * clear the top byte for TBI. But it's clearer to follow
+ * the pseudocode set of addrdesc.paddress.
+ */
+ address =3D extract64(address, 0, 52);
+ }
+ }
*phys_ptr =3D address;
*prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC;
*page_size =3D TARGET_PAGE_SIZE;
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 08/36] target/arm: Disable clean_data_tbi for system mode
Date: Thu, 12 Mar 2020 16:44:31 +0000
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From: Richard Henderson <richard.henderson@linaro.org>
We must include the tag in the FAR_ELx register when raising
an addressing exception. Which means that we should not clear
out the tag during translation.
We cannot at present comply with this for user mode, so we
retain the clean_data_tbi function for the moment, though it
no longer does what it says on the tin for system mode. This
function is to be replaced with MTE, so don't worry about the
slight misnaming.
Buglink: https://bugs.launchpad.net/qemu/+bug/1867072
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200308012946.16303-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-a64.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index fefe8af7f52..8fffb52203d 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -228,7 +228,18 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 s=
rc)
static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr)
{
TCGv_i64 clean =3D new_tmp_a64(s);
+ /*
+ * In order to get the correct value in the FAR_ELx register,
+ * we must present the memory subsystem with the "dirty" address
+ * including the TBI. In system mode we can make this work via
+ * the TLB, dropping the TBI during translation. But for user-only
+ * mode we don't have that option, and must remove the top byte now.
+ */
+#ifdef CONFIG_USER_ONLY
gen_top_byte_ignore(s, clean, addr, s->tbid);
+#else
+ tcg_gen_mov_i64(clean, addr);
+#endif
return clean;
}
=20
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 09/36] hw/arm/cubieboard: make sure SOC object isn't leaked
Date: Thu, 12 Mar 2020 16:44:32 +0000
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From: Igor Mammedov <imammedo@redhat.com>
SOC object returned by object_new() is leaked in current code.
Set SOC parent explicitly to board and then unref to SOC object
to make sure that refererence returned by object_new() is taken
care of.
The SOC object will be kept alive by its parent (machine) and
will be automatically freed when MachineState is destroyed.
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reported-by: Andrew Jones <drjones@redhat.com>
Tested-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id: 20200303091254.22373-1-imammedo@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/cubieboard.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index 871b1beef4c..d791817646b 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/cubieboard.c
@@ -54,6 +54,9 @@ static void cubieboard_init(MachineState *machine)
}
=20
a10 =3D AW_A10(object_new(TYPE_AW_A10));
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(a10),
+ &error_abort);
+ object_unref(OBJECT(a10));
=20
object_property_set_int(OBJECT(&a10->emac), 1, "phy-addr", &err);
if (err !=3D NULL) {
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 10/36] hw/arm/fsl-imx25: Wire up eSDHC controllers
Date: Thu, 12 Mar 2020 16:44:33 +0000
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From: Guenter Roeck <linux@roeck-us.net>
Wire up eSDHC controllers in fsl-imx25. For imx25-pdk, connect drives
provided on the command line to available eSDHC controllers.
This patch enables booting the imx25-pdk emulation from SD card.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20200310215146.19688-2-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: made commit subject consistent with other patch]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/fsl-imx25.h | 9 +++++++++
hw/arm/fsl-imx25.c | 32 ++++++++++++++++++++++++++++++++
hw/arm/imx25_pdk.c | 16 ++++++++++++++++
3 files changed, 57 insertions(+)
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
index 1c86bb55fbd..4e2d4868cda 100644
--- a/include/hw/arm/fsl-imx25.h
+++ b/include/hw/arm/fsl-imx25.h
@@ -27,6 +27,7 @@
#include "hw/misc/imx_rngc.h"
#include "hw/i2c/imx_i2c.h"
#include "hw/gpio/imx_gpio.h"
+#include "hw/sd/sdhci.h"
#include "exec/memory.h"
#include "target/arm/cpu.h"
=20
@@ -38,6 +39,7 @@
#define FSL_IMX25_NUM_EPITS 2
#define FSL_IMX25_NUM_I2CS 3
#define FSL_IMX25_NUM_GPIOS 4
+#define FSL_IMX25_NUM_ESDHCS 2
=20
typedef struct FslIMX25State {
/*< private >*/
@@ -54,6 +56,7 @@ typedef struct FslIMX25State {
IMXRNGCState rngc;
IMXI2CState i2c[FSL_IMX25_NUM_I2CS];
IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
+ SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS];
MemoryRegion rom[2];
MemoryRegion iram;
MemoryRegion iram_alias;
@@ -215,6 +218,10 @@ typedef struct FslIMX25State {
#define FSL_IMX25_GPIO3_SIZE 0x4000
#define FSL_IMX25_RNGC_ADDR 0x53FB0000
#define FSL_IMX25_RNGC_SIZE 0x4000
+#define FSL_IMX25_ESDHC1_ADDR 0x53FB4000
+#define FSL_IMX25_ESDHC1_SIZE 0x4000
+#define FSL_IMX25_ESDHC2_ADDR 0x53FB8000
+#define FSL_IMX25_ESDHC2_SIZE 0x4000
#define FSL_IMX25_GPIO1_ADDR 0x53FCC000
#define FSL_IMX25_GPIO1_SIZE 0x4000
#define FSL_IMX25_GPIO2_ADDR 0x53FD0000
@@ -250,5 +257,7 @@ typedef struct FslIMX25State {
#define FSL_IMX25_GPIO2_IRQ 51
#define FSL_IMX25_GPIO3_IRQ 16
#define FSL_IMX25_GPIO4_IRQ 23
+#define FSL_IMX25_ESDHC1_IRQ 9
+#define FSL_IMX25_ESDHC2_IRQ 8
=20
#endif /* FSL_IMX25_H */
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
index da3471b3953..f977c42426b 100644
--- a/hw/arm/fsl-imx25.c
+++ b/hw/arm/fsl-imx25.c
@@ -31,6 +31,8 @@
#include "hw/qdev-properties.h"
#include "chardev/char.h"
=20
+#define IMX25_ESDHC_CAPABILITIES 0x07e20000
+
static void fsl_imx25_init(Object *obj)
{
FslIMX25State *s =3D FSL_IMX25(obj);
@@ -74,6 +76,11 @@ static void fsl_imx25_init(Object *obj)
sysbus_init_child_obj(obj, "gpio[*]", &s->gpio[i], sizeof(s->gpio[=
i]),
TYPE_IMX_GPIO);
}
+
+ for (i =3D 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
+ sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdh=
c[i]),
+ TYPE_IMX_USDHC);
+ }
}
=20
static void fsl_imx25_realize(DeviceState *dev, Error **errp)
@@ -246,6 +253,31 @@ static void fsl_imx25_realize(DeviceState *dev, Error =
**errp)
gpio_table[i].irq));
}
=20
+ /* Initialize all SDHC */
+ for (i =3D 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
+ static const struct {
+ hwaddr addr;
+ unsigned int irq;
+ } esdhc_table[FSL_IMX25_NUM_ESDHCS] =3D {
+ { FSL_IMX25_ESDHC1_ADDR, FSL_IMX25_ESDHC1_IRQ },
+ { FSL_IMX25_ESDHC2_ADDR, FSL_IMX25_ESDHC2_IRQ },
+ };
+
+ object_property_set_uint(OBJECT(&s->esdhc[i]), 2, "sd-spec-version=
",
+ &err);
+ object_property_set_uint(OBJECT(&s->esdhc[i]), IMX25_ESDHC_CAPABIL=
ITIES,
+ "capareg", &err);
+ object_property_set_bool(OBJECT(&s->esdhc[i]), true, "realized", &=
err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->esdhc[i]), 0, esdhc_table[i].ad=
dr);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->esdhc[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->avic),
+ esdhc_table[i].irq));
+ }
+
/* initialize 2 x 16 KB ROM */
memory_region_init_rom(&s->rom[0], NULL,
"imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c
index 26713d9a7e7..b3ca82bafa7 100644
--- a/hw/arm/imx25_pdk.c
+++ b/hw/arm/imx25_pdk.c
@@ -26,6 +26,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
#include "cpu.h"
+#include "hw/qdev-properties.h"
#include "hw/arm/fsl-imx25.h"
#include "hw/boards.h"
#include "qemu/error-report.h"
@@ -120,6 +121,21 @@ static void imx25_pdk_init(MachineState *machine)
imx25_pdk_binfo.board_id =3D 1771,
imx25_pdk_binfo.nb_cpus =3D 1;
=20
+ for (i =3D 0; i < FSL_IMX25_NUM_ESDHCS; i++) {
+ BusState *bus;
+ DeviceState *carddev;
+ DriveInfo *di;
+ BlockBackend *blk;
+
+ di =3D drive_get_next(IF_SD);
+ blk =3D di ? blk_by_legacy_dinfo(di) : NULL;
+ bus =3D qdev_get_child_bus(DEVICE(&s->soc.esdhc[i]), "sd-bus");
+ carddev =3D qdev_create(bus, TYPE_SD_CARD);
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
+ object_property_set_bool(OBJECT(carddev), true,
+ "realized", &error_fatal);
+ }
+
/*
* We test explicitly for qtest here as it is not done (yet?) in
* arm_load_kernel(). Without this the "make check" command would
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 11/36] hw/arm/fsl-imx25: Wire up USB controllers
Date: Thu, 12 Mar 2020 16:44:34 +0000
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From: Guenter Roeck <linux@roeck-us.net>
i.MX25 supports two USB controllers. Let's wire them up.
With this patch, imx25-pdk can boot from both USB ports.
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Message-id: 20200310215146.19688-3-linux@roeck-us.net
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/fsl-imx25.h | 9 +++++++++
hw/arm/fsl-imx25.c | 24 ++++++++++++++++++++++++
2 files changed, 33 insertions(+)
diff --git a/include/hw/arm/fsl-imx25.h b/include/hw/arm/fsl-imx25.h
index 4e2d4868cda..5e196bbf059 100644
--- a/include/hw/arm/fsl-imx25.h
+++ b/include/hw/arm/fsl-imx25.h
@@ -28,6 +28,7 @@
#include "hw/i2c/imx_i2c.h"
#include "hw/gpio/imx_gpio.h"
#include "hw/sd/sdhci.h"
+#include "hw/usb/chipidea.h"
#include "exec/memory.h"
#include "target/arm/cpu.h"
=20
@@ -40,6 +41,7 @@
#define FSL_IMX25_NUM_I2CS 3
#define FSL_IMX25_NUM_GPIOS 4
#define FSL_IMX25_NUM_ESDHCS 2
+#define FSL_IMX25_NUM_USBS 2
=20
typedef struct FslIMX25State {
/*< private >*/
@@ -57,6 +59,7 @@ typedef struct FslIMX25State {
IMXI2CState i2c[FSL_IMX25_NUM_I2CS];
IMXGPIOState gpio[FSL_IMX25_NUM_GPIOS];
SDHCIState esdhc[FSL_IMX25_NUM_ESDHCS];
+ ChipideaState usb[FSL_IMX25_NUM_USBS];
MemoryRegion rom[2];
MemoryRegion iram;
MemoryRegion iram_alias;
@@ -226,6 +229,10 @@ typedef struct FslIMX25State {
#define FSL_IMX25_GPIO1_SIZE 0x4000
#define FSL_IMX25_GPIO2_ADDR 0x53FD0000
#define FSL_IMX25_GPIO2_SIZE 0x4000
+#define FSL_IMX25_USB1_ADDR 0x53FF4000
+#define FSL_IMX25_USB1_SIZE 0x0200
+#define FSL_IMX25_USB2_ADDR 0x53FF4400
+#define FSL_IMX25_USB2_SIZE 0x0200
#define FSL_IMX25_AVIC_ADDR 0x68000000
#define FSL_IMX25_AVIC_SIZE 0x4000
#define FSL_IMX25_IRAM_ADDR 0x78000000
@@ -259,5 +266,7 @@ typedef struct FslIMX25State {
#define FSL_IMX25_GPIO4_IRQ 23
#define FSL_IMX25_ESDHC1_IRQ 9
#define FSL_IMX25_ESDHC2_IRQ 8
+#define FSL_IMX25_USB1_IRQ 37
+#define FSL_IMX25_USB2_IRQ 35
=20
#endif /* FSL_IMX25_H */
diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c
index f977c42426b..a3f829f4366 100644
--- a/hw/arm/fsl-imx25.c
+++ b/hw/arm/fsl-imx25.c
@@ -81,6 +81,12 @@ static void fsl_imx25_init(Object *obj)
sysbus_init_child_obj(obj, "sdhc[*]", &s->esdhc[i], sizeof(s->esdh=
c[i]),
TYPE_IMX_USDHC);
}
+
+ for (i =3D 0; i < FSL_IMX25_NUM_USBS; i++) {
+ sysbus_init_child_obj(obj, "usb[*]", &s->usb[i], sizeof(s->usb[i]),
+ TYPE_CHIPIDEA);
+ }
+
}
=20
static void fsl_imx25_realize(DeviceState *dev, Error **errp)
@@ -278,6 +284,24 @@ static void fsl_imx25_realize(DeviceState *dev, Error =
**errp)
esdhc_table[i].irq));
}
=20
+ /* USB */
+ for (i =3D 0; i < FSL_IMX25_NUM_USBS; i++) {
+ static const struct {
+ hwaddr addr;
+ unsigned int irq;
+ } usb_table[FSL_IMX25_NUM_USBS] =3D {
+ { FSL_IMX25_USB1_ADDR, FSL_IMX25_USB1_IRQ },
+ { FSL_IMX25_USB2_ADDR, FSL_IMX25_USB2_IRQ },
+ };
+
+ object_property_set_bool(OBJECT(&s->usb[i]), true, "realized",
+ &error_abort);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->usb[i]), 0, usb_table[i].addr);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->usb[i]), 0,
+ qdev_get_gpio_in(DEVICE(&s->avic),
+ usb_table[i].irq));
+ }
+
/* initialize 2 x 16 KB ROM */
memory_region_init_rom(&s->rom[0], NULL,
"imx25.rom0", FSL_IMX25_ROM0_SIZE, &err);
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 12/36] hw/arm: add Allwinner H3 System-on-Chip
Date: Thu, 12 Mar 2020 16:44:35 +0000
Message-Id: <20200312164459.25924-13-peter.maydell@linaro.org>
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From: Niek Linnenbank <nieklinnenbank@gmail.com>
The Allwinner H3 is a System on Chip containing four ARM Cortex A7
processor cores. Features and specifications include DDR2/DDR3 memory,
SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
various I/O modules. This commit adds support for the Allwinner H3
System on Chip.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Message-id: 20200311221854.30370-2-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/Makefile.objs | 1 +
include/hw/arm/allwinner-h3.h | 106 +++++++++++
hw/arm/allwinner-h3.c | 327 ++++++++++++++++++++++++++++++++
MAINTAINERS | 7 +
default-configs/arm-softmmu.mak | 1 +
hw/arm/Kconfig | 8 +
6 files changed, 450 insertions(+)
create mode 100644 include/hw/arm/allwinner-h3.h
create mode 100644 hw/arm/allwinner-h3.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index 336f6dd3749..ae577e875fd 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -35,6 +35,7 @@ obj-$(CONFIG_DIGIC) +=3D digic.o
obj-$(CONFIG_OMAP) +=3D omap1.o omap2.o
obj-$(CONFIG_STRONGARM) +=3D strongarm.o
obj-$(CONFIG_ALLWINNER_A10) +=3D allwinner-a10.o cubieboard.o
+obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o
obj-$(CONFIG_RASPI) +=3D bcm2835_peripherals.o bcm2836.o raspi.o
obj-$(CONFIG_STM32F205_SOC) +=3D stm32f205_soc.o
obj-$(CONFIG_STM32F405_SOC) +=3D stm32f405_soc.o
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
new file mode 100644
index 00000000000..2aac9b78ecf
--- /dev/null
+++ b/include/hw/arm/allwinner-h3.h
@@ -0,0 +1,106 @@
+/*
+ * Allwinner H3 System on Chip emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * The Allwinner H3 is a System on Chip containing four ARM Cortex A7
+ * processor cores. Features and specifications include DDR2/DDR3 memory,
+ * SD/MMC storage cards, 10/100/1000Mbit Ethernet, USB 2.0, HDMI and
+ * various I/O modules.
+ *
+ * This implementation is based on the following datasheet:
+ *
+ * https://linux-sunxi.org/File:Allwinner_H3_Datasheet_V1.2.pdf
+ *
+ * The latest datasheet and more info can be found on the Linux Sunxi wiki:
+ *
+ * https://linux-sunxi.org/H3
+ */
+
+#ifndef HW_ARM_ALLWINNER_H3_H
+#define HW_ARM_ALLWINNER_H3_H
+
+#include "qom/object.h"
+#include "hw/arm/boot.h"
+#include "hw/timer/allwinner-a10-pit.h"
+#include "hw/intc/arm_gic.h"
+#include "target/arm/cpu.h"
+
+/**
+ * Allwinner H3 device list
+ *
+ * This enumeration is can be used refer to a particular device in the
+ * Allwinner H3 SoC. For example, the physical memory base address for
+ * each device can be found in the AwH3State object in the memmap member
+ * using the device enum value as index.
+ *
+ * @see AwH3State
+ */
+enum {
+ AW_H3_SRAM_A1,
+ AW_H3_SRAM_A2,
+ AW_H3_SRAM_C,
+ AW_H3_PIT,
+ AW_H3_UART0,
+ AW_H3_UART1,
+ AW_H3_UART2,
+ AW_H3_UART3,
+ AW_H3_GIC_DIST,
+ AW_H3_GIC_CPU,
+ AW_H3_GIC_HYP,
+ AW_H3_GIC_VCPU,
+ AW_H3_SDRAM
+};
+
+/** Total number of CPU cores in the H3 SoC */
+#define AW_H3_NUM_CPUS (4)
+
+/**
+ * Allwinner H3 object model
+ * @{
+ */
+
+/** Object type for the Allwinner H3 SoC */
+#define TYPE_AW_H3 "allwinner-h3"
+
+/** Convert input object to Allwinner H3 state object */
+#define AW_H3(obj) OBJECT_CHECK(AwH3State, (obj), TYPE_AW_H3)
+
+/** @} */
+
+/**
+ * Allwinner H3 object
+ *
+ * This struct contains the state of all the devices
+ * which are currently emulated by the H3 SoC code.
+ */
+typedef struct AwH3State {
+ /*< private >*/
+ DeviceState parent_obj;
+ /*< public >*/
+
+ ARMCPU cpus[AW_H3_NUM_CPUS];
+ const hwaddr *memmap;
+ AwA10PITState timer;
+ GICState gic;
+ MemoryRegion sram_a1;
+ MemoryRegion sram_a2;
+ MemoryRegion sram_c;
+} AwH3State;
+
+#endif /* HW_ARM_ALLWINNER_H3_H */
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
new file mode 100644
index 00000000000..7958f376852
--- /dev/null
+++ b/hw/arm/allwinner-h3.c
@@ -0,0 +1,327 @@
+/*
+ * Allwinner H3 System on Chip emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "exec/address-spaces.h"
+#include "qapi/error.h"
+#include "qemu/error-report.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+#include "hw/qdev-core.h"
+#include "cpu.h"
+#include "hw/sysbus.h"
+#include "hw/char/serial.h"
+#include "hw/misc/unimp.h"
+#include "sysemu/sysemu.h"
+#include "hw/arm/allwinner-h3.h"
+
+/* Memory map */
+const hwaddr allwinner_h3_memmap[] =3D {
+ [AW_H3_SRAM_A1] =3D 0x00000000,
+ [AW_H3_SRAM_A2] =3D 0x00044000,
+ [AW_H3_SRAM_C] =3D 0x00010000,
+ [AW_H3_PIT] =3D 0x01c20c00,
+ [AW_H3_UART0] =3D 0x01c28000,
+ [AW_H3_UART1] =3D 0x01c28400,
+ [AW_H3_UART2] =3D 0x01c28800,
+ [AW_H3_UART3] =3D 0x01c28c00,
+ [AW_H3_GIC_DIST] =3D 0x01c81000,
+ [AW_H3_GIC_CPU] =3D 0x01c82000,
+ [AW_H3_GIC_HYP] =3D 0x01c84000,
+ [AW_H3_GIC_VCPU] =3D 0x01c86000,
+ [AW_H3_SDRAM] =3D 0x40000000
+};
+
+/* List of unimplemented devices */
+struct AwH3Unimplemented {
+ const char *device_name;
+ hwaddr base;
+ hwaddr size;
+} unimplemented[] =3D {
+ { "d-engine", 0x01000000, 4 * MiB },
+ { "d-inter", 0x01400000, 128 * KiB },
+ { "syscon", 0x01c00000, 4 * KiB },
+ { "dma", 0x01c02000, 4 * KiB },
+ { "nfdc", 0x01c03000, 4 * KiB },
+ { "ts", 0x01c06000, 4 * KiB },
+ { "keymem", 0x01c0b000, 4 * KiB },
+ { "lcd0", 0x01c0c000, 4 * KiB },
+ { "lcd1", 0x01c0d000, 4 * KiB },
+ { "ve", 0x01c0e000, 4 * KiB },
+ { "mmc0", 0x01c0f000, 4 * KiB },
+ { "mmc1", 0x01c10000, 4 * KiB },
+ { "mmc2", 0x01c11000, 4 * KiB },
+ { "sid", 0x01c14000, 1 * KiB },
+ { "crypto", 0x01c15000, 4 * KiB },
+ { "msgbox", 0x01c17000, 4 * KiB },
+ { "spinlock", 0x01c18000, 4 * KiB },
+ { "usb0-otg", 0x01c19000, 4 * KiB },
+ { "usb0-phy", 0x01c1a000, 4 * KiB },
+ { "usb1-phy", 0x01c1b000, 4 * KiB },
+ { "usb2-phy", 0x01c1c000, 4 * KiB },
+ { "usb3-phy", 0x01c1d000, 4 * KiB },
+ { "smc", 0x01c1e000, 4 * KiB },
+ { "ccu", 0x01c20000, 1 * KiB },
+ { "pio", 0x01c20800, 1 * KiB },
+ { "owa", 0x01c21000, 1 * KiB },
+ { "pwm", 0x01c21400, 1 * KiB },
+ { "keyadc", 0x01c21800, 1 * KiB },
+ { "pcm0", 0x01c22000, 1 * KiB },
+ { "pcm1", 0x01c22400, 1 * KiB },
+ { "pcm2", 0x01c22800, 1 * KiB },
+ { "audio", 0x01c22c00, 2 * KiB },
+ { "smta", 0x01c23400, 1 * KiB },
+ { "ths", 0x01c25000, 1 * KiB },
+ { "uart0", 0x01c28000, 1 * KiB },
+ { "uart1", 0x01c28400, 1 * KiB },
+ { "uart2", 0x01c28800, 1 * KiB },
+ { "uart3", 0x01c28c00, 1 * KiB },
+ { "twi0", 0x01c2ac00, 1 * KiB },
+ { "twi1", 0x01c2b000, 1 * KiB },
+ { "twi2", 0x01c2b400, 1 * KiB },
+ { "scr", 0x01c2c400, 1 * KiB },
+ { "emac", 0x01c30000, 64 * KiB },
+ { "gpu", 0x01c40000, 64 * KiB },
+ { "hstmr", 0x01c60000, 4 * KiB },
+ { "dramcom", 0x01c62000, 4 * KiB },
+ { "dramctl0", 0x01c63000, 4 * KiB },
+ { "dramphy0", 0x01c65000, 4 * KiB },
+ { "spi0", 0x01c68000, 4 * KiB },
+ { "spi1", 0x01c69000, 4 * KiB },
+ { "csi", 0x01cb0000, 320 * KiB },
+ { "tve", 0x01e00000, 64 * KiB },
+ { "hdmi", 0x01ee0000, 128 * KiB },
+ { "rtc", 0x01f00000, 1 * KiB },
+ { "r_timer", 0x01f00800, 1 * KiB },
+ { "r_intc", 0x01f00c00, 1 * KiB },
+ { "r_wdog", 0x01f01000, 1 * KiB },
+ { "r_prcm", 0x01f01400, 1 * KiB },
+ { "r_twd", 0x01f01800, 1 * KiB },
+ { "r_cpucfg", 0x01f01c00, 1 * KiB },
+ { "r_cir-rx", 0x01f02000, 1 * KiB },
+ { "r_twi", 0x01f02400, 1 * KiB },
+ { "r_uart", 0x01f02800, 1 * KiB },
+ { "r_pio", 0x01f02c00, 1 * KiB },
+ { "r_pwm", 0x01f03800, 1 * KiB },
+ { "core-dbg", 0x3f500000, 128 * KiB },
+ { "tsgen-ro", 0x3f506000, 4 * KiB },
+ { "tsgen-ctl", 0x3f507000, 4 * KiB },
+ { "ddr-mem", 0x40000000, 2 * GiB },
+ { "n-brom", 0xffff0000, 32 * KiB },
+ { "s-brom", 0xffff0000, 64 * KiB }
+};
+
+/* Per Processor Interrupts */
+enum {
+ AW_H3_GIC_PPI_MAINT =3D 9,
+ AW_H3_GIC_PPI_HYPTIMER =3D 10,
+ AW_H3_GIC_PPI_VIRTTIMER =3D 11,
+ AW_H3_GIC_PPI_SECTIMER =3D 13,
+ AW_H3_GIC_PPI_PHYSTIMER =3D 14
+};
+
+/* Shared Processor Interrupts */
+enum {
+ AW_H3_GIC_SPI_UART0 =3D 0,
+ AW_H3_GIC_SPI_UART1 =3D 1,
+ AW_H3_GIC_SPI_UART2 =3D 2,
+ AW_H3_GIC_SPI_UART3 =3D 3,
+ AW_H3_GIC_SPI_TIMER0 =3D 18,
+ AW_H3_GIC_SPI_TIMER1 =3D 19,
+};
+
+/* Allwinner H3 general constants */
+enum {
+ AW_H3_GIC_NUM_SPI =3D 128
+};
+
+static void allwinner_h3_init(Object *obj)
+{
+ AwH3State *s =3D AW_H3(obj);
+
+ s->memmap =3D allwinner_h3_memmap;
+
+ for (int i =3D 0; i < AW_H3_NUM_CPUS; i++) {
+ object_initialize_child(obj, "cpu[*]", &s->cpus[i], sizeof(s->cpus=
[i]),
+ ARM_CPU_TYPE_NAME("cortex-a7"),
+ &error_abort, NULL);
+ }
+
+ sysbus_init_child_obj(obj, "gic", &s->gic, sizeof(s->gic),
+ TYPE_ARM_GIC);
+
+ sysbus_init_child_obj(obj, "timer", &s->timer, sizeof(s->timer),
+ TYPE_AW_A10_PIT);
+ object_property_add_alias(obj, "clk0-freq", OBJECT(&s->timer),
+ "clk0-freq", &error_abort);
+ object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
+ "clk1-freq", &error_abort);
+}
+
+static void allwinner_h3_realize(DeviceState *dev, Error **errp)
+{
+ AwH3State *s =3D AW_H3(dev);
+ unsigned i;
+
+ /* CPUs */
+ for (i =3D 0; i < AW_H3_NUM_CPUS; i++) {
+
+ /* Provide Power State Coordination Interface */
+ qdev_prop_set_int32(DEVICE(&s->cpus[i]), "psci-conduit",
+ QEMU_PSCI_CONDUIT_HVC);
+
+ /* Disable secondary CPUs */
+ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "start-powered-off",
+ i > 0);
+
+ /* All exception levels required */
+ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el3", true);
+ qdev_prop_set_bit(DEVICE(&s->cpus[i]), "has_el2", true);
+
+ /* Mark realized */
+ qdev_init_nofail(DEVICE(&s->cpus[i]));
+ }
+
+ /* Generic Interrupt Controller */
+ qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", AW_H3_GIC_NUM_SPI +
+ GIC_INTERNAL);
+ qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
+ qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", AW_H3_NUM_CPUS);
+ qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", false);
+ qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", tr=
ue);
+ qdev_init_nofail(DEVICE(&s->gic));
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_GIC_HYP]);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_GIC_VCPU]);
+
+ /*
+ * Wire the outputs from each CPU's generic timer and the GICv3
+ * maintenance interrupt signal to the appropriate GIC PPI inputs,
+ * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inpu=
ts.
+ */
+ for (i =3D 0; i < AW_H3_NUM_CPUS; i++) {
+ DeviceState *cpudev =3D DEVICE(&s->cpus[i]);
+ int ppibase =3D AW_H3_GIC_NUM_SPI + i * GIC_INTERNAL + GIC_NR_SGIS;
+ int irq;
+ /*
+ * Mapping from the output timer irq lines from the CPU to the
+ * GIC PPI inputs used for this board.
+ */
+ const int timer_irq[] =3D {
+ [GTIMER_PHYS] =3D AW_H3_GIC_PPI_PHYSTIMER,
+ [GTIMER_VIRT] =3D AW_H3_GIC_PPI_VIRTTIMER,
+ [GTIMER_HYP] =3D AW_H3_GIC_PPI_HYPTIMER,
+ [GTIMER_SEC] =3D AW_H3_GIC_PPI_SECTIMER,
+ };
+
+ /* Connect CPU timer outputs to GIC PPI inputs */
+ for (irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) {
+ qdev_connect_gpio_out(cpudev, irq,
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ ppibase + timer_irq[irq=
]));
+ }
+
+ /* Connect GIC outputs to CPU interrupt inputs */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
+ qdev_get_gpio_in(cpudev, ARM_CPU_IRQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + AW_H3_NUM_CPUS,
+ qdev_get_gpio_in(cpudev, ARM_CPU_FIQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (2 * AW_H3_NUM_CPU=
S),
+ qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (3 * AW_H3_NUM_CPU=
S),
+ qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ));
+
+ /* GIC maintenance signal */
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + (4 * AW_H3_NUM_CPU=
S),
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ ppibase + AW_H3_GIC_PPI_MAINT)=
);
+ }
+
+ /* Timer */
+ qdev_init_nofail(DEVICE(&s->timer));
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIM=
ER0));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIM=
ER1));
+
+ /* SRAM */
+ memory_region_init_ram(&s->sram_a1, OBJECT(dev), "sram A1",
+ 64 * KiB, &error_abort);
+ memory_region_init_ram(&s->sram_a2, OBJECT(dev), "sram A2",
+ 32 * KiB, &error_abort);
+ memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C",
+ 44 * KiB, &error_abort);
+ memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_=
A1],
+ &s->sram_a1);
+ memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_=
A2],
+ &s->sram_a2);
+ memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_=
C],
+ &s->sram_c);
+
+ /* UART0. For future clocktree API: All UARTS are connected to APB2_CL=
K. */
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
+ 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
+ /* UART1 */
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART1], 2,
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
+ 115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
+ /* UART2 */
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART2], 2,
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
+ 115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
+ /* UART3 */
+ serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2,
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
+ 115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
+
+ /* Unimplemented devices */
+ for (i =3D 0; i < ARRAY_SIZE(unimplemented); i++) {
+ create_unimplemented_device(unimplemented[i].device_name,
+ unimplemented[i].base,
+ unimplemented[i].size);
+ }
+}
+
+static void allwinner_h3_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc =3D DEVICE_CLASS(oc);
+
+ dc->realize =3D allwinner_h3_realize;
+ /* Reason: uses serial_hd() in realize function */
+ dc->user_creatable =3D false;
+}
+
+static const TypeInfo allwinner_h3_type_info =3D {
+ .name =3D TYPE_AW_H3,
+ .parent =3D TYPE_DEVICE,
+ .instance_size =3D sizeof(AwH3State),
+ .instance_init =3D allwinner_h3_init,
+ .class_init =3D allwinner_h3_class_init,
+};
+
+static void allwinner_h3_register_types(void)
+{
+ type_register_static(&allwinner_h3_type_info);
+}
+
+type_init(allwinner_h3_register_types)
diff --git a/MAINTAINERS b/MAINTAINERS
index 2903cbe564e..3efa8e53ec8 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -492,6 +492,13 @@ F: hw/*/allwinner*
F: include/hw/*/allwinner*
F: hw/arm/cubieboard.c
=20
+Allwinner-h3
+M: Niek Linnenbank <nieklinnenbank@gmail.com>
+L: qemu-arm@nongnu.org
+S: Maintained
+F: hw/*/allwinner-h3*
+F: include/hw/*/allwinner-h3*
+
ARM PrimeCell and CMSDK devices
M: Peter Maydell <peter.maydell@linaro.org>
L: qemu-arm@nongnu.org
diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.=
mak
index 645e6201bb5..36a0e89daae 100644
--- a/default-configs/arm-softmmu.mak
+++ b/default-configs/arm-softmmu.mak
@@ -41,3 +41,4 @@ CONFIG_FSL_IMX25=3Dy
CONFIG_FSL_IMX7=3Dy
CONFIG_FSL_IMX6UL=3Dy
CONFIG_SEMIHOSTING=3Dy
+CONFIG_ALLWINNER_H3=3Dy
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index bc54fd61f94..fcdc651b73e 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -297,6 +297,14 @@ config ALLWINNER_A10
select SERIAL
select UNIMP
=20
+config ALLWINNER_H3
+ bool
+ select ALLWINNER_A10_PIT
+ select SERIAL
+ select ARM_TIMER
+ select ARM_GIC
+ select UNIMP
+
config RASPI
bool
select FRAMEBUFFER
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 13/36] hw/arm: add Xunlong Orange Pi PC machine
Date: Thu, 12 Mar 2020 16:44:36 +0000
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From: Niek Linnenbank <nieklinnenbank@gmail.com>
The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
based embedded computer with mainline support in both U-Boot
and Linux. The board comes with a Quad Core Cortex A7 @ 1.3GHz,
1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
various other I/O. This commit add support for the Xunlong
Orange Pi PC machine.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Tested-by: KONRAD Frederic <frederic.konrad@adacore.com>
Tested-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Message-id: 20200311221854.30370-3-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/Makefile.objs | 2 +-
hw/arm/orangepi.c | 92 ++++++++++++++++++++++++++++++++++++++++++++
MAINTAINERS | 1 +
3 files changed, 94 insertions(+), 1 deletion(-)
create mode 100644 hw/arm/orangepi.c
diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs
index ae577e875fd..534a6a119e5 100644
--- a/hw/arm/Makefile.objs
+++ b/hw/arm/Makefile.objs
@@ -35,7 +35,7 @@ obj-$(CONFIG_DIGIC) +=3D digic.o
obj-$(CONFIG_OMAP) +=3D omap1.o omap2.o
obj-$(CONFIG_STRONGARM) +=3D strongarm.o
obj-$(CONFIG_ALLWINNER_A10) +=3D allwinner-a10.o cubieboard.o
-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o
+obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3.o orangepi.o
obj-$(CONFIG_RASPI) +=3D bcm2835_peripherals.o bcm2836.o raspi.o
obj-$(CONFIG_STM32F205_SOC) +=3D stm32f205_soc.o
obj-$(CONFIG_STM32F405_SOC) +=3D stm32f405_soc.o
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
new file mode 100644
index 00000000000..3fcec1944e8
--- /dev/null
+++ b/hw/arm/orangepi.c
@@ -0,0 +1,92 @@
+/*
+ * Orange Pi emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "exec/address-spaces.h"
+#include "qapi/error.h"
+#include "cpu.h"
+#include "hw/sysbus.h"
+#include "hw/boards.h"
+#include "hw/qdev-properties.h"
+#include "hw/arm/allwinner-h3.h"
+#include "sysemu/sysemu.h"
+
+static struct arm_boot_info orangepi_binfo =3D {
+ .nb_cpus =3D AW_H3_NUM_CPUS,
+};
+
+static void orangepi_init(MachineState *machine)
+{
+ AwH3State *h3;
+
+ /* BIOS is not supported by this board */
+ if (bios_name) {
+ error_report("BIOS not supported for this machine");
+ exit(1);
+ }
+
+ /* This board has fixed size RAM */
+ if (machine->ram_size !=3D 1 * GiB) {
+ error_report("This machine can only be used with 1GiB of RAM");
+ exit(1);
+ }
+
+ /* Only allow Cortex-A7 for this board */
+ if (strcmp(machine->cpu_type, ARM_CPU_TYPE_NAME("cortex-a7")) !=3D 0) {
+ error_report("This board can only be used with cortex-a7 CPU");
+ exit(1);
+ }
+
+ h3 =3D AW_H3(object_new(TYPE_AW_H3));
+ object_property_add_child(OBJECT(machine), "soc", OBJECT(h3),
+ &error_abort);
+ object_unref(OBJECT(h3));
+
+ /* Setup timer properties */
+ object_property_set_int(OBJECT(h3), 32768, "clk0-freq",
+ &error_abort);
+ object_property_set_int(OBJECT(h3), 24 * 1000 * 1000, "clk1-freq",
+ &error_abort);
+
+ /* Mark H3 object realized */
+ object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
+
+ /* SDRAM */
+ memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRA=
M],
+ machine->ram);
+
+ orangepi_binfo.loader_start =3D h3->memmap[AW_H3_SDRAM];
+ orangepi_binfo.ram_size =3D machine->ram_size;
+ arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);
+}
+
+static void orangepi_machine_init(MachineClass *mc)
+{
+ mc->desc =3D "Orange Pi PC";
+ mc->init =3D orangepi_init;
+ mc->min_cpus =3D AW_H3_NUM_CPUS;
+ mc->max_cpus =3D AW_H3_NUM_CPUS;
+ mc->default_cpus =3D AW_H3_NUM_CPUS;
+ mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a7");
+ mc->default_ram_size =3D 1 * GiB;
+ mc->default_ram_id =3D "orangepi.ram";
+}
+
+DEFINE_MACHINE("orangepi-pc", orangepi_machine_init)
diff --git a/MAINTAINERS b/MAINTAINERS
index 3efa8e53ec8..d7a26d7171e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -498,6 +498,7 @@ L: qemu-arm@nongnu.org
S: Maintained
F: hw/*/allwinner-h3*
F: include/hw/*/allwinner-h3*
+F: hw/arm/orangepi.c
=20
ARM PrimeCell and CMSDK devices
M: Peter Maydell <peter.maydell@linaro.org>
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 14/36] hw/arm/allwinner-h3: add Clock Control Unit
Date: Thu, 12 Mar 2020 16:44:37 +0000
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From: Niek Linnenbank <nieklinnenbank@gmail.com>
The Clock Control Unit is responsible for clock signal generation,
configuration and distribution in the Allwinner H3 System on Chip.
This commit adds support for the Clock Control Unit which emulates
a simple read/write register interface.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Message-id: 20200311221854.30370-4-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/misc/Makefile.objs | 1 +
include/hw/arm/allwinner-h3.h | 3 +
include/hw/misc/allwinner-h3-ccu.h | 66 ++++++++
hw/arm/allwinner-h3.c | 9 +-
hw/misc/allwinner-h3-ccu.c | 242 +++++++++++++++++++++++++++++
5 files changed, 320 insertions(+), 1 deletion(-)
create mode 100644 include/hw/misc/allwinner-h3-ccu.h
create mode 100644 hw/misc/allwinner-h3-ccu.c
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index da993f45b74..5e635b74d5a 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -28,6 +28,7 @@ common-obj-$(CONFIG_MACIO) +=3D macio/
=20
common-obj-$(CONFIG_IVSHMEM_DEVICE) +=3D ivshmem.o
=20
+common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-ccu.o
common-obj-$(CONFIG_REALVIEW) +=3D arm_sysctl.o
common-obj-$(CONFIG_NSERIES) +=3D cbus.o
common-obj-$(CONFIG_ECCMEMCTL) +=3D eccmemctl.o
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index 2aac9b78ecf..abdc20871a6 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -39,6 +39,7 @@
#include "hw/arm/boot.h"
#include "hw/timer/allwinner-a10-pit.h"
#include "hw/intc/arm_gic.h"
+#include "hw/misc/allwinner-h3-ccu.h"
#include "target/arm/cpu.h"
=20
/**
@@ -55,6 +56,7 @@ enum {
AW_H3_SRAM_A1,
AW_H3_SRAM_A2,
AW_H3_SRAM_C,
+ AW_H3_CCU,
AW_H3_PIT,
AW_H3_UART0,
AW_H3_UART1,
@@ -97,6 +99,7 @@ typedef struct AwH3State {
ARMCPU cpus[AW_H3_NUM_CPUS];
const hwaddr *memmap;
AwA10PITState timer;
+ AwH3ClockCtlState ccu;
GICState gic;
MemoryRegion sram_a1;
MemoryRegion sram_a2;
diff --git a/include/hw/misc/allwinner-h3-ccu.h b/include/hw/misc/allwinner=
-h3-ccu.h
new file mode 100644
index 00000000000..eec59649f31
--- /dev/null
+++ b/include/hw/misc/allwinner-h3-ccu.h
@@ -0,0 +1,66 @@
+/*
+ * Allwinner H3 Clock Control Unit emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_MISC_ALLWINNER_H3_CCU_H
+#define HW_MISC_ALLWINNER_H3_CCU_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+
+/**
+ * @name Constants
+ * @{
+ */
+
+/** Size of register I/O address space used by CCU device */
+#define AW_H3_CCU_IOSIZE (0x400)
+
+/** Total number of known registers */
+#define AW_H3_CCU_REGS_NUM (AW_H3_CCU_IOSIZE / sizeof(uint32_t))
+
+/** @} */
+
+/**
+ * @name Object model
+ * @{
+ */
+
+#define TYPE_AW_H3_CCU "allwinner-h3-ccu"
+#define AW_H3_CCU(obj) \
+ OBJECT_CHECK(AwH3ClockCtlState, (obj), TYPE_AW_H3_CCU)
+
+/** @} */
+
+/**
+ * Allwinner H3 CCU object instance state.
+ */
+typedef struct AwH3ClockCtlState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ /** Maps I/O registers in physical memory */
+ MemoryRegion iomem;
+
+ /** Array of hardware registers */
+ uint32_t regs[AW_H3_CCU_REGS_NUM];
+
+} AwH3ClockCtlState;
+
+#endif /* HW_MISC_ALLWINNER_H3_CCU_H */
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index 7958f376852..1fff3c317b4 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -36,6 +36,7 @@ const hwaddr allwinner_h3_memmap[] =3D {
[AW_H3_SRAM_A1] =3D 0x00000000,
[AW_H3_SRAM_A2] =3D 0x00044000,
[AW_H3_SRAM_C] =3D 0x00010000,
+ [AW_H3_CCU] =3D 0x01c20000,
[AW_H3_PIT] =3D 0x01c20c00,
[AW_H3_UART0] =3D 0x01c28000,
[AW_H3_UART1] =3D 0x01c28400,
@@ -77,7 +78,6 @@ struct AwH3Unimplemented {
{ "usb2-phy", 0x01c1c000, 4 * KiB },
{ "usb3-phy", 0x01c1d000, 4 * KiB },
{ "smc", 0x01c1e000, 4 * KiB },
- { "ccu", 0x01c20000, 1 * KiB },
{ "pio", 0x01c20800, 1 * KiB },
{ "owa", 0x01c21000, 1 * KiB },
{ "pwm", 0x01c21400, 1 * KiB },
@@ -172,6 +172,9 @@ static void allwinner_h3_init(Object *obj)
"clk0-freq", &error_abort);
object_property_add_alias(obj, "clk1-freq", OBJECT(&s->timer),
"clk1-freq", &error_abort);
+
+ sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
+ TYPE_AW_H3_CCU);
}
=20
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -277,6 +280,10 @@ static void allwinner_h3_realize(DeviceState *dev, Err=
or **errp)
memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_=
C],
&s->sram_c);
=20
+ /* Clock Control Unit */
+ qdev_init_nofail(DEVICE(&s->ccu));
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
+
/* UART0. For future clocktree API: All UARTS are connected to APB2_CL=
K. */
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
diff --git a/hw/misc/allwinner-h3-ccu.c b/hw/misc/allwinner-h3-ccu.c
new file mode 100644
index 00000000000..18d10745458
--- /dev/null
+++ b/hw/misc/allwinner-h3-ccu.c
@@ -0,0 +1,242 @@
+/*
+ * Allwinner H3 Clock Control Unit emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/misc/allwinner-h3-ccu.h"
+
+/* CCU register offsets */
+enum {
+ REG_PLL_CPUX =3D 0x0000, /* PLL CPUX Control */
+ REG_PLL_AUDIO =3D 0x0008, /* PLL Audio Control */
+ REG_PLL_VIDEO =3D 0x0010, /* PLL Video Control */
+ REG_PLL_VE =3D 0x0018, /* PLL VE Control */
+ REG_PLL_DDR =3D 0x0020, /* PLL DDR Control */
+ REG_PLL_PERIPH0 =3D 0x0028, /* PLL Peripherals 0 Control */
+ REG_PLL_GPU =3D 0x0038, /* PLL GPU Control */
+ REG_PLL_PERIPH1 =3D 0x0044, /* PLL Peripherals 1 Control */
+ REG_PLL_DE =3D 0x0048, /* PLL Display Engine Control */
+ REG_CPUX_AXI =3D 0x0050, /* CPUX/AXI Configuration */
+ REG_APB1 =3D 0x0054, /* ARM Peripheral Bus 1 Config */
+ REG_APB2 =3D 0x0058, /* ARM Peripheral Bus 2 Config */
+ REG_DRAM_CFG =3D 0x00F4, /* DRAM Configuration */
+ REG_MBUS =3D 0x00FC, /* MBUS Reset */
+ REG_PLL_TIME0 =3D 0x0200, /* PLL Stable Time 0 */
+ REG_PLL_TIME1 =3D 0x0204, /* PLL Stable Time 1 */
+ REG_PLL_CPUX_BIAS =3D 0x0220, /* PLL CPUX Bias */
+ REG_PLL_AUDIO_BIAS =3D 0x0224, /* PLL Audio Bias */
+ REG_PLL_VIDEO_BIAS =3D 0x0228, /* PLL Video Bias */
+ REG_PLL_VE_BIAS =3D 0x022C, /* PLL VE Bias */
+ REG_PLL_DDR_BIAS =3D 0x0230, /* PLL DDR Bias */
+ REG_PLL_PERIPH0_BIAS =3D 0x0234, /* PLL Peripherals 0 Bias */
+ REG_PLL_GPU_BIAS =3D 0x023C, /* PLL GPU Bias */
+ REG_PLL_PERIPH1_BIAS =3D 0x0244, /* PLL Peripherals 1 Bias */
+ REG_PLL_DE_BIAS =3D 0x0248, /* PLL Display Engine Bias */
+ REG_PLL_CPUX_TUNING =3D 0x0250, /* PLL CPUX Tuning */
+ REG_PLL_DDR_TUNING =3D 0x0260, /* PLL DDR Tuning */
+};
+
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
+
+/* CCU register flags */
+enum {
+ REG_DRAM_CFG_UPDATE =3D (1 << 16),
+};
+
+enum {
+ REG_PLL_ENABLE =3D (1 << 31),
+ REG_PLL_LOCK =3D (1 << 28),
+};
+
+
+/* CCU register reset values */
+enum {
+ REG_PLL_CPUX_RST =3D 0x00001000,
+ REG_PLL_AUDIO_RST =3D 0x00035514,
+ REG_PLL_VIDEO_RST =3D 0x03006207,
+ REG_PLL_VE_RST =3D 0x03006207,
+ REG_PLL_DDR_RST =3D 0x00001000,
+ REG_PLL_PERIPH0_RST =3D 0x00041811,
+ REG_PLL_GPU_RST =3D 0x03006207,
+ REG_PLL_PERIPH1_RST =3D 0x00041811,
+ REG_PLL_DE_RST =3D 0x03006207,
+ REG_CPUX_AXI_RST =3D 0x00010000,
+ REG_APB1_RST =3D 0x00001010,
+ REG_APB2_RST =3D 0x01000000,
+ REG_DRAM_CFG_RST =3D 0x00000000,
+ REG_MBUS_RST =3D 0x80000000,
+ REG_PLL_TIME0_RST =3D 0x000000FF,
+ REG_PLL_TIME1_RST =3D 0x000000FF,
+ REG_PLL_CPUX_BIAS_RST =3D 0x08100200,
+ REG_PLL_AUDIO_BIAS_RST =3D 0x10100000,
+ REG_PLL_VIDEO_BIAS_RST =3D 0x10100000,
+ REG_PLL_VE_BIAS_RST =3D 0x10100000,
+ REG_PLL_DDR_BIAS_RST =3D 0x81104000,
+ REG_PLL_PERIPH0_BIAS_RST =3D 0x10100010,
+ REG_PLL_GPU_BIAS_RST =3D 0x10100000,
+ REG_PLL_PERIPH1_BIAS_RST =3D 0x10100010,
+ REG_PLL_DE_BIAS_RST =3D 0x10100000,
+ REG_PLL_CPUX_TUNING_RST =3D 0x0A101000,
+ REG_PLL_DDR_TUNING_RST =3D 0x14880000,
+};
+
+static uint64_t allwinner_h3_ccu_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ const AwH3ClockCtlState *s =3D AW_H3_CCU(opaque);
+ const uint32_t idx =3D REG_INDEX(offset);
+
+ switch (offset) {
+ case 0x308 ... AW_H3_CCU_IOSIZE:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return 0;
+ }
+
+ return s->regs[idx];
+}
+
+static void allwinner_h3_ccu_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AwH3ClockCtlState *s =3D AW_H3_CCU(opaque);
+ const uint32_t idx =3D REG_INDEX(offset);
+
+ switch (offset) {
+ case REG_DRAM_CFG: /* DRAM Configuration */
+ val &=3D ~REG_DRAM_CFG_UPDATE;
+ break;
+ case REG_PLL_CPUX: /* PLL CPUX Control */
+ case REG_PLL_AUDIO: /* PLL Audio Control */
+ case REG_PLL_VIDEO: /* PLL Video Control */
+ case REG_PLL_VE: /* PLL VE Control */
+ case REG_PLL_DDR: /* PLL DDR Control */
+ case REG_PLL_PERIPH0: /* PLL Peripherals 0 Control */
+ case REG_PLL_GPU: /* PLL GPU Control */
+ case REG_PLL_PERIPH1: /* PLL Peripherals 1 Control */
+ case REG_PLL_DE: /* PLL Display Engine Control */
+ if (val & REG_PLL_ENABLE) {
+ val |=3D REG_PLL_LOCK;
+ }
+ break;
+ case 0x308 ... AW_H3_CCU_IOSIZE:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented write offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ break;
+ }
+
+ s->regs[idx] =3D (uint32_t) val;
+}
+
+static const MemoryRegionOps allwinner_h3_ccu_ops =3D {
+ .read =3D allwinner_h3_ccu_read,
+ .write =3D allwinner_h3_ccu_write,
+ .endianness =3D DEVICE_NATIVE_ENDIAN,
+ .valid =3D {
+ .min_access_size =3D 4,
+ .max_access_size =3D 4,
+ },
+ .impl.min_access_size =3D 4,
+};
+
+static void allwinner_h3_ccu_reset(DeviceState *dev)
+{
+ AwH3ClockCtlState *s =3D AW_H3_CCU(dev);
+
+ /* Set default values for registers */
+ s->regs[REG_INDEX(REG_PLL_CPUX)] =3D REG_PLL_CPUX_RST;
+ s->regs[REG_INDEX(REG_PLL_AUDIO)] =3D REG_PLL_AUDIO_RST;
+ s->regs[REG_INDEX(REG_PLL_VIDEO)] =3D REG_PLL_VIDEO_RST;
+ s->regs[REG_INDEX(REG_PLL_VE)] =3D REG_PLL_VE_RST;
+ s->regs[REG_INDEX(REG_PLL_DDR)] =3D REG_PLL_DDR_RST;
+ s->regs[REG_INDEX(REG_PLL_PERIPH0)] =3D REG_PLL_PERIPH0_RST;
+ s->regs[REG_INDEX(REG_PLL_GPU)] =3D REG_PLL_GPU_RST;
+ s->regs[REG_INDEX(REG_PLL_PERIPH1)] =3D REG_PLL_PERIPH1_RST;
+ s->regs[REG_INDEX(REG_PLL_DE)] =3D REG_PLL_DE_RST;
+ s->regs[REG_INDEX(REG_CPUX_AXI)] =3D REG_CPUX_AXI_RST;
+ s->regs[REG_INDEX(REG_APB1)] =3D REG_APB1_RST;
+ s->regs[REG_INDEX(REG_APB2)] =3D REG_APB2_RST;
+ s->regs[REG_INDEX(REG_DRAM_CFG)] =3D REG_DRAM_CFG_RST;
+ s->regs[REG_INDEX(REG_MBUS)] =3D REG_MBUS_RST;
+ s->regs[REG_INDEX(REG_PLL_TIME0)] =3D REG_PLL_TIME0_RST;
+ s->regs[REG_INDEX(REG_PLL_TIME1)] =3D REG_PLL_TIME1_RST;
+ s->regs[REG_INDEX(REG_PLL_CPUX_BIAS)] =3D REG_PLL_CPUX_BIAS_RST;
+ s->regs[REG_INDEX(REG_PLL_AUDIO_BIAS)] =3D REG_PLL_AUDIO_BIAS_RST;
+ s->regs[REG_INDEX(REG_PLL_VIDEO_BIAS)] =3D REG_PLL_VIDEO_BIAS_RST;
+ s->regs[REG_INDEX(REG_PLL_VE_BIAS)] =3D REG_PLL_VE_BIAS_RST;
+ s->regs[REG_INDEX(REG_PLL_DDR_BIAS)] =3D REG_PLL_DDR_BIAS_RST;
+ s->regs[REG_INDEX(REG_PLL_PERIPH0_BIAS)] =3D REG_PLL_PERIPH0_BIAS_RST;
+ s->regs[REG_INDEX(REG_PLL_GPU_BIAS)] =3D REG_PLL_GPU_BIAS_RST;
+ s->regs[REG_INDEX(REG_PLL_PERIPH1_BIAS)] =3D REG_PLL_PERIPH1_BIAS_RST;
+ s->regs[REG_INDEX(REG_PLL_DE_BIAS)] =3D REG_PLL_DE_BIAS_RST;
+ s->regs[REG_INDEX(REG_PLL_CPUX_TUNING)] =3D REG_PLL_CPUX_TUNING_RST;
+ s->regs[REG_INDEX(REG_PLL_DDR_TUNING)] =3D REG_PLL_DDR_TUNING_RST;
+}
+
+static void allwinner_h3_ccu_init(Object *obj)
+{
+ SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj);
+ AwH3ClockCtlState *s =3D AW_H3_CCU(obj);
+
+ /* Memory mapping */
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_ccu_ops, s,
+ TYPE_AW_H3_CCU, AW_H3_CCU_IOSIZE);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static const VMStateDescription allwinner_h3_ccu_vmstate =3D {
+ .name =3D "allwinner-h3-ccu",
+ .version_id =3D 1,
+ .minimum_version_id =3D 1,
+ .fields =3D (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, AwH3ClockCtlState, AW_H3_CCU_REGS_NUM),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void allwinner_h3_ccu_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc =3D DEVICE_CLASS(klass);
+
+ dc->reset =3D allwinner_h3_ccu_reset;
+ dc->vmsd =3D &allwinner_h3_ccu_vmstate;
+}
+
+static const TypeInfo allwinner_h3_ccu_info =3D {
+ .name =3D TYPE_AW_H3_CCU,
+ .parent =3D TYPE_SYS_BUS_DEVICE,
+ .instance_init =3D allwinner_h3_ccu_init,
+ .instance_size =3D sizeof(AwH3ClockCtlState),
+ .class_init =3D allwinner_h3_ccu_class_init,
+};
+
+static void allwinner_h3_ccu_register(void)
+{
+ type_register_static(&allwinner_h3_ccu_info);
+}
+
+type_init(allwinner_h3_ccu_register)
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 15/36] hw/arm/allwinner-h3: add USB host controller
Date: Thu, 12 Mar 2020 16:44:38 +0000
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From: Niek Linnenbank <nieklinnenbank@gmail.com>
The Allwinner H3 System on Chip contains multiple USB 2.0 bus
connections which provide software access using the Enhanced
Host Controller Interface (EHCI) and Open Host Controller
Interface (OHCI) interfaces. This commit adds support for
both interfaces in the Allwinner H3 System on Chip.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Message-id: 20200311221854.30370-5-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/usb/hcd-ehci.h | 1 +
include/hw/arm/allwinner-h3.h | 8 +++++++
hw/arm/allwinner-h3.c | 44 +++++++++++++++++++++++++++++++++++
hw/usb/hcd-ehci-sysbus.c | 17 ++++++++++++++
hw/arm/Kconfig | 2 ++
5 files changed, 72 insertions(+)
diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h
index 0298238f0b9..edb59311c4e 100644
--- a/hw/usb/hcd-ehci.h
+++ b/hw/usb/hcd-ehci.h
@@ -342,6 +342,7 @@ typedef struct EHCIPCIState {
#define TYPE_SYS_BUS_EHCI "sysbus-ehci-usb"
#define TYPE_PLATFORM_EHCI "platform-ehci-usb"
#define TYPE_EXYNOS4210_EHCI "exynos4210-ehci-usb"
+#define TYPE_AW_H3_EHCI "aw-h3-ehci-usb"
#define TYPE_TEGRA2_EHCI "tegra2-ehci-usb"
#define TYPE_PPC4xx_EHCI "ppc4xx-ehci-usb"
#define TYPE_FUSBH200_EHCI "fusbh200-ehci-usb"
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index abdc20871a6..4f4dcbcd177 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -56,6 +56,14 @@ enum {
AW_H3_SRAM_A1,
AW_H3_SRAM_A2,
AW_H3_SRAM_C,
+ AW_H3_EHCI0,
+ AW_H3_OHCI0,
+ AW_H3_EHCI1,
+ AW_H3_OHCI1,
+ AW_H3_EHCI2,
+ AW_H3_OHCI2,
+ AW_H3_EHCI3,
+ AW_H3_OHCI3,
AW_H3_CCU,
AW_H3_PIT,
AW_H3_UART0,
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index 1fff3c317b4..c205f06738a 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -28,6 +28,7 @@
#include "hw/sysbus.h"
#include "hw/char/serial.h"
#include "hw/misc/unimp.h"
+#include "hw/usb/hcd-ehci.h"
#include "sysemu/sysemu.h"
#include "hw/arm/allwinner-h3.h"
=20
@@ -36,6 +37,14 @@ const hwaddr allwinner_h3_memmap[] =3D {
[AW_H3_SRAM_A1] =3D 0x00000000,
[AW_H3_SRAM_A2] =3D 0x00044000,
[AW_H3_SRAM_C] =3D 0x00010000,
+ [AW_H3_EHCI0] =3D 0x01c1a000,
+ [AW_H3_OHCI0] =3D 0x01c1a400,
+ [AW_H3_EHCI1] =3D 0x01c1b000,
+ [AW_H3_OHCI1] =3D 0x01c1b400,
+ [AW_H3_EHCI2] =3D 0x01c1c000,
+ [AW_H3_OHCI2] =3D 0x01c1c400,
+ [AW_H3_EHCI3] =3D 0x01c1d000,
+ [AW_H3_OHCI3] =3D 0x01c1d400,
[AW_H3_CCU] =3D 0x01c20000,
[AW_H3_PIT] =3D 0x01c20c00,
[AW_H3_UART0] =3D 0x01c28000,
@@ -144,6 +153,14 @@ enum {
AW_H3_GIC_SPI_UART3 =3D 3,
AW_H3_GIC_SPI_TIMER0 =3D 18,
AW_H3_GIC_SPI_TIMER1 =3D 19,
+ AW_H3_GIC_SPI_EHCI0 =3D 72,
+ AW_H3_GIC_SPI_OHCI0 =3D 73,
+ AW_H3_GIC_SPI_EHCI1 =3D 74,
+ AW_H3_GIC_SPI_OHCI1 =3D 75,
+ AW_H3_GIC_SPI_EHCI2 =3D 76,
+ AW_H3_GIC_SPI_OHCI2 =3D 77,
+ AW_H3_GIC_SPI_EHCI3 =3D 78,
+ AW_H3_GIC_SPI_OHCI3 =3D 79,
};
=20
/* Allwinner H3 general constants */
@@ -284,6 +301,33 @@ static void allwinner_h3_realize(DeviceState *dev, Err=
or **errp)
qdev_init_nofail(DEVICE(&s->ccu));
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
=20
+ /* Universal Serial Bus */
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_EHCI0));
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI1],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_EHCI1));
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI2],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_EHCI2));
+ sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI3],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_EHCI3));
+
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI0],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_OHCI0));
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI1],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_OHCI1));
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI2],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_OHCI2));
+ sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI3],
+ qdev_get_gpio_in(DEVICE(&s->gic),
+ AW_H3_GIC_SPI_OHCI3));
+
/* UART0. For future clocktree API: All UARTS are connected to APB2_CL=
K. */
serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c
index 5b7991cffe4..3730736540f 100644
--- a/hw/usb/hcd-ehci-sysbus.c
+++ b/hw/usb/hcd-ehci-sysbus.c
@@ -131,6 +131,22 @@ static const TypeInfo ehci_exynos4210_type_info =3D {
.class_init =3D ehci_exynos4210_class_init,
};
=20
+static void ehci_aw_h3_class_init(ObjectClass *oc, void *data)
+{
+ SysBusEHCIClass *sec =3D SYS_BUS_EHCI_CLASS(oc);
+ DeviceClass *dc =3D DEVICE_CLASS(oc);
+
+ sec->capsbase =3D 0x0;
+ sec->opregbase =3D 0x10;
+ set_bit(DEVICE_CATEGORY_USB, dc->categories);
+}
+
+static const TypeInfo ehci_aw_h3_type_info =3D {
+ .name =3D TYPE_AW_H3_EHCI,
+ .parent =3D TYPE_SYS_BUS_EHCI,
+ .class_init =3D ehci_aw_h3_class_init,
+};
+
static void ehci_tegra2_class_init(ObjectClass *oc, void *data)
{
SysBusEHCIClass *sec =3D SYS_BUS_EHCI_CLASS(oc);
@@ -252,6 +268,7 @@ static void ehci_sysbus_register_types(void)
type_register_static(&ehci_type_info);
type_register_static(&ehci_platform_type_info);
type_register_static(&ehci_exynos4210_type_info);
+ type_register_static(&ehci_aw_h3_type_info);
type_register_static(&ehci_tegra2_type_info);
type_register_static(&ehci_ppc4xx_type_info);
type_register_static(&ehci_fusbh200_type_info);
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index fcdc651b73e..f6422d54664 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -304,6 +304,8 @@ config ALLWINNER_H3
select ARM_TIMER
select ARM_GIC
select UNIMP
+ select USB_OHCI
+ select USB_EHCI_SYSBUS
=20
config RASPI
bool
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 16/36] hw/arm/allwinner-h3: add System Control module
Date: Thu, 12 Mar 2020 16:44:39 +0000
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From: Niek Linnenbank <nieklinnenbank@gmail.com>
The Allwinner H3 System on Chip has an System Control
module that provides system wide generic controls and
device information. This commit adds support for the
Allwinner H3 System Control module.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Message-id: 20200311221854.30370-6-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/misc/Makefile.objs | 1 +
include/hw/arm/allwinner-h3.h | 3 +
include/hw/misc/allwinner-h3-sysctrl.h | 67 ++++++++++++
hw/arm/allwinner-h3.c | 9 +-
hw/misc/allwinner-h3-sysctrl.c | 140 +++++++++++++++++++++++++
5 files changed, 219 insertions(+), 1 deletion(-)
create mode 100644 include/hw/misc/allwinner-h3-sysctrl.h
create mode 100644 hw/misc/allwinner-h3-sysctrl.c
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 5e635b74d5a..63b2e528f98 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -29,6 +29,7 @@ common-obj-$(CONFIG_MACIO) +=3D macio/
common-obj-$(CONFIG_IVSHMEM_DEVICE) +=3D ivshmem.o
=20
common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-ccu.o
+common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-sysctrl.o
common-obj-$(CONFIG_REALVIEW) +=3D arm_sysctl.o
common-obj-$(CONFIG_NSERIES) +=3D cbus.o
common-obj-$(CONFIG_ECCMEMCTL) +=3D eccmemctl.o
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index 4f4dcbcd177..43500c42621 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -40,6 +40,7 @@
#include "hw/timer/allwinner-a10-pit.h"
#include "hw/intc/arm_gic.h"
#include "hw/misc/allwinner-h3-ccu.h"
+#include "hw/misc/allwinner-h3-sysctrl.h"
#include "target/arm/cpu.h"
=20
/**
@@ -56,6 +57,7 @@ enum {
AW_H3_SRAM_A1,
AW_H3_SRAM_A2,
AW_H3_SRAM_C,
+ AW_H3_SYSCTRL,
AW_H3_EHCI0,
AW_H3_OHCI0,
AW_H3_EHCI1,
@@ -108,6 +110,7 @@ typedef struct AwH3State {
const hwaddr *memmap;
AwA10PITState timer;
AwH3ClockCtlState ccu;
+ AwH3SysCtrlState sysctrl;
GICState gic;
MemoryRegion sram_a1;
MemoryRegion sram_a2;
diff --git a/include/hw/misc/allwinner-h3-sysctrl.h b/include/hw/misc/allwi=
nner-h3-sysctrl.h
new file mode 100644
index 00000000000..af4119e0269
--- /dev/null
+++ b/include/hw/misc/allwinner-h3-sysctrl.h
@@ -0,0 +1,67 @@
+/*
+ * Allwinner H3 System Control emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_MISC_ALLWINNER_H3_SYSCTRL_H
+#define HW_MISC_ALLWINNER_H3_SYSCTRL_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+
+/**
+ * @name Constants
+ * @{
+ */
+
+/** Highest register address used by System Control device */
+#define AW_H3_SYSCTRL_REGS_MAXADDR (0x30)
+
+/** Total number of known registers */
+#define AW_H3_SYSCTRL_REGS_NUM ((AW_H3_SYSCTRL_REGS_MAXADDR / \
+ sizeof(uint32_t)) + 1)
+
+/** @} */
+
+/**
+ * @name Object model
+ * @{
+ */
+
+#define TYPE_AW_H3_SYSCTRL "allwinner-h3-sysctrl"
+#define AW_H3_SYSCTRL(obj) \
+ OBJECT_CHECK(AwH3SysCtrlState, (obj), TYPE_AW_H3_SYSCTRL)
+
+/** @} */
+
+/**
+ * Allwinner H3 System Control object instance state
+ */
+typedef struct AwH3SysCtrlState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ /** Maps I/O registers in physical memory */
+ MemoryRegion iomem;
+
+ /** Array of hardware registers */
+ uint32_t regs[AW_H3_SYSCTRL_REGS_NUM];
+
+} AwH3SysCtrlState;
+
+#endif /* HW_MISC_ALLWINNER_H3_SYSCTRL_H */
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index c205f06738a..0aa46712db7 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -37,6 +37,7 @@ const hwaddr allwinner_h3_memmap[] =3D {
[AW_H3_SRAM_A1] =3D 0x00000000,
[AW_H3_SRAM_A2] =3D 0x00044000,
[AW_H3_SRAM_C] =3D 0x00010000,
+ [AW_H3_SYSCTRL] =3D 0x01c00000,
[AW_H3_EHCI0] =3D 0x01c1a000,
[AW_H3_OHCI0] =3D 0x01c1a400,
[AW_H3_EHCI1] =3D 0x01c1b000,
@@ -66,7 +67,6 @@ struct AwH3Unimplemented {
} unimplemented[] =3D {
{ "d-engine", 0x01000000, 4 * MiB },
{ "d-inter", 0x01400000, 128 * KiB },
- { "syscon", 0x01c00000, 4 * KiB },
{ "dma", 0x01c02000, 4 * KiB },
{ "nfdc", 0x01c03000, 4 * KiB },
{ "ts", 0x01c06000, 4 * KiB },
@@ -192,6 +192,9 @@ static void allwinner_h3_init(Object *obj)
=20
sysbus_init_child_obj(obj, "ccu", &s->ccu, sizeof(s->ccu),
TYPE_AW_H3_CCU);
+
+ sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
+ TYPE_AW_H3_SYSCTRL);
}
=20
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -301,6 +304,10 @@ static void allwinner_h3_realize(DeviceState *dev, Err=
or **errp)
qdev_init_nofail(DEVICE(&s->ccu));
sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
=20
+ /* System Control */
+ qdev_init_nofail(DEVICE(&s->sysctrl));
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTR=
L]);
+
/* Universal Serial Bus */
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
qdev_get_gpio_in(DEVICE(&s->gic),
diff --git a/hw/misc/allwinner-h3-sysctrl.c b/hw/misc/allwinner-h3-sysctrl.c
new file mode 100644
index 00000000000..1d07efa880d
--- /dev/null
+++ b/hw/misc/allwinner-h3-sysctrl.c
@@ -0,0 +1,140 @@
+/*
+ * Allwinner H3 System Control emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/misc/allwinner-h3-sysctrl.h"
+
+/* System Control register offsets */
+enum {
+ REG_VER =3D 0x24, /* Version */
+ REG_EMAC_PHY_CLK =3D 0x30, /* EMAC PHY Clock */
+};
+
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
+
+/* System Control register reset values */
+enum {
+ REG_VER_RST =3D 0x0,
+ REG_EMAC_PHY_CLK_RST =3D 0x58000,
+};
+
+static uint64_t allwinner_h3_sysctrl_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ const AwH3SysCtrlState *s =3D AW_H3_SYSCTRL(opaque);
+ const uint32_t idx =3D REG_INDEX(offset);
+
+ if (idx >=3D AW_H3_SYSCTRL_REGS_NUM) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return 0;
+ }
+
+ return s->regs[idx];
+}
+
+static void allwinner_h3_sysctrl_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AwH3SysCtrlState *s =3D AW_H3_SYSCTRL(opaque);
+ const uint32_t idx =3D REG_INDEX(offset);
+
+ if (idx >=3D AW_H3_SYSCTRL_REGS_NUM) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return;
+ }
+
+ switch (offset) {
+ case REG_VER: /* Version */
+ break;
+ default:
+ s->regs[idx] =3D (uint32_t) val;
+ break;
+ }
+}
+
+static const MemoryRegionOps allwinner_h3_sysctrl_ops =3D {
+ .read =3D allwinner_h3_sysctrl_read,
+ .write =3D allwinner_h3_sysctrl_write,
+ .endianness =3D DEVICE_NATIVE_ENDIAN,
+ .valid =3D {
+ .min_access_size =3D 4,
+ .max_access_size =3D 4,
+ },
+ .impl.min_access_size =3D 4,
+};
+
+static void allwinner_h3_sysctrl_reset(DeviceState *dev)
+{
+ AwH3SysCtrlState *s =3D AW_H3_SYSCTRL(dev);
+
+ /* Set default values for registers */
+ s->regs[REG_INDEX(REG_VER)] =3D REG_VER_RST;
+ s->regs[REG_INDEX(REG_EMAC_PHY_CLK)] =3D REG_EMAC_PHY_CLK_RST;
+}
+
+static void allwinner_h3_sysctrl_init(Object *obj)
+{
+ SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj);
+ AwH3SysCtrlState *s =3D AW_H3_SYSCTRL(obj);
+
+ /* Memory mapping */
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_h3_sysctrl_ops,=
s,
+ TYPE_AW_H3_SYSCTRL, 4 * KiB);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static const VMStateDescription allwinner_h3_sysctrl_vmstate =3D {
+ .name =3D "allwinner-h3-sysctrl",
+ .version_id =3D 1,
+ .minimum_version_id =3D 1,
+ .fields =3D (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, AwH3SysCtrlState, AW_H3_SYSCTRL_REGS_NU=
M),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void allwinner_h3_sysctrl_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc =3D DEVICE_CLASS(klass);
+
+ dc->reset =3D allwinner_h3_sysctrl_reset;
+ dc->vmsd =3D &allwinner_h3_sysctrl_vmstate;
+}
+
+static const TypeInfo allwinner_h3_sysctrl_info =3D {
+ .name =3D TYPE_AW_H3_SYSCTRL,
+ .parent =3D TYPE_SYS_BUS_DEVICE,
+ .instance_init =3D allwinner_h3_sysctrl_init,
+ .instance_size =3D sizeof(AwH3SysCtrlState),
+ .class_init =3D allwinner_h3_sysctrl_class_init,
+};
+
+static void allwinner_h3_sysctrl_register(void)
+{
+ type_register_static(&allwinner_h3_sysctrl_info);
+}
+
+type_init(allwinner_h3_sysctrl_register)
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 17/36] hw/arm/allwinner: add CPU Configuration module
Date: Thu, 12 Mar 2020 16:44:40 +0000
Message-Id: <20200312164459.25924-18-peter.maydell@linaro.org>
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From: Niek Linnenbank <nieklinnenbank@gmail.com>
Various Allwinner System on Chip designs contain multiple processors
that can be configured and reset using the generic CPU Configuration
module interface. This commit adds support for the Allwinner CPU
configuration interface which emulates the following features:
* CPU reset
* CPU status
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Message-id: 20200311221854.30370-7-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/misc/Makefile.objs | 1 +
include/hw/arm/allwinner-h3.h | 3 +
include/hw/misc/allwinner-cpucfg.h | 52 ++++++
hw/arm/allwinner-h3.c | 9 +-
hw/misc/allwinner-cpucfg.c | 282 +++++++++++++++++++++++++++++
hw/misc/trace-events | 5 +
6 files changed, 351 insertions(+), 1 deletion(-)
create mode 100644 include/hw/misc/allwinner-cpucfg.h
create mode 100644 hw/misc/allwinner-cpucfg.c
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 63b2e528f98..f3788a59036 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -29,6 +29,7 @@ common-obj-$(CONFIG_MACIO) +=3D macio/
common-obj-$(CONFIG_IVSHMEM_DEVICE) +=3D ivshmem.o
=20
common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-ccu.o
+obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-cpucfg.o
common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-sysctrl.o
common-obj-$(CONFIG_REALVIEW) +=3D arm_sysctl.o
common-obj-$(CONFIG_NSERIES) +=3D cbus.o
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index 43500c42621..dc729176ab3 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -40,6 +40,7 @@
#include "hw/timer/allwinner-a10-pit.h"
#include "hw/intc/arm_gic.h"
#include "hw/misc/allwinner-h3-ccu.h"
+#include "hw/misc/allwinner-cpucfg.h"
#include "hw/misc/allwinner-h3-sysctrl.h"
#include "target/arm/cpu.h"
=20
@@ -76,6 +77,7 @@ enum {
AW_H3_GIC_CPU,
AW_H3_GIC_HYP,
AW_H3_GIC_VCPU,
+ AW_H3_CPUCFG,
AW_H3_SDRAM
};
=20
@@ -110,6 +112,7 @@ typedef struct AwH3State {
const hwaddr *memmap;
AwA10PITState timer;
AwH3ClockCtlState ccu;
+ AwCpuCfgState cpucfg;
AwH3SysCtrlState sysctrl;
GICState gic;
MemoryRegion sram_a1;
diff --git a/include/hw/misc/allwinner-cpucfg.h b/include/hw/misc/allwinner=
-cpucfg.h
new file mode 100644
index 00000000000..2c3693a8bec
--- /dev/null
+++ b/include/hw/misc/allwinner-cpucfg.h
@@ -0,0 +1,52 @@
+/*
+ * Allwinner CPU Configuration Module emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_MISC_ALLWINNER_CPUCFG_H
+#define HW_MISC_ALLWINNER_CPUCFG_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+
+/**
+ * Object model
+ * @{
+ */
+
+#define TYPE_AW_CPUCFG "allwinner-cpucfg"
+#define AW_CPUCFG(obj) \
+ OBJECT_CHECK(AwCpuCfgState, (obj), TYPE_AW_CPUCFG)
+
+/** @} */
+
+/**
+ * Allwinner CPU Configuration Module instance state
+ */
+typedef struct AwCpuCfgState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ MemoryRegion iomem;
+ uint32_t gen_ctrl;
+ uint32_t super_standby;
+ uint32_t entry_addr;
+
+} AwCpuCfgState;
+
+#endif /* HW_MISC_ALLWINNER_CPUCFG_H */
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index 0aa46712db7..b9a5597f2a2 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -56,6 +56,7 @@ const hwaddr allwinner_h3_memmap[] =3D {
[AW_H3_GIC_CPU] =3D 0x01c82000,
[AW_H3_GIC_HYP] =3D 0x01c84000,
[AW_H3_GIC_VCPU] =3D 0x01c86000,
+ [AW_H3_CPUCFG] =3D 0x01f01c00,
[AW_H3_SDRAM] =3D 0x40000000
};
=20
@@ -122,7 +123,6 @@ struct AwH3Unimplemented {
{ "r_wdog", 0x01f01000, 1 * KiB },
{ "r_prcm", 0x01f01400, 1 * KiB },
{ "r_twd", 0x01f01800, 1 * KiB },
- { "r_cpucfg", 0x01f01c00, 1 * KiB },
{ "r_cir-rx", 0x01f02000, 1 * KiB },
{ "r_twi", 0x01f02400, 1 * KiB },
{ "r_uart", 0x01f02800, 1 * KiB },
@@ -195,6 +195,9 @@ static void allwinner_h3_init(Object *obj)
=20
sysbus_init_child_obj(obj, "sysctrl", &s->sysctrl, sizeof(s->sysctrl),
TYPE_AW_H3_SYSCTRL);
+
+ sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg),
+ TYPE_AW_CPUCFG);
}
=20
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -308,6 +311,10 @@ static void allwinner_h3_realize(DeviceState *dev, Err=
or **errp)
qdev_init_nofail(DEVICE(&s->sysctrl));
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTR=
L]);
=20
+ /* CPU Configuration */
+ qdev_init_nofail(DEVICE(&s->cpucfg));
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]=
);
+
/* Universal Serial Bus */
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
qdev_get_gpio_in(DEVICE(&s->gic),
diff --git a/hw/misc/allwinner-cpucfg.c b/hw/misc/allwinner-cpucfg.c
new file mode 100644
index 00000000000..bbd33a7dac8
--- /dev/null
+++ b/hw/misc/allwinner-cpucfg.c
@@ -0,0 +1,282 @@
+/*
+ * Allwinner CPU Configuration Module emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/error-report.h"
+#include "qemu/timer.h"
+#include "hw/core/cpu.h"
+#include "target/arm/arm-powerctl.h"
+#include "target/arm/cpu.h"
+#include "hw/misc/allwinner-cpucfg.h"
+#include "trace.h"
+
+/* CPUCFG register offsets */
+enum {
+ REG_CPUS_RST_CTRL =3D 0x0000, /* CPUs Reset Control */
+ REG_CPU0_RST_CTRL =3D 0x0040, /* CPU#0 Reset Control */
+ REG_CPU0_CTRL =3D 0x0044, /* CPU#0 Control */
+ REG_CPU0_STATUS =3D 0x0048, /* CPU#0 Status */
+ REG_CPU1_RST_CTRL =3D 0x0080, /* CPU#1 Reset Control */
+ REG_CPU1_CTRL =3D 0x0084, /* CPU#1 Control */
+ REG_CPU1_STATUS =3D 0x0088, /* CPU#1 Status */
+ REG_CPU2_RST_CTRL =3D 0x00C0, /* CPU#2 Reset Control */
+ REG_CPU2_CTRL =3D 0x00C4, /* CPU#2 Control */
+ REG_CPU2_STATUS =3D 0x00C8, /* CPU#2 Status */
+ REG_CPU3_RST_CTRL =3D 0x0100, /* CPU#3 Reset Control */
+ REG_CPU3_CTRL =3D 0x0104, /* CPU#3 Control */
+ REG_CPU3_STATUS =3D 0x0108, /* CPU#3 Status */
+ REG_CPU_SYS_RST =3D 0x0140, /* CPU System Reset */
+ REG_CLK_GATING =3D 0x0144, /* CPU Clock Gating */
+ REG_GEN_CTRL =3D 0x0184, /* General Control */
+ REG_SUPER_STANDBY =3D 0x01A0, /* Super Standby Flag */
+ REG_ENTRY_ADDR =3D 0x01A4, /* Reset Entry Address */
+ REG_DBG_EXTERN =3D 0x01E4, /* Debug External */
+ REG_CNT64_CTRL =3D 0x0280, /* 64-bit Counter Control */
+ REG_CNT64_LOW =3D 0x0284, /* 64-bit Counter Low */
+ REG_CNT64_HIGH =3D 0x0288, /* 64-bit Counter High */
+};
+
+/* CPUCFG register flags */
+enum {
+ CPUX_RESET_RELEASED =3D ((1 << 1) | (1 << 0)),
+ CPUX_STATUS_SMP =3D (1 << 0),
+ CPU_SYS_RESET_RELEASED =3D (1 << 0),
+ CLK_GATING_ENABLE =3D ((1 << 8) | 0xF),
+};
+
+/* CPUCFG register reset values */
+enum {
+ REG_CLK_GATING_RST =3D 0x0000010F,
+ REG_GEN_CTRL_RST =3D 0x00000020,
+ REG_SUPER_STANDBY_RST =3D 0x0,
+ REG_CNT64_CTRL_RST =3D 0x0,
+};
+
+/* CPUCFG constants */
+enum {
+ CPU_EXCEPTION_LEVEL_ON_RESET =3D 3, /* EL3 */
+};
+
+static void allwinner_cpucfg_cpu_reset(AwCpuCfgState *s, uint8_t cpu_id)
+{
+ int ret;
+
+ trace_allwinner_cpucfg_cpu_reset(cpu_id, s->entry_addr);
+
+ ARMCPU *target_cpu =3D ARM_CPU(arm_get_cpu_by_id(cpu_id));
+ if (!target_cpu) {
+ /*
+ * Called with a bogus value for cpu_id. Guest error will
+ * already have been logged, we can simply return here.
+ */
+ return;
+ }
+ bool target_aa64 =3D arm_feature(&target_cpu->env, ARM_FEATURE_AARCH64=
);
+
+ ret =3D arm_set_cpu_on(cpu_id, s->entry_addr, 0,
+ CPU_EXCEPTION_LEVEL_ON_RESET, target_aa64);
+ if (ret !=3D QEMU_ARM_POWERCTL_RET_SUCCESS) {
+ error_report("%s: failed to bring up CPU %d: err %d",
+ __func__, cpu_id, ret);
+ return;
+ }
+}
+
+static uint64_t allwinner_cpucfg_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ const AwCpuCfgState *s =3D AW_CPUCFG(opaque);
+ uint64_t val =3D 0;
+
+ switch (offset) {
+ case REG_CPUS_RST_CTRL: /* CPUs Reset Control */
+ case REG_CPU_SYS_RST: /* CPU System Reset */
+ val =3D CPU_SYS_RESET_RELEASED;
+ break;
+ case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */
+ case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */
+ case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */
+ case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */
+ val =3D CPUX_RESET_RELEASED;
+ break;
+ case REG_CPU0_CTRL: /* CPU#0 Control */
+ case REG_CPU1_CTRL: /* CPU#1 Control */
+ case REG_CPU2_CTRL: /* CPU#2 Control */
+ case REG_CPU3_CTRL: /* CPU#3 Control */
+ val =3D 0;
+ break;
+ case REG_CPU0_STATUS: /* CPU#0 Status */
+ case REG_CPU1_STATUS: /* CPU#1 Status */
+ case REG_CPU2_STATUS: /* CPU#2 Status */
+ case REG_CPU3_STATUS: /* CPU#3 Status */
+ val =3D CPUX_STATUS_SMP;
+ break;
+ case REG_CLK_GATING: /* CPU Clock Gating */
+ val =3D CLK_GATING_ENABLE;
+ break;
+ case REG_GEN_CTRL: /* General Control */
+ val =3D s->gen_ctrl;
+ break;
+ case REG_SUPER_STANDBY: /* Super Standby Flag */
+ val =3D s->super_standby;
+ break;
+ case REG_ENTRY_ADDR: /* Reset Entry Address */
+ val =3D s->entry_addr;
+ break;
+ case REG_DBG_EXTERN: /* Debug External */
+ case REG_CNT64_CTRL: /* 64-bit Counter Control */
+ case REG_CNT64_LOW: /* 64-bit Counter Low */
+ case REG_CNT64_HIGH: /* 64-bit Counter High */
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register at 0x%04x\n",
+ __func__, (uint32_t)offset);
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ break;
+ }
+
+ trace_allwinner_cpucfg_read(offset, val, size);
+
+ return val;
+}
+
+static void allwinner_cpucfg_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AwCpuCfgState *s =3D AW_CPUCFG(opaque);
+
+ trace_allwinner_cpucfg_write(offset, val, size);
+
+ switch (offset) {
+ case REG_CPUS_RST_CTRL: /* CPUs Reset Control */
+ case REG_CPU_SYS_RST: /* CPU System Reset */
+ break;
+ case REG_CPU0_RST_CTRL: /* CPU#0 Reset Control */
+ case REG_CPU1_RST_CTRL: /* CPU#1 Reset Control */
+ case REG_CPU2_RST_CTRL: /* CPU#2 Reset Control */
+ case REG_CPU3_RST_CTRL: /* CPU#3 Reset Control */
+ if (val) {
+ allwinner_cpucfg_cpu_reset(s, (offset - REG_CPU0_RST_CTRL) >> =
6);
+ }
+ break;
+ case REG_CPU0_CTRL: /* CPU#0 Control */
+ case REG_CPU1_CTRL: /* CPU#1 Control */
+ case REG_CPU2_CTRL: /* CPU#2 Control */
+ case REG_CPU3_CTRL: /* CPU#3 Control */
+ case REG_CPU0_STATUS: /* CPU#0 Status */
+ case REG_CPU1_STATUS: /* CPU#1 Status */
+ case REG_CPU2_STATUS: /* CPU#2 Status */
+ case REG_CPU3_STATUS: /* CPU#3 Status */
+ case REG_CLK_GATING: /* CPU Clock Gating */
+ break;
+ case REG_GEN_CTRL: /* General Control */
+ s->gen_ctrl =3D val;
+ break;
+ case REG_SUPER_STANDBY: /* Super Standby Flag */
+ s->super_standby =3D val;
+ break;
+ case REG_ENTRY_ADDR: /* Reset Entry Address */
+ s->entry_addr =3D val;
+ break;
+ case REG_DBG_EXTERN: /* Debug External */
+ case REG_CNT64_CTRL: /* 64-bit Counter Control */
+ case REG_CNT64_LOW: /* 64-bit Counter Low */
+ case REG_CNT64_HIGH: /* 64-bit Counter High */
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register at 0x%04x\n",
+ __func__, (uint32_t)offset);
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ break;
+ }
+}
+
+static const MemoryRegionOps allwinner_cpucfg_ops =3D {
+ .read =3D allwinner_cpucfg_read,
+ .write =3D allwinner_cpucfg_write,
+ .endianness =3D DEVICE_NATIVE_ENDIAN,
+ .valid =3D {
+ .min_access_size =3D 4,
+ .max_access_size =3D 4,
+ },
+ .impl.min_access_size =3D 4,
+};
+
+static void allwinner_cpucfg_reset(DeviceState *dev)
+{
+ AwCpuCfgState *s =3D AW_CPUCFG(dev);
+
+ /* Set default values for registers */
+ s->gen_ctrl =3D REG_GEN_CTRL_RST;
+ s->super_standby =3D REG_SUPER_STANDBY_RST;
+ s->entry_addr =3D 0;
+}
+
+static void allwinner_cpucfg_init(Object *obj)
+{
+ SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj);
+ AwCpuCfgState *s =3D AW_CPUCFG(obj);
+
+ /* Memory mapping */
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_cpucfg_ops, s,
+ TYPE_AW_CPUCFG, 1 * KiB);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static const VMStateDescription allwinner_cpucfg_vmstate =3D {
+ .name =3D "allwinner-cpucfg",
+ .version_id =3D 1,
+ .minimum_version_id =3D 1,
+ .fields =3D (VMStateField[]) {
+ VMSTATE_UINT32(gen_ctrl, AwCpuCfgState),
+ VMSTATE_UINT32(super_standby, AwCpuCfgState),
+ VMSTATE_UINT32(entry_addr, AwCpuCfgState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void allwinner_cpucfg_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc =3D DEVICE_CLASS(klass);
+
+ dc->reset =3D allwinner_cpucfg_reset;
+ dc->vmsd =3D &allwinner_cpucfg_vmstate;
+}
+
+static const TypeInfo allwinner_cpucfg_info =3D {
+ .name =3D TYPE_AW_CPUCFG,
+ .parent =3D TYPE_SYS_BUS_DEVICE,
+ .instance_init =3D allwinner_cpucfg_init,
+ .instance_size =3D sizeof(AwCpuCfgState),
+ .class_init =3D allwinner_cpucfg_class_init,
+};
+
+static void allwinner_cpucfg_register(void)
+{
+ type_register_static(&allwinner_cpucfg_info);
+}
+
+type_init(allwinner_cpucfg_register)
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 7f0f5dff3a8..ede1650672e 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -1,5 +1,10 @@
# See docs/devel/tracing.txt for syntax documentation.
=20
+# allwinner-cpucfg.c
+allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_addr) "id %u, re=
set_addr 0x%" PRIu32
+allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offs=
et 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "off=
set 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+
# eccmemctl.c
ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x"
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 18/36] hw/arm/allwinner: add Security Identifier device
Date: Thu, 12 Mar 2020 16:44:41 +0000
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From: Niek Linnenbank <nieklinnenbank@gmail.com>
The Security Identifier device found in various Allwinner System on Chip
designs gives applications a per-board unique identifier. This commit
adds support for the Allwinner Security Identifier using a 128-bit
UUID value as input.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Message-id: 20200311221854.30370-8-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/misc/Makefile.objs | 1 +
include/hw/arm/allwinner-h3.h | 3 +
include/hw/misc/allwinner-sid.h | 60 ++++++++++++
hw/arm/allwinner-h3.c | 11 ++-
hw/arm/orangepi.c | 8 ++
hw/misc/allwinner-sid.c | 168 ++++++++++++++++++++++++++++++++
hw/misc/trace-events | 4 +
7 files changed, 254 insertions(+), 1 deletion(-)
create mode 100644 include/hw/misc/allwinner-sid.h
create mode 100644 hw/misc/allwinner-sid.c
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index f3788a59036..daa734036eb 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -31,6 +31,7 @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) +=3D ivshmem.o
common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-ccu.o
obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-cpucfg.o
common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-sysctrl.o
+common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-sid.o
common-obj-$(CONFIG_REALVIEW) +=3D arm_sysctl.o
common-obj-$(CONFIG_NSERIES) +=3D cbus.o
common-obj-$(CONFIG_ECCMEMCTL) +=3D eccmemctl.o
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index dc729176ab3..85416d9d64d 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -42,6 +42,7 @@
#include "hw/misc/allwinner-h3-ccu.h"
#include "hw/misc/allwinner-cpucfg.h"
#include "hw/misc/allwinner-h3-sysctrl.h"
+#include "hw/misc/allwinner-sid.h"
#include "target/arm/cpu.h"
=20
/**
@@ -59,6 +60,7 @@ enum {
AW_H3_SRAM_A2,
AW_H3_SRAM_C,
AW_H3_SYSCTRL,
+ AW_H3_SID,
AW_H3_EHCI0,
AW_H3_OHCI0,
AW_H3_EHCI1,
@@ -114,6 +116,7 @@ typedef struct AwH3State {
AwH3ClockCtlState ccu;
AwCpuCfgState cpucfg;
AwH3SysCtrlState sysctrl;
+ AwSidState sid;
GICState gic;
MemoryRegion sram_a1;
MemoryRegion sram_a2;
diff --git a/include/hw/misc/allwinner-sid.h b/include/hw/misc/allwinner-si=
d.h
new file mode 100644
index 00000000000..4c1fa4762b9
--- /dev/null
+++ b/include/hw/misc/allwinner-sid.h
@@ -0,0 +1,60 @@
+/*
+ * Allwinner Security ID emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_MISC_ALLWINNER_SID_H
+#define HW_MISC_ALLWINNER_SID_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+#include "qemu/uuid.h"
+
+/**
+ * Object model
+ * @{
+ */
+
+#define TYPE_AW_SID "allwinner-sid"
+#define AW_SID(obj) \
+ OBJECT_CHECK(AwSidState, (obj), TYPE_AW_SID)
+
+/** @} */
+
+/**
+ * Allwinner Security ID object instance state
+ */
+typedef struct AwSidState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ /** Maps I/O registers in physical memory */
+ MemoryRegion iomem;
+
+ /** Control register defines how and what to read */
+ uint32_t control;
+
+ /** RdKey register contains the data retrieved by the device */
+ uint32_t rdkey;
+
+ /** Stores the emulated device identifier */
+ QemuUUID identifier;
+
+} AwSidState;
+
+#endif /* HW_MISC_ALLWINNER_SID_H */
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index b9a5597f2a2..deeea63f5f3 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -38,6 +38,7 @@ const hwaddr allwinner_h3_memmap[] =3D {
[AW_H3_SRAM_A2] =3D 0x00044000,
[AW_H3_SRAM_C] =3D 0x00010000,
[AW_H3_SYSCTRL] =3D 0x01c00000,
+ [AW_H3_SID] =3D 0x01c14000,
[AW_H3_EHCI0] =3D 0x01c1a000,
[AW_H3_OHCI0] =3D 0x01c1a400,
[AW_H3_EHCI1] =3D 0x01c1b000,
@@ -78,7 +79,6 @@ struct AwH3Unimplemented {
{ "mmc0", 0x01c0f000, 4 * KiB },
{ "mmc1", 0x01c10000, 4 * KiB },
{ "mmc2", 0x01c11000, 4 * KiB },
- { "sid", 0x01c14000, 1 * KiB },
{ "crypto", 0x01c15000, 4 * KiB },
{ "msgbox", 0x01c17000, 4 * KiB },
{ "spinlock", 0x01c18000, 4 * KiB },
@@ -198,6 +198,11 @@ static void allwinner_h3_init(Object *obj)
=20
sysbus_init_child_obj(obj, "cpucfg", &s->cpucfg, sizeof(s->cpucfg),
TYPE_AW_CPUCFG);
+
+ sysbus_init_child_obj(obj, "sid", &s->sid, sizeof(s->sid),
+ TYPE_AW_SID);
+ object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
+ "identifier", &error_abort);
}
=20
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -315,6 +320,10 @@ static void allwinner_h3_realize(DeviceState *dev, Err=
or **errp)
qdev_init_nofail(DEVICE(&s->cpucfg));
sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]=
);
=20
+ /* Security Identifier */
+ qdev_init_nofail(DEVICE(&s->sid));
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
+
/* Universal Serial Bus */
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
qdev_get_gpio_in(DEVICE(&s->gic),
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index 3fcec1944e8..4047c4c3863 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -65,6 +65,14 @@ static void orangepi_init(MachineState *machine)
object_property_set_int(OBJECT(h3), 24 * 1000 * 1000, "clk1-freq",
&error_abort);
=20
+ /* Setup SID properties. Currently using a default fixed SID identifie=
r. */
+ if (qemu_uuid_is_null(&h3->sid.identifier)) {
+ qdev_prop_set_string(DEVICE(h3), "identifier",
+ "02c00081-1111-2222-3333-000044556677");
+ } else if (ldl_be_p(&h3->sid.identifier.data[0]) !=3D 0x02c00081) {
+ warn_report("Security Identifier value does not include H3 prefix"=
);
+ }
+
/* Mark H3 object realized */
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
=20
diff --git a/hw/misc/allwinner-sid.c b/hw/misc/allwinner-sid.c
new file mode 100644
index 00000000000..196380c33a4
--- /dev/null
+++ b/hw/misc/allwinner-sid.c
@@ -0,0 +1,168 @@
+/*
+ * Allwinner Security ID emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/guest-random.h"
+#include "qapi/error.h"
+#include "hw/qdev-properties.h"
+#include "hw/misc/allwinner-sid.h"
+#include "trace.h"
+
+/* SID register offsets */
+enum {
+ REG_PRCTL =3D 0x40, /* Control */
+ REG_RDKEY =3D 0x60, /* Read Key */
+};
+
+/* SID register flags */
+enum {
+ REG_PRCTL_WRITE =3D 0x0002, /* Unknown write flag */
+ REG_PRCTL_OP_LOCK =3D 0xAC00, /* Lock operation */
+};
+
+static uint64_t allwinner_sid_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ const AwSidState *s =3D AW_SID(opaque);
+ uint64_t val =3D 0;
+
+ switch (offset) {
+ case REG_PRCTL: /* Control */
+ val =3D s->control;
+ break;
+ case REG_RDKEY: /* Read Key */
+ val =3D s->rdkey;
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return 0;
+ }
+
+ trace_allwinner_sid_read(offset, val, size);
+
+ return val;
+}
+
+static void allwinner_sid_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AwSidState *s =3D AW_SID(opaque);
+
+ trace_allwinner_sid_write(offset, val, size);
+
+ switch (offset) {
+ case REG_PRCTL: /* Control */
+ s->control =3D val;
+
+ if ((s->control & REG_PRCTL_OP_LOCK) &&
+ (s->control & REG_PRCTL_WRITE)) {
+ uint32_t id =3D s->control >> 16;
+
+ if (id <=3D sizeof(QemuUUID) - sizeof(s->rdkey)) {
+ s->rdkey =3D ldl_be_p(&s->identifier.data[id]);
+ }
+ }
+ s->control &=3D ~REG_PRCTL_WRITE;
+ break;
+ case REG_RDKEY: /* Read Key */
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ break;
+ }
+}
+
+static const MemoryRegionOps allwinner_sid_ops =3D {
+ .read =3D allwinner_sid_read,
+ .write =3D allwinner_sid_write,
+ .endianness =3D DEVICE_NATIVE_ENDIAN,
+ .valid =3D {
+ .min_access_size =3D 4,
+ .max_access_size =3D 4,
+ },
+ .impl.min_access_size =3D 4,
+};
+
+static void allwinner_sid_reset(DeviceState *dev)
+{
+ AwSidState *s =3D AW_SID(dev);
+
+ /* Set default values for registers */
+ s->control =3D 0;
+ s->rdkey =3D 0;
+}
+
+static void allwinner_sid_init(Object *obj)
+{
+ SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj);
+ AwSidState *s =3D AW_SID(obj);
+
+ /* Memory mapping */
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sid_ops, s,
+ TYPE_AW_SID, 1 * KiB);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static Property allwinner_sid_properties[] =3D {
+ DEFINE_PROP_UUID_NODEFAULT("identifier", AwSidState, identifier),
+ DEFINE_PROP_END_OF_LIST()
+};
+
+static const VMStateDescription allwinner_sid_vmstate =3D {
+ .name =3D "allwinner-sid",
+ .version_id =3D 1,
+ .minimum_version_id =3D 1,
+ .fields =3D (VMStateField[]) {
+ VMSTATE_UINT32(control, AwSidState),
+ VMSTATE_UINT32(rdkey, AwSidState),
+ VMSTATE_UINT8_ARRAY_V(identifier.data, AwSidState, sizeof(QemuUUID=
), 1),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void allwinner_sid_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc =3D DEVICE_CLASS(klass);
+
+ dc->reset =3D allwinner_sid_reset;
+ dc->vmsd =3D &allwinner_sid_vmstate;
+ device_class_set_props(dc, allwinner_sid_properties);
+}
+
+static const TypeInfo allwinner_sid_info =3D {
+ .name =3D TYPE_AW_SID,
+ .parent =3D TYPE_SYS_BUS_DEVICE,
+ .instance_init =3D allwinner_sid_init,
+ .instance_size =3D sizeof(AwSidState),
+ .class_init =3D allwinner_sid_class_init,
+};
+
+static void allwinner_sid_register(void)
+{
+ type_register_static(&allwinner_sid_info);
+}
+
+type_init(allwinner_sid_register)
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index ede1650672e..4f38328d9c3 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -5,6 +5,10 @@ allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_=
addr) "id %u, reset_ad
allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offs=
et 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "off=
set 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
=20
+# allwinner-sid.c
+allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset =
0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset=
0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+
# eccmemctl.c
ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x"
ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x"
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 19/36] hw/arm/allwinner: add SD/MMC host controller
Date: Thu, 12 Mar 2020 16:44:42 +0000
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From: Niek Linnenbank <nieklinnenbank@gmail.com>
The Allwinner System on Chip families sun4i and above contain
an integrated storage controller for Secure Digital (SD) and
Multi Media Card (MMC) interfaces. This commit adds support
for the Allwinner SD/MMC storage controller with the following
emulated features:
* DMA transfers
* Direct FIFO I/O
* Short/Long format command responses
* Auto-Stop command (CMD12)
* Insert & remove card detection
The following boards are extended with the SD host controller:
* Cubieboard (hw/arm/cubieboard.c)
* Orange Pi PC (hw/arm/orangepi.c)
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Message-id: 20200311221854.30370-9-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/sd/Makefile.objs | 1 +
include/hw/arm/allwinner-a10.h | 2 +
include/hw/arm/allwinner-h3.h | 3 +
include/hw/sd/allwinner-sdhost.h | 135 +++++
hw/arm/allwinner-a10.c | 11 +
hw/arm/allwinner-h3.c | 15 +-
hw/arm/cubieboard.c | 15 +
hw/arm/orangepi.c | 16 +
hw/sd/allwinner-sdhost.c | 854 +++++++++++++++++++++++++++++++
hw/arm/Kconfig | 1 +
hw/sd/trace-events | 7 +
11 files changed, 1059 insertions(+), 1 deletion(-)
create mode 100644 include/hw/sd/allwinner-sdhost.h
create mode 100644 hw/sd/allwinner-sdhost.c
diff --git a/hw/sd/Makefile.objs b/hw/sd/Makefile.objs
index e371281ac4a..0d1df1721ca 100644
--- a/hw/sd/Makefile.objs
+++ b/hw/sd/Makefile.objs
@@ -4,6 +4,7 @@ common-obj-$(CONFIG_SD) +=3D sd.o core.o sdmmc-internal.o
common-obj-$(CONFIG_SDHCI) +=3D sdhci.o
common-obj-$(CONFIG_SDHCI_PCI) +=3D sdhci-pci.o
=20
+common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-sdhost.o
common-obj-$(CONFIG_MILKYMIST) +=3D milkymist-memcard.o
common-obj-$(CONFIG_OMAP) +=3D omap_mmc.o
common-obj-$(CONFIG_PXA2XX) +=3D pxa2xx_mmci.o
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index 8af724548f0..ae33a84b18b 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -7,6 +7,7 @@
#include "hw/timer/allwinner-a10-pit.h"
#include "hw/intc/allwinner-a10-pic.h"
#include "hw/net/allwinner_emac.h"
+#include "hw/sd/allwinner-sdhost.h"
#include "hw/ide/ahci.h"
#include "hw/usb/hcd-ohci.h"
#include "hw/usb/hcd-ehci.h"
@@ -31,6 +32,7 @@ typedef struct AwA10State {
AwA10PICState intc;
AwEmacState emac;
AllwinnerAHCIState sata;
+ AwSdHostState mmc0;
MemoryRegion sram_a;
EHCISysBusState ehci[AW_A10_NUM_USB];
OHCISysBusState ohci[AW_A10_NUM_USB];
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index 85416d9d64d..d71a4917ab8 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -43,6 +43,7 @@
#include "hw/misc/allwinner-cpucfg.h"
#include "hw/misc/allwinner-h3-sysctrl.h"
#include "hw/misc/allwinner-sid.h"
+#include "hw/sd/allwinner-sdhost.h"
#include "target/arm/cpu.h"
=20
/**
@@ -60,6 +61,7 @@ enum {
AW_H3_SRAM_A2,
AW_H3_SRAM_C,
AW_H3_SYSCTRL,
+ AW_H3_MMC0,
AW_H3_SID,
AW_H3_EHCI0,
AW_H3_OHCI0,
@@ -117,6 +119,7 @@ typedef struct AwH3State {
AwCpuCfgState cpucfg;
AwH3SysCtrlState sysctrl;
AwSidState sid;
+ AwSdHostState mmc0;
GICState gic;
MemoryRegion sram_a1;
MemoryRegion sram_a2;
diff --git a/include/hw/sd/allwinner-sdhost.h b/include/hw/sd/allwinner-sdh=
ost.h
new file mode 100644
index 00000000000..d94606a8531
--- /dev/null
+++ b/include/hw/sd/allwinner-sdhost.h
@@ -0,0 +1,135 @@
+/*
+ * Allwinner (sun4i and above) SD Host Controller emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_SD_ALLWINNER_SDHOST_H
+#define HW_SD_ALLWINNER_SDHOST_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+#include "hw/sd/sd.h"
+
+/**
+ * Object model types
+ * @{
+ */
+
+/** Generic Allwinner SD Host Controller (abstract) */
+#define TYPE_AW_SDHOST "allwinner-sdhost"
+
+/** Allwinner sun4i family (A10, A12) */
+#define TYPE_AW_SDHOST_SUN4I TYPE_AW_SDHOST "-sun4i"
+
+/** Allwinner sun5i family and newer (A13, H2+, H3, etc) */
+#define TYPE_AW_SDHOST_SUN5I TYPE_AW_SDHOST "-sun5i"
+
+/** @} */
+
+/**
+ * Object model macros
+ * @{
+ */
+
+#define AW_SDHOST(obj) \
+ OBJECT_CHECK(AwSdHostState, (obj), TYPE_AW_SDHOST)
+#define AW_SDHOST_CLASS(klass) \
+ OBJECT_CLASS_CHECK(AwSdHostClass, (klass), TYPE_AW_SDHOST)
+#define AW_SDHOST_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(AwSdHostClass, (obj), TYPE_AW_SDHOST)
+
+/** @} */
+
+/**
+ * Allwinner SD Host Controller object instance state.
+ */
+typedef struct AwSdHostState {
+ /*< private >*/
+ SysBusDevice busdev;
+ /*< public >*/
+
+ /** Secure Digital (SD) bus, which connects to SD card (if present) */
+ SDBus sdbus;
+
+ /** Maps I/O registers in physical memory */
+ MemoryRegion iomem;
+
+ /** Interrupt output signal to notify CPU */
+ qemu_irq irq;
+
+ /** Number of bytes left in current DMA transfer */
+ uint32_t transfer_cnt;
+
+ /**
+ * @name Hardware Registers
+ * @{
+ */
+
+ uint32_t global_ctl; /**< Global Control */
+ uint32_t clock_ctl; /**< Clock Control */
+ uint32_t timeout; /**< Timeout */
+ uint32_t bus_width; /**< Bus Width */
+ uint32_t block_size; /**< Block Size */
+ uint32_t byte_count; /**< Byte Count */
+
+ uint32_t command; /**< Command */
+ uint32_t command_arg; /**< Command Argument */
+ uint32_t response[4]; /**< Command Response */
+
+ uint32_t irq_mask; /**< Interrupt Mask */
+ uint32_t irq_status; /**< Raw Interrupt Status */
+ uint32_t status; /**< Status */
+
+ uint32_t fifo_wlevel; /**< FIFO Water Level */
+ uint32_t fifo_func_sel; /**< FIFO Function Select */
+ uint32_t debug_enable; /**< Debug Enable */
+ uint32_t auto12_arg; /**< Auto Command 12 Argument */
+ uint32_t newtiming_set; /**< SD New Timing Set */
+ uint32_t newtiming_debug; /**< SD New Timing Debug */
+ uint32_t hardware_rst; /**< Hardware Reset */
+ uint32_t dmac; /**< Internal DMA Controller Control */
+ uint32_t desc_base; /**< Descriptor List Base Address */
+ uint32_t dmac_status; /**< Internal DMA Controller Status */
+ uint32_t dmac_irq; /**< Internal DMA Controller IRQ Enable */
+ uint32_t card_threshold; /**< Card Threshold Control */
+ uint32_t startbit_detect; /**< eMMC DDR Start Bit Detection Control =
*/
+ uint32_t response_crc; /**< Response CRC */
+ uint32_t data_crc[8]; /**< Data CRC */
+ uint32_t status_crc; /**< Status CRC */
+
+ /** @} */
+
+} AwSdHostState;
+
+/**
+ * Allwinner SD Host Controller class-level struct.
+ *
+ * This struct is filled by each sunxi device specific code
+ * such that the generic code can use this struct to support
+ * all devices.
+ */
+typedef struct AwSdHostClass {
+ /*< private >*/
+ SysBusDeviceClass parent_class;
+ /*< public >*/
+
+ /** Maximum buffer size in bytes per DMA descriptor */
+ size_t max_desc_size;
+
+} AwSdHostClass;
+
+#endif /* HW_SD_ALLWINNER_SDHOST_H */
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index 2ae9c15311c..dc62c764167 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -27,6 +27,7 @@
#include "hw/boards.h"
#include "hw/usb/hcd-ohci.h"
=20
+#define AW_A10_MMC0_BASE 0x01c0f000
#define AW_A10_PIC_REG_BASE 0x01c20400
#define AW_A10_PIT_REG_BASE 0x01c20c00
#define AW_A10_UART0_REG_BASE 0x01c28000
@@ -64,6 +65,9 @@ static void aw_a10_init(Object *obj)
sizeof(s->ohci[i]), TYPE_SYSBUS_OHCI);
}
}
+
+ sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
+ TYPE_AW_SDHOST_SUN4I);
}
=20
static void aw_a10_realize(DeviceState *dev, Error **errp)
@@ -164,6 +168,13 @@ static void aw_a10_realize(DeviceState *dev, Error **e=
rrp)
qdev_get_gpio_in(dev, 64 + i));
}
}
+
+ /* SD/MMC */
+ qdev_init_nofail(DEVICE(&s->mmc0));
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, AW_A10_MMC0_BASE);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, =
32));
+ object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
+ "sd-bus", &error_abort);
}
=20
static void aw_a10_class_init(ObjectClass *oc, void *data)
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index deeea63f5f3..8c7ac61517a 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -38,6 +38,7 @@ const hwaddr allwinner_h3_memmap[] =3D {
[AW_H3_SRAM_A2] =3D 0x00044000,
[AW_H3_SRAM_C] =3D 0x00010000,
[AW_H3_SYSCTRL] =3D 0x01c00000,
+ [AW_H3_MMC0] =3D 0x01c0f000,
[AW_H3_SID] =3D 0x01c14000,
[AW_H3_EHCI0] =3D 0x01c1a000,
[AW_H3_OHCI0] =3D 0x01c1a400,
@@ -76,7 +77,6 @@ struct AwH3Unimplemented {
{ "lcd0", 0x01c0c000, 4 * KiB },
{ "lcd1", 0x01c0d000, 4 * KiB },
{ "ve", 0x01c0e000, 4 * KiB },
- { "mmc0", 0x01c0f000, 4 * KiB },
{ "mmc1", 0x01c10000, 4 * KiB },
{ "mmc2", 0x01c11000, 4 * KiB },
{ "crypto", 0x01c15000, 4 * KiB },
@@ -153,6 +153,7 @@ enum {
AW_H3_GIC_SPI_UART3 =3D 3,
AW_H3_GIC_SPI_TIMER0 =3D 18,
AW_H3_GIC_SPI_TIMER1 =3D 19,
+ AW_H3_GIC_SPI_MMC0 =3D 60,
AW_H3_GIC_SPI_EHCI0 =3D 72,
AW_H3_GIC_SPI_OHCI0 =3D 73,
AW_H3_GIC_SPI_EHCI1 =3D 74,
@@ -203,6 +204,9 @@ static void allwinner_h3_init(Object *obj)
TYPE_AW_SID);
object_property_add_alias(obj, "identifier", OBJECT(&s->sid),
"identifier", &error_abort);
+
+ sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
+ TYPE_AW_SDHOST_SUN5I);
}
=20
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -324,6 +328,15 @@ static void allwinner_h3_realize(DeviceState *dev, Err=
or **errp)
qdev_init_nofail(DEVICE(&s->sid));
sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
=20
+ /* SD/MMC */
+ qdev_init_nofail(DEVICE(&s->mmc0));
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC=
0));
+
+ object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
+ "sd-bus", &error_abort);
+
/* Universal Serial Bus */
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
qdev_get_gpio_in(DEVICE(&s->gic),
diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c
index d791817646b..0b8ba44976a 100644
--- a/hw/arm/cubieboard.c
+++ b/hw/arm/cubieboard.c
@@ -22,6 +22,7 @@
#include "sysemu/sysemu.h"
#include "hw/sysbus.h"
#include "hw/boards.h"
+#include "hw/qdev-properties.h"
#include "hw/arm/allwinner-a10.h"
=20
static struct arm_boot_info cubieboard_binfo =3D {
@@ -33,6 +34,10 @@ static void cubieboard_init(MachineState *machine)
{
AwA10State *a10;
Error *err =3D NULL;
+ DriveInfo *di;
+ BlockBackend *blk;
+ BusState *bus;
+ DeviceState *carddev;
=20
/* BIOS is not supported by this board */
if (bios_name) {
@@ -82,6 +87,16 @@ static void cubieboard_init(MachineState *machine)
exit(1);
}
=20
+ /* Retrieve SD bus */
+ di =3D drive_get_next(IF_SD);
+ blk =3D di ? blk_by_legacy_dinfo(di) : NULL;
+ bus =3D qdev_get_child_bus(DEVICE(a10), "sd-bus");
+
+ /* Plug in SD card */
+ carddev =3D qdev_create(bus, TYPE_SD_CARD);
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
+ object_property_set_bool(OBJECT(carddev), true, "realized", &error_fat=
al);
+
memory_region_add_subregion(get_system_memory(), AW_A10_SDRAM_BASE,
machine->ram);
=20
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index 4047c4c3863..e7ac7b1d148 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -35,6 +35,10 @@ static struct arm_boot_info orangepi_binfo =3D {
static void orangepi_init(MachineState *machine)
{
AwH3State *h3;
+ DriveInfo *di;
+ BlockBackend *blk;
+ BusState *bus;
+ DeviceState *carddev;
=20
/* BIOS is not supported by this board */
if (bios_name) {
@@ -76,6 +80,16 @@ static void orangepi_init(MachineState *machine)
/* Mark H3 object realized */
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
=20
+ /* Retrieve SD bus */
+ di =3D drive_get_next(IF_SD);
+ blk =3D di ? blk_by_legacy_dinfo(di) : NULL;
+ bus =3D qdev_get_child_bus(DEVICE(h3), "sd-bus");
+
+ /* Plug in SD card */
+ carddev =3D qdev_create(bus, TYPE_SD_CARD);
+ qdev_prop_set_drive(carddev, "drive", blk, &error_fatal);
+ object_property_set_bool(OBJECT(carddev), true, "realized", &error_fat=
al);
+
/* SDRAM */
memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRA=
M],
machine->ram);
@@ -89,6 +103,8 @@ static void orangepi_machine_init(MachineClass *mc)
{
mc->desc =3D "Orange Pi PC";
mc->init =3D orangepi_init;
+ mc->block_default_type =3D IF_SD;
+ mc->units_per_default_bus =3D 1;
mc->min_cpus =3D AW_H3_NUM_CPUS;
mc->max_cpus =3D AW_H3_NUM_CPUS;
mc->default_cpus =3D AW_H3_NUM_CPUS;
diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c
new file mode 100644
index 00000000000..f404e1fdb45
--- /dev/null
+++ b/hw/sd/allwinner-sdhost.c
@@ -0,0 +1,854 @@
+/*
+ * Allwinner (sun4i and above) SD Host Controller emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu/units.h"
+#include "sysemu/blockdev.h"
+#include "hw/irq.h"
+#include "hw/sd/allwinner-sdhost.h"
+#include "migration/vmstate.h"
+#include "trace.h"
+
+#define TYPE_AW_SDHOST_BUS "allwinner-sdhost-bus"
+#define AW_SDHOST_BUS(obj) \
+ OBJECT_CHECK(SDBus, (obj), TYPE_AW_SDHOST_BUS)
+
+/* SD Host register offsets */
+enum {
+ REG_SD_GCTL =3D 0x00, /* Global Control */
+ REG_SD_CKCR =3D 0x04, /* Clock Control */
+ REG_SD_TMOR =3D 0x08, /* Timeout */
+ REG_SD_BWDR =3D 0x0C, /* Bus Width */
+ REG_SD_BKSR =3D 0x10, /* Block Size */
+ REG_SD_BYCR =3D 0x14, /* Byte Count */
+ REG_SD_CMDR =3D 0x18, /* Command */
+ REG_SD_CAGR =3D 0x1C, /* Command Argument */
+ REG_SD_RESP0 =3D 0x20, /* Response Zero */
+ REG_SD_RESP1 =3D 0x24, /* Response One */
+ REG_SD_RESP2 =3D 0x28, /* Response Two */
+ REG_SD_RESP3 =3D 0x2C, /* Response Three */
+ REG_SD_IMKR =3D 0x30, /* Interrupt Mask */
+ REG_SD_MISR =3D 0x34, /* Masked Interrupt Status */
+ REG_SD_RISR =3D 0x38, /* Raw Interrupt Status */
+ REG_SD_STAR =3D 0x3C, /* Status */
+ REG_SD_FWLR =3D 0x40, /* FIFO Water Level */
+ REG_SD_FUNS =3D 0x44, /* FIFO Function Select */
+ REG_SD_DBGC =3D 0x50, /* Debug Enable */
+ REG_SD_A12A =3D 0x58, /* Auto command 12 argument */
+ REG_SD_NTSR =3D 0x5C, /* SD NewTiming Set */
+ REG_SD_SDBG =3D 0x60, /* SD newTiming Set Debug */
+ REG_SD_HWRST =3D 0x78, /* Hardware Reset Register */
+ REG_SD_DMAC =3D 0x80, /* Internal DMA Controller Control */
+ REG_SD_DLBA =3D 0x84, /* Descriptor List Base Address */
+ REG_SD_IDST =3D 0x88, /* Internal DMA Controller Status */
+ REG_SD_IDIE =3D 0x8C, /* Internal DMA Controller IRQ Enable */
+ REG_SD_THLDC =3D 0x100, /* Card Threshold Control */
+ REG_SD_DSBD =3D 0x10C, /* eMMC DDR Start Bit Detection Control */
+ REG_SD_RES_CRC =3D 0x110, /* Response CRC from card/eMMC */
+ REG_SD_DATA7_CRC =3D 0x114, /* CRC Data 7 from card/eMMC */
+ REG_SD_DATA6_CRC =3D 0x118, /* CRC Data 6 from card/eMMC */
+ REG_SD_DATA5_CRC =3D 0x11C, /* CRC Data 5 from card/eMMC */
+ REG_SD_DATA4_CRC =3D 0x120, /* CRC Data 4 from card/eMMC */
+ REG_SD_DATA3_CRC =3D 0x124, /* CRC Data 3 from card/eMMC */
+ REG_SD_DATA2_CRC =3D 0x128, /* CRC Data 2 from card/eMMC */
+ REG_SD_DATA1_CRC =3D 0x12C, /* CRC Data 1 from card/eMMC */
+ REG_SD_DATA0_CRC =3D 0x130, /* CRC Data 0 from card/eMMC */
+ REG_SD_CRC_STA =3D 0x134, /* CRC status from card/eMMC during write=
*/
+ REG_SD_FIFO =3D 0x200, /* Read/Write FIFO */
+};
+
+/* SD Host register flags */
+enum {
+ SD_GCTL_FIFO_AC_MOD =3D (1 << 31),
+ SD_GCTL_DDR_MOD_SEL =3D (1 << 10),
+ SD_GCTL_CD_DBC_ENB =3D (1 << 8),
+ SD_GCTL_DMA_ENB =3D (1 << 5),
+ SD_GCTL_INT_ENB =3D (1 << 4),
+ SD_GCTL_DMA_RST =3D (1 << 2),
+ SD_GCTL_FIFO_RST =3D (1 << 1),
+ SD_GCTL_SOFT_RST =3D (1 << 0),
+};
+
+enum {
+ SD_CMDR_LOAD =3D (1 << 31),
+ SD_CMDR_CLKCHANGE =3D (1 << 21),
+ SD_CMDR_WRITE =3D (1 << 10),
+ SD_CMDR_AUTOSTOP =3D (1 << 12),
+ SD_CMDR_DATA =3D (1 << 9),
+ SD_CMDR_RESPONSE_LONG =3D (1 << 7),
+ SD_CMDR_RESPONSE =3D (1 << 6),
+ SD_CMDR_CMDID_MASK =3D (0x3f),
+};
+
+enum {
+ SD_RISR_CARD_REMOVE =3D (1 << 31),
+ SD_RISR_CARD_INSERT =3D (1 << 30),
+ SD_RISR_SDIO_INTR =3D (1 << 16),
+ SD_RISR_AUTOCMD_DONE =3D (1 << 14),
+ SD_RISR_DATA_COMPLETE =3D (1 << 3),
+ SD_RISR_CMD_COMPLETE =3D (1 << 2),
+ SD_RISR_NO_RESPONSE =3D (1 << 1),
+};
+
+enum {
+ SD_STAR_CARD_PRESENT =3D (1 << 8),
+};
+
+enum {
+ SD_IDST_INT_SUMMARY =3D (1 << 8),
+ SD_IDST_RECEIVE_IRQ =3D (1 << 1),
+ SD_IDST_TRANSMIT_IRQ =3D (1 << 0),
+ SD_IDST_IRQ_MASK =3D (1 << 1) | (1 << 0) | (1 << 8),
+ SD_IDST_WR_MASK =3D (0x3ff),
+};
+
+/* SD Host register reset values */
+enum {
+ REG_SD_GCTL_RST =3D 0x00000300,
+ REG_SD_CKCR_RST =3D 0x0,
+ REG_SD_TMOR_RST =3D 0xFFFFFF40,
+ REG_SD_BWDR_RST =3D 0x0,
+ REG_SD_BKSR_RST =3D 0x00000200,
+ REG_SD_BYCR_RST =3D 0x00000200,
+ REG_SD_CMDR_RST =3D 0x0,
+ REG_SD_CAGR_RST =3D 0x0,
+ REG_SD_RESP_RST =3D 0x0,
+ REG_SD_IMKR_RST =3D 0x0,
+ REG_SD_MISR_RST =3D 0x0,
+ REG_SD_RISR_RST =3D 0x0,
+ REG_SD_STAR_RST =3D 0x00000100,
+ REG_SD_FWLR_RST =3D 0x000F0000,
+ REG_SD_FUNS_RST =3D 0x0,
+ REG_SD_DBGC_RST =3D 0x0,
+ REG_SD_A12A_RST =3D 0x0000FFFF,
+ REG_SD_NTSR_RST =3D 0x00000001,
+ REG_SD_SDBG_RST =3D 0x0,
+ REG_SD_HWRST_RST =3D 0x00000001,
+ REG_SD_DMAC_RST =3D 0x0,
+ REG_SD_DLBA_RST =3D 0x0,
+ REG_SD_IDST_RST =3D 0x0,
+ REG_SD_IDIE_RST =3D 0x0,
+ REG_SD_THLDC_RST =3D 0x0,
+ REG_SD_DSBD_RST =3D 0x0,
+ REG_SD_RES_CRC_RST =3D 0x0,
+ REG_SD_DATA_CRC_RST =3D 0x0,
+ REG_SD_CRC_STA_RST =3D 0x0,
+ REG_SD_FIFO_RST =3D 0x0,
+};
+
+/* Data transfer descriptor for DMA */
+typedef struct TransferDescriptor {
+ uint32_t status; /* Status flags */
+ uint32_t size; /* Data buffer size */
+ uint32_t addr; /* Data buffer address */
+ uint32_t next; /* Physical address of next descriptor */
+} TransferDescriptor;
+
+/* Data transfer descriptor flags */
+enum {
+ DESC_STATUS_HOLD =3D (1 << 31), /* Set when descriptor is in use by =
DMA */
+ DESC_STATUS_ERROR =3D (1 << 30), /* Set when DMA transfer error occur=
red */
+ DESC_STATUS_CHAIN =3D (1 << 4), /* Indicates chained descriptor. */
+ DESC_STATUS_FIRST =3D (1 << 3), /* Set on the first descriptor */
+ DESC_STATUS_LAST =3D (1 << 2), /* Set on the last descriptor */
+ DESC_STATUS_NOIRQ =3D (1 << 1), /* Skip raising interrupt after tran=
sfer */
+ DESC_SIZE_MASK =3D (0xfffffffc)
+};
+
+static void allwinner_sdhost_update_irq(AwSdHostState *s)
+{
+ uint32_t irq;
+
+ if (s->global_ctl & SD_GCTL_INT_ENB) {
+ irq =3D s->irq_status & s->irq_mask;
+ } else {
+ irq =3D 0;
+ }
+
+ trace_allwinner_sdhost_update_irq(irq);
+ qemu_set_irq(s->irq, irq);
+}
+
+static void allwinner_sdhost_update_transfer_cnt(AwSdHostState *s,
+ uint32_t bytes)
+{
+ if (s->transfer_cnt > bytes) {
+ s->transfer_cnt -=3D bytes;
+ } else {
+ s->transfer_cnt =3D 0;
+ }
+
+ if (!s->transfer_cnt) {
+ s->irq_status |=3D SD_RISR_DATA_COMPLETE;
+ }
+}
+
+static void allwinner_sdhost_set_inserted(DeviceState *dev, bool inserted)
+{
+ AwSdHostState *s =3D AW_SDHOST(dev);
+
+ trace_allwinner_sdhost_set_inserted(inserted);
+
+ if (inserted) {
+ s->irq_status |=3D SD_RISR_CARD_INSERT;
+ s->irq_status &=3D ~SD_RISR_CARD_REMOVE;
+ s->status |=3D SD_STAR_CARD_PRESENT;
+ } else {
+ s->irq_status &=3D ~SD_RISR_CARD_INSERT;
+ s->irq_status |=3D SD_RISR_CARD_REMOVE;
+ s->status &=3D ~SD_STAR_CARD_PRESENT;
+ }
+
+ allwinner_sdhost_update_irq(s);
+}
+
+static void allwinner_sdhost_send_command(AwSdHostState *s)
+{
+ SDRequest request;
+ uint8_t resp[16];
+ int rlen;
+
+ /* Auto clear load flag */
+ s->command &=3D ~SD_CMDR_LOAD;
+
+ /* Clock change does not actually interact with the SD bus */
+ if (!(s->command & SD_CMDR_CLKCHANGE)) {
+
+ /* Prepare request */
+ request.cmd =3D s->command & SD_CMDR_CMDID_MASK;
+ request.arg =3D s->command_arg;
+
+ /* Send request to SD bus */
+ rlen =3D sdbus_do_command(&s->sdbus, &request, resp);
+ if (rlen < 0) {
+ goto error;
+ }
+
+ /* If the command has a response, store it in the response registe=
rs */
+ if ((s->command & SD_CMDR_RESPONSE)) {
+ if (rlen =3D=3D 4 && !(s->command & SD_CMDR_RESPONSE_LONG)) {
+ s->response[0] =3D ldl_be_p(&resp[0]);
+ s->response[1] =3D s->response[2] =3D s->response[3] =3D 0;
+
+ } else if (rlen =3D=3D 16 && (s->command & SD_CMDR_RESPONSE_LO=
NG)) {
+ s->response[0] =3D ldl_be_p(&resp[12]);
+ s->response[1] =3D ldl_be_p(&resp[8]);
+ s->response[2] =3D ldl_be_p(&resp[4]);
+ s->response[3] =3D ldl_be_p(&resp[0]);
+ } else {
+ goto error;
+ }
+ }
+ }
+
+ /* Set interrupt status bits */
+ s->irq_status |=3D SD_RISR_CMD_COMPLETE;
+ return;
+
+error:
+ s->irq_status |=3D SD_RISR_NO_RESPONSE;
+}
+
+static void allwinner_sdhost_auto_stop(AwSdHostState *s)
+{
+ /*
+ * The stop command (CMD12) ensures the SD bus
+ * returns to the transfer state.
+ */
+ if ((s->command & SD_CMDR_AUTOSTOP) && (s->transfer_cnt =3D=3D 0)) {
+ /* First save current command registers */
+ uint32_t saved_cmd =3D s->command;
+ uint32_t saved_arg =3D s->command_arg;
+
+ /* Prepare stop command (CMD12) */
+ s->command &=3D ~SD_CMDR_CMDID_MASK;
+ s->command |=3D 12; /* CMD12 */
+ s->command_arg =3D 0;
+
+ /* Put the command on SD bus */
+ allwinner_sdhost_send_command(s);
+
+ /* Restore command values */
+ s->command =3D saved_cmd;
+ s->command_arg =3D saved_arg;
+
+ /* Set IRQ status bit for automatic stop done */
+ s->irq_status |=3D SD_RISR_AUTOCMD_DONE;
+ }
+}
+
+static uint32_t allwinner_sdhost_process_desc(AwSdHostState *s,
+ hwaddr desc_addr,
+ TransferDescriptor *desc,
+ bool is_write, uint32_t max_=
bytes)
+{
+ AwSdHostClass *klass =3D AW_SDHOST_GET_CLASS(s);
+ uint32_t num_done =3D 0;
+ uint32_t num_bytes =3D max_bytes;
+ uint8_t buf[1024];
+
+ /* Read descriptor */
+ cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
+ if (desc->size =3D=3D 0) {
+ desc->size =3D klass->max_desc_size;
+ } else if (desc->size > klass->max_desc_size) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA descriptor buffer size "
+ " is out-of-bounds: %" PRIu32 " > %zu",
+ __func__, desc->size, klass->max_desc_size);
+ desc->size =3D klass->max_desc_size;
+ }
+ if (desc->size < num_bytes) {
+ num_bytes =3D desc->size;
+ }
+
+ trace_allwinner_sdhost_process_desc(desc_addr, desc->size,
+ is_write, max_bytes);
+
+ while (num_done < num_bytes) {
+ /* Try to completely fill the local buffer */
+ uint32_t buf_bytes =3D num_bytes - num_done;
+ if (buf_bytes > sizeof(buf)) {
+ buf_bytes =3D sizeof(buf);
+ }
+
+ /* Write to SD bus */
+ if (is_write) {
+ cpu_physical_memory_read((desc->addr & DESC_SIZE_MASK) + num_d=
one,
+ buf, buf_bytes);
+
+ for (uint32_t i =3D 0; i < buf_bytes; i++) {
+ sdbus_write_data(&s->sdbus, buf[i]);
+ }
+
+ /* Read from SD bus */
+ } else {
+ for (uint32_t i =3D 0; i < buf_bytes; i++) {
+ buf[i] =3D sdbus_read_data(&s->sdbus);
+ }
+ cpu_physical_memory_write((desc->addr & DESC_SIZE_MASK) + num_=
done,
+ buf, buf_bytes);
+ }
+ num_done +=3D buf_bytes;
+ }
+
+ /* Clear hold flag and flush descriptor */
+ desc->status &=3D ~DESC_STATUS_HOLD;
+ cpu_physical_memory_write(desc_addr, desc, sizeof(*desc));
+
+ return num_done;
+}
+
+static void allwinner_sdhost_dma(AwSdHostState *s)
+{
+ TransferDescriptor desc;
+ hwaddr desc_addr =3D s->desc_base;
+ bool is_write =3D (s->command & SD_CMDR_WRITE);
+ uint32_t bytes_done =3D 0;
+
+ /* Check if DMA can be performed */
+ if (s->byte_count =3D=3D 0 || s->block_size =3D=3D 0 ||
+ !(s->global_ctl & SD_GCTL_DMA_ENB)) {
+ return;
+ }
+
+ /*
+ * For read operations, data must be available on the SD bus
+ * If not, it is an error and we should not act at all
+ */
+ if (!is_write && !sdbus_data_ready(&s->sdbus)) {
+ return;
+ }
+
+ /* Process the DMA descriptors until all data is copied */
+ while (s->byte_count > 0) {
+ bytes_done =3D allwinner_sdhost_process_desc(s, desc_addr, &desc,
+ is_write, s->byte_count=
);
+ allwinner_sdhost_update_transfer_cnt(s, bytes_done);
+
+ if (bytes_done <=3D s->byte_count) {
+ s->byte_count -=3D bytes_done;
+ } else {
+ s->byte_count =3D 0;
+ }
+
+ if (desc.status & DESC_STATUS_LAST) {
+ break;
+ } else {
+ desc_addr =3D desc.next;
+ }
+ }
+
+ /* Raise IRQ to signal DMA is completed */
+ s->irq_status |=3D SD_RISR_DATA_COMPLETE | SD_RISR_SDIO_INTR;
+
+ /* Update DMAC bits */
+ s->dmac_status |=3D SD_IDST_INT_SUMMARY;
+
+ if (is_write) {
+ s->dmac_status |=3D SD_IDST_TRANSMIT_IRQ;
+ } else {
+ s->dmac_status |=3D SD_IDST_RECEIVE_IRQ;
+ }
+}
+
+static uint64_t allwinner_sdhost_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ AwSdHostState *s =3D AW_SDHOST(opaque);
+ uint32_t res =3D 0;
+
+ switch (offset) {
+ case REG_SD_GCTL: /* Global Control */
+ res =3D s->global_ctl;
+ break;
+ case REG_SD_CKCR: /* Clock Control */
+ res =3D s->clock_ctl;
+ break;
+ case REG_SD_TMOR: /* Timeout */
+ res =3D s->timeout;
+ break;
+ case REG_SD_BWDR: /* Bus Width */
+ res =3D s->bus_width;
+ break;
+ case REG_SD_BKSR: /* Block Size */
+ res =3D s->block_size;
+ break;
+ case REG_SD_BYCR: /* Byte Count */
+ res =3D s->byte_count;
+ break;
+ case REG_SD_CMDR: /* Command */
+ res =3D s->command;
+ break;
+ case REG_SD_CAGR: /* Command Argument */
+ res =3D s->command_arg;
+ break;
+ case REG_SD_RESP0: /* Response Zero */
+ res =3D s->response[0];
+ break;
+ case REG_SD_RESP1: /* Response One */
+ res =3D s->response[1];
+ break;
+ case REG_SD_RESP2: /* Response Two */
+ res =3D s->response[2];
+ break;
+ case REG_SD_RESP3: /* Response Three */
+ res =3D s->response[3];
+ break;
+ case REG_SD_IMKR: /* Interrupt Mask */
+ res =3D s->irq_mask;
+ break;
+ case REG_SD_MISR: /* Masked Interrupt Status */
+ res =3D s->irq_status & s->irq_mask;
+ break;
+ case REG_SD_RISR: /* Raw Interrupt Status */
+ res =3D s->irq_status;
+ break;
+ case REG_SD_STAR: /* Status */
+ res =3D s->status;
+ break;
+ case REG_SD_FWLR: /* FIFO Water Level */
+ res =3D s->fifo_wlevel;
+ break;
+ case REG_SD_FUNS: /* FIFO Function Select */
+ res =3D s->fifo_func_sel;
+ break;
+ case REG_SD_DBGC: /* Debug Enable */
+ res =3D s->debug_enable;
+ break;
+ case REG_SD_A12A: /* Auto command 12 argument */
+ res =3D s->auto12_arg;
+ break;
+ case REG_SD_NTSR: /* SD NewTiming Set */
+ res =3D s->newtiming_set;
+ break;
+ case REG_SD_SDBG: /* SD newTiming Set Debug */
+ res =3D s->newtiming_debug;
+ break;
+ case REG_SD_HWRST: /* Hardware Reset Register */
+ res =3D s->hardware_rst;
+ break;
+ case REG_SD_DMAC: /* Internal DMA Controller Control */
+ res =3D s->dmac;
+ break;
+ case REG_SD_DLBA: /* Descriptor List Base Address */
+ res =3D s->desc_base;
+ break;
+ case REG_SD_IDST: /* Internal DMA Controller Status */
+ res =3D s->dmac_status;
+ break;
+ case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
+ res =3D s->dmac_irq;
+ break;
+ case REG_SD_THLDC: /* Card Threshold Control */
+ res =3D s->card_threshold;
+ break;
+ case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
+ res =3D s->startbit_detect;
+ break;
+ case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
+ res =3D s->response_crc;
+ break;
+ case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
+ case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
+ case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
+ case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
+ case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
+ case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
+ case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
+ case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
+ res =3D s->data_crc[((offset - REG_SD_DATA7_CRC) / sizeof(uint32_t=
))];
+ break;
+ case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation=
*/
+ res =3D s->status_crc;
+ break;
+ case REG_SD_FIFO: /* Read/Write FIFO */
+ if (sdbus_data_ready(&s->sdbus)) {
+ res =3D sdbus_read_data(&s->sdbus);
+ res |=3D sdbus_read_data(&s->sdbus) << 8;
+ res |=3D sdbus_read_data(&s->sdbus) << 16;
+ res |=3D sdbus_read_data(&s->sdbus) << 24;
+ allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
+ allwinner_sdhost_auto_stop(s);
+ allwinner_sdhost_update_irq(s);
+ } else {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: no data ready on SD bus\n",
+ __func__);
+ }
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
+ HWADDR_PRIx"\n", __func__, offset);
+ res =3D 0;
+ break;
+ }
+
+ trace_allwinner_sdhost_read(offset, res, size);
+ return res;
+}
+
+static void allwinner_sdhost_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ AwSdHostState *s =3D AW_SDHOST(opaque);
+
+ trace_allwinner_sdhost_write(offset, value, size);
+
+ switch (offset) {
+ case REG_SD_GCTL: /* Global Control */
+ s->global_ctl =3D value;
+ s->global_ctl &=3D ~(SD_GCTL_DMA_RST | SD_GCTL_FIFO_RST |
+ SD_GCTL_SOFT_RST);
+ allwinner_sdhost_update_irq(s);
+ break;
+ case REG_SD_CKCR: /* Clock Control */
+ s->clock_ctl =3D value;
+ break;
+ case REG_SD_TMOR: /* Timeout */
+ s->timeout =3D value;
+ break;
+ case REG_SD_BWDR: /* Bus Width */
+ s->bus_width =3D value;
+ break;
+ case REG_SD_BKSR: /* Block Size */
+ s->block_size =3D value;
+ break;
+ case REG_SD_BYCR: /* Byte Count */
+ s->byte_count =3D value;
+ s->transfer_cnt =3D value;
+ break;
+ case REG_SD_CMDR: /* Command */
+ s->command =3D value;
+ if (value & SD_CMDR_LOAD) {
+ allwinner_sdhost_send_command(s);
+ allwinner_sdhost_dma(s);
+ allwinner_sdhost_auto_stop(s);
+ }
+ allwinner_sdhost_update_irq(s);
+ break;
+ case REG_SD_CAGR: /* Command Argument */
+ s->command_arg =3D value;
+ break;
+ case REG_SD_RESP0: /* Response Zero */
+ s->response[0] =3D value;
+ break;
+ case REG_SD_RESP1: /* Response One */
+ s->response[1] =3D value;
+ break;
+ case REG_SD_RESP2: /* Response Two */
+ s->response[2] =3D value;
+ break;
+ case REG_SD_RESP3: /* Response Three */
+ s->response[3] =3D value;
+ break;
+ case REG_SD_IMKR: /* Interrupt Mask */
+ s->irq_mask =3D value;
+ allwinner_sdhost_update_irq(s);
+ break;
+ case REG_SD_MISR: /* Masked Interrupt Status */
+ case REG_SD_RISR: /* Raw Interrupt Status */
+ s->irq_status &=3D ~value;
+ allwinner_sdhost_update_irq(s);
+ break;
+ case REG_SD_STAR: /* Status */
+ s->status &=3D ~value;
+ allwinner_sdhost_update_irq(s);
+ break;
+ case REG_SD_FWLR: /* FIFO Water Level */
+ s->fifo_wlevel =3D value;
+ break;
+ case REG_SD_FUNS: /* FIFO Function Select */
+ s->fifo_func_sel =3D value;
+ break;
+ case REG_SD_DBGC: /* Debug Enable */
+ s->debug_enable =3D value;
+ break;
+ case REG_SD_A12A: /* Auto command 12 argument */
+ s->auto12_arg =3D value;
+ break;
+ case REG_SD_NTSR: /* SD NewTiming Set */
+ s->newtiming_set =3D value;
+ break;
+ case REG_SD_SDBG: /* SD newTiming Set Debug */
+ s->newtiming_debug =3D value;
+ break;
+ case REG_SD_HWRST: /* Hardware Reset Register */
+ s->hardware_rst =3D value;
+ break;
+ case REG_SD_DMAC: /* Internal DMA Controller Control */
+ s->dmac =3D value;
+ allwinner_sdhost_update_irq(s);
+ break;
+ case REG_SD_DLBA: /* Descriptor List Base Address */
+ s->desc_base =3D value;
+ break;
+ case REG_SD_IDST: /* Internal DMA Controller Status */
+ s->dmac_status &=3D (~SD_IDST_WR_MASK) | (~value & SD_IDST_WR_MASK=
);
+ allwinner_sdhost_update_irq(s);
+ break;
+ case REG_SD_IDIE: /* Internal DMA Controller Interrupt Enable */
+ s->dmac_irq =3D value;
+ allwinner_sdhost_update_irq(s);
+ break;
+ case REG_SD_THLDC: /* Card Threshold Control */
+ s->card_threshold =3D value;
+ break;
+ case REG_SD_DSBD: /* eMMC DDR Start Bit Detection Control */
+ s->startbit_detect =3D value;
+ break;
+ case REG_SD_FIFO: /* Read/Write FIFO */
+ sdbus_write_data(&s->sdbus, value & 0xff);
+ sdbus_write_data(&s->sdbus, (value >> 8) & 0xff);
+ sdbus_write_data(&s->sdbus, (value >> 16) & 0xff);
+ sdbus_write_data(&s->sdbus, (value >> 24) & 0xff);
+ allwinner_sdhost_update_transfer_cnt(s, sizeof(uint32_t));
+ allwinner_sdhost_auto_stop(s);
+ allwinner_sdhost_update_irq(s);
+ break;
+ case REG_SD_RES_CRC: /* Response CRC from card/eMMC */
+ case REG_SD_DATA7_CRC: /* CRC Data 7 from card/eMMC */
+ case REG_SD_DATA6_CRC: /* CRC Data 6 from card/eMMC */
+ case REG_SD_DATA5_CRC: /* CRC Data 5 from card/eMMC */
+ case REG_SD_DATA4_CRC: /* CRC Data 4 from card/eMMC */
+ case REG_SD_DATA3_CRC: /* CRC Data 3 from card/eMMC */
+ case REG_SD_DATA2_CRC: /* CRC Data 2 from card/eMMC */
+ case REG_SD_DATA1_CRC: /* CRC Data 1 from card/eMMC */
+ case REG_SD_DATA0_CRC: /* CRC Data 0 from card/eMMC */
+ case REG_SD_CRC_STA: /* CRC status from card/eMMC in write operation=
*/
+ break;
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset %"
+ HWADDR_PRIx"\n", __func__, offset);
+ break;
+ }
+}
+
+static const MemoryRegionOps allwinner_sdhost_ops =3D {
+ .read =3D allwinner_sdhost_read,
+ .write =3D allwinner_sdhost_write,
+ .endianness =3D DEVICE_NATIVE_ENDIAN,
+ .valid =3D {
+ .min_access_size =3D 4,
+ .max_access_size =3D 4,
+ },
+ .impl.min_access_size =3D 4,
+};
+
+static const VMStateDescription vmstate_allwinner_sdhost =3D {
+ .name =3D "allwinner-sdhost",
+ .version_id =3D 1,
+ .minimum_version_id =3D 1,
+ .fields =3D (VMStateField[]) {
+ VMSTATE_UINT32(global_ctl, AwSdHostState),
+ VMSTATE_UINT32(clock_ctl, AwSdHostState),
+ VMSTATE_UINT32(timeout, AwSdHostState),
+ VMSTATE_UINT32(bus_width, AwSdHostState),
+ VMSTATE_UINT32(block_size, AwSdHostState),
+ VMSTATE_UINT32(byte_count, AwSdHostState),
+ VMSTATE_UINT32(transfer_cnt, AwSdHostState),
+ VMSTATE_UINT32(command, AwSdHostState),
+ VMSTATE_UINT32(command_arg, AwSdHostState),
+ VMSTATE_UINT32_ARRAY(response, AwSdHostState, 4),
+ VMSTATE_UINT32(irq_mask, AwSdHostState),
+ VMSTATE_UINT32(irq_status, AwSdHostState),
+ VMSTATE_UINT32(status, AwSdHostState),
+ VMSTATE_UINT32(fifo_wlevel, AwSdHostState),
+ VMSTATE_UINT32(fifo_func_sel, AwSdHostState),
+ VMSTATE_UINT32(debug_enable, AwSdHostState),
+ VMSTATE_UINT32(auto12_arg, AwSdHostState),
+ VMSTATE_UINT32(newtiming_set, AwSdHostState),
+ VMSTATE_UINT32(newtiming_debug, AwSdHostState),
+ VMSTATE_UINT32(hardware_rst, AwSdHostState),
+ VMSTATE_UINT32(dmac, AwSdHostState),
+ VMSTATE_UINT32(desc_base, AwSdHostState),
+ VMSTATE_UINT32(dmac_status, AwSdHostState),
+ VMSTATE_UINT32(dmac_irq, AwSdHostState),
+ VMSTATE_UINT32(card_threshold, AwSdHostState),
+ VMSTATE_UINT32(startbit_detect, AwSdHostState),
+ VMSTATE_UINT32(response_crc, AwSdHostState),
+ VMSTATE_UINT32_ARRAY(data_crc, AwSdHostState, 8),
+ VMSTATE_UINT32(status_crc, AwSdHostState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void allwinner_sdhost_init(Object *obj)
+{
+ AwSdHostState *s =3D AW_SDHOST(obj);
+
+ qbus_create_inplace(&s->sdbus, sizeof(s->sdbus),
+ TYPE_AW_SDHOST_BUS, DEVICE(s), "sd-bus");
+
+ memory_region_init_io(&s->iomem, obj, &allwinner_sdhost_ops, s,
+ TYPE_AW_SDHOST, 4 * KiB);
+ sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->iomem);
+ sysbus_init_irq(SYS_BUS_DEVICE(s), &s->irq);
+}
+
+static void allwinner_sdhost_reset(DeviceState *dev)
+{
+ AwSdHostState *s =3D AW_SDHOST(dev);
+
+ s->global_ctl =3D REG_SD_GCTL_RST;
+ s->clock_ctl =3D REG_SD_CKCR_RST;
+ s->timeout =3D REG_SD_TMOR_RST;
+ s->bus_width =3D REG_SD_BWDR_RST;
+ s->block_size =3D REG_SD_BKSR_RST;
+ s->byte_count =3D REG_SD_BYCR_RST;
+ s->transfer_cnt =3D 0;
+
+ s->command =3D REG_SD_CMDR_RST;
+ s->command_arg =3D REG_SD_CAGR_RST;
+
+ for (int i =3D 0; i < ARRAY_SIZE(s->response); i++) {
+ s->response[i] =3D REG_SD_RESP_RST;
+ }
+
+ s->irq_mask =3D REG_SD_IMKR_RST;
+ s->irq_status =3D REG_SD_RISR_RST;
+ s->status =3D REG_SD_STAR_RST;
+
+ s->fifo_wlevel =3D REG_SD_FWLR_RST;
+ s->fifo_func_sel =3D REG_SD_FUNS_RST;
+ s->debug_enable =3D REG_SD_DBGC_RST;
+ s->auto12_arg =3D REG_SD_A12A_RST;
+ s->newtiming_set =3D REG_SD_NTSR_RST;
+ s->newtiming_debug =3D REG_SD_SDBG_RST;
+ s->hardware_rst =3D REG_SD_HWRST_RST;
+ s->dmac =3D REG_SD_DMAC_RST;
+ s->desc_base =3D REG_SD_DLBA_RST;
+ s->dmac_status =3D REG_SD_IDST_RST;
+ s->dmac_irq =3D REG_SD_IDIE_RST;
+ s->card_threshold =3D REG_SD_THLDC_RST;
+ s->startbit_detect =3D REG_SD_DSBD_RST;
+ s->response_crc =3D REG_SD_RES_CRC_RST;
+
+ for (int i =3D 0; i < ARRAY_SIZE(s->data_crc); i++) {
+ s->data_crc[i] =3D REG_SD_DATA_CRC_RST;
+ }
+
+ s->status_crc =3D REG_SD_CRC_STA_RST;
+}
+
+static void allwinner_sdhost_bus_class_init(ObjectClass *klass, void *data)
+{
+ SDBusClass *sbc =3D SD_BUS_CLASS(klass);
+
+ sbc->set_inserted =3D allwinner_sdhost_set_inserted;
+}
+
+static void allwinner_sdhost_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc =3D DEVICE_CLASS(klass);
+
+ dc->reset =3D allwinner_sdhost_reset;
+ dc->vmsd =3D &vmstate_allwinner_sdhost;
+}
+
+static void allwinner_sdhost_sun4i_class_init(ObjectClass *klass, void *da=
ta)
+{
+ AwSdHostClass *sc =3D AW_SDHOST_CLASS(klass);
+ sc->max_desc_size =3D 8 * KiB;
+}
+
+static void allwinner_sdhost_sun5i_class_init(ObjectClass *klass, void *da=
ta)
+{
+ AwSdHostClass *sc =3D AW_SDHOST_CLASS(klass);
+ sc->max_desc_size =3D 64 * KiB;
+}
+
+static TypeInfo allwinner_sdhost_info =3D {
+ .name =3D TYPE_AW_SDHOST,
+ .parent =3D TYPE_SYS_BUS_DEVICE,
+ .instance_init =3D allwinner_sdhost_init,
+ .instance_size =3D sizeof(AwSdHostState),
+ .class_init =3D allwinner_sdhost_class_init,
+ .class_size =3D sizeof(AwSdHostClass),
+ .abstract =3D true,
+};
+
+static const TypeInfo allwinner_sdhost_sun4i_info =3D {
+ .name =3D TYPE_AW_SDHOST_SUN4I,
+ .parent =3D TYPE_AW_SDHOST,
+ .class_init =3D allwinner_sdhost_sun4i_class_init,
+};
+
+static const TypeInfo allwinner_sdhost_sun5i_info =3D {
+ .name =3D TYPE_AW_SDHOST_SUN5I,
+ .parent =3D TYPE_AW_SDHOST,
+ .class_init =3D allwinner_sdhost_sun5i_class_init,
+};
+
+static const TypeInfo allwinner_sdhost_bus_info =3D {
+ .name =3D TYPE_AW_SDHOST_BUS,
+ .parent =3D TYPE_SD_BUS,
+ .instance_size =3D sizeof(SDBus),
+ .class_init =3D allwinner_sdhost_bus_class_init,
+};
+
+static void allwinner_sdhost_register_types(void)
+{
+ type_register_static(&allwinner_sdhost_info);
+ type_register_static(&allwinner_sdhost_sun4i_info);
+ type_register_static(&allwinner_sdhost_sun5i_info);
+ type_register_static(&allwinner_sdhost_bus_info);
+}
+
+type_init(allwinner_sdhost_register_types)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index f6422d54664..dd22fffdb0f 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -306,6 +306,7 @@ config ALLWINNER_H3
select UNIMP
select USB_OHCI
select USB_EHCI_SYSBUS
+ select SD
=20
config RASPI
bool
diff --git a/hw/sd/trace-events b/hw/sd/trace-events
index efcff666a20..5f09d32eb2c 100644
--- a/hw/sd/trace-events
+++ b/hw/sd/trace-events
@@ -1,5 +1,12 @@
# See docs/devel/tracing.txt for syntax documentation.
=20
+# allwinner-sdhost.c
+allwinner_sdhost_set_inserted(bool inserted) "inserted %u"
+allwinner_sdhost_process_desc(uint64_t desc_addr, uint32_t desc_size, bool=
is_write, uint32_t max_bytes) "desc_addr 0x%" PRIx64 " desc_size %" PRIu32=
" is_write %u max_bytes %" PRIu32
+allwinner_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offs=
et 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+allwinner_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "off=
set 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+allwinner_sdhost_update_irq(uint32_t irq) "IRQ bits 0x%" PRIx32
+
# bcm2835_sdhost.c
bcm2835_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset=
0x%" PRIx64 " data 0x%" PRIx64 " size %u"
bcm2835_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offse=
t 0x%" PRIx64 " data 0x%" PRIx64 " size %u"
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 20/36] hw/arm/allwinner-h3: add EMAC ethernet device
Date: Thu, 12 Mar 2020 16:44:43 +0000
Message-Id: <20200312164459.25924-21-peter.maydell@linaro.org>
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From: Niek Linnenbank <nieklinnenbank@gmail.com>
The Allwinner Sun8i System on Chip family includes an Ethernet MAC (EMAC)
which provides 10M/100M/1000M Ethernet connectivity. This commit
adds support for the Allwinner EMAC from the Sun8i family (H2+, H3, A33, et=
c),
including emulation for the following functionality:
* DMA transfers
* MII interface
* Transmit CRC calculation
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Message-id: 20200311221854.30370-10-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/net/Makefile.objs | 1 +
include/hw/arm/allwinner-h3.h | 3 +
include/hw/net/allwinner-sun8i-emac.h | 99 +++
hw/arm/allwinner-h3.c | 16 +-
hw/arm/orangepi.c | 3 +
hw/net/allwinner-sun8i-emac.c | 871 ++++++++++++++++++++++++++
hw/arm/Kconfig | 1 +
hw/net/Kconfig | 3 +
hw/net/trace-events | 10 +
9 files changed, 1006 insertions(+), 1 deletion(-)
create mode 100644 include/hw/net/allwinner-sun8i-emac.h
create mode 100644 hw/net/allwinner-sun8i-emac.c
diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs
index 991c46c7732..af4d1948666 100644
--- a/hw/net/Makefile.objs
+++ b/hw/net/Makefile.objs
@@ -23,6 +23,7 @@ common-obj-$(CONFIG_XGMAC) +=3D xgmac.o
common-obj-$(CONFIG_MIPSNET) +=3D mipsnet.o
common-obj-$(CONFIG_XILINX_AXI) +=3D xilinx_axienet.o
common-obj-$(CONFIG_ALLWINNER_EMAC) +=3D allwinner_emac.o
+common-obj-$(CONFIG_ALLWINNER_SUN8I_EMAC) +=3D allwinner-sun8i-emac.o
common-obj-$(CONFIG_IMX_FEC) +=3D imx_fec.o
=20
common-obj-$(CONFIG_CADENCE) +=3D cadence_gem.o
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index d71a4917ab8..f9b9a023734 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -44,6 +44,7 @@
#include "hw/misc/allwinner-h3-sysctrl.h"
#include "hw/misc/allwinner-sid.h"
#include "hw/sd/allwinner-sdhost.h"
+#include "hw/net/allwinner-sun8i-emac.h"
#include "target/arm/cpu.h"
=20
/**
@@ -77,6 +78,7 @@ enum {
AW_H3_UART1,
AW_H3_UART2,
AW_H3_UART3,
+ AW_H3_EMAC,
AW_H3_GIC_DIST,
AW_H3_GIC_CPU,
AW_H3_GIC_HYP,
@@ -120,6 +122,7 @@ typedef struct AwH3State {
AwH3SysCtrlState sysctrl;
AwSidState sid;
AwSdHostState mmc0;
+ AwSun8iEmacState emac;
GICState gic;
MemoryRegion sram_a1;
MemoryRegion sram_a2;
diff --git a/include/hw/net/allwinner-sun8i-emac.h b/include/hw/net/allwinn=
er-sun8i-emac.h
new file mode 100644
index 00000000000..eda034e96b2
--- /dev/null
+++ b/include/hw/net/allwinner-sun8i-emac.h
@@ -0,0 +1,99 @@
+/*
+ * Allwinner Sun8i Ethernet MAC emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_NET_ALLWINNER_SUN8I_EMAC_H
+#define HW_NET_ALLWINNER_SUN8I_EMAC_H
+
+#include "qom/object.h"
+#include "net/net.h"
+#include "hw/sysbus.h"
+
+/**
+ * Object model
+ * @{
+ */
+
+#define TYPE_AW_SUN8I_EMAC "allwinner-sun8i-emac"
+#define AW_SUN8I_EMAC(obj) \
+ OBJECT_CHECK(AwSun8iEmacState, (obj), TYPE_AW_SUN8I_EMAC)
+
+/** @} */
+
+/**
+ * Allwinner Sun8i EMAC object instance state
+ */
+typedef struct AwSun8iEmacState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ /** Maps I/O registers in physical memory */
+ MemoryRegion iomem;
+
+ /** Interrupt output signal to notify CPU */
+ qemu_irq irq;
+
+ /** Generic Network Interface Controller (NIC) for networking API */
+ NICState *nic;
+
+ /** Generic Network Interface Controller (NIC) configuration */
+ NICConf conf;
+
+ /**
+ * @name Media Independent Interface (MII)
+ * @{
+ */
+
+ uint8_t mii_phy_addr; /**< PHY address */
+ uint32_t mii_cr; /**< Control */
+ uint32_t mii_st; /**< Status */
+ uint32_t mii_adv; /**< Advertised Abilities */
+
+ /** @} */
+
+ /**
+ * @name Hardware Registers
+ * @{
+ */
+
+ uint32_t basic_ctl0; /**< Basic Control 0 */
+ uint32_t basic_ctl1; /**< Basic Control 1 */
+ uint32_t int_en; /**< Interrupt Enable */
+ uint32_t int_sta; /**< Interrupt Status */
+ uint32_t frm_flt; /**< Receive Frame Filter */
+
+ uint32_t rx_ctl0; /**< Receive Control 0 */
+ uint32_t rx_ctl1; /**< Receive Control 1 */
+ uint32_t rx_desc_head; /**< Receive Descriptor List Address */
+ uint32_t rx_desc_curr; /**< Current Receive Descriptor Address */
+
+ uint32_t tx_ctl0; /**< Transmit Control 0 */
+ uint32_t tx_ctl1; /**< Transmit Control 1 */
+ uint32_t tx_desc_head; /**< Transmit Descriptor List Address */
+ uint32_t tx_desc_curr; /**< Current Transmit Descriptor Address */
+ uint32_t tx_flowctl; /**< Transmit Flow Control */
+
+ uint32_t mii_cmd; /**< Management Interface Command */
+ uint32_t mii_data; /**< Management Interface Data */
+
+ /** @} */
+
+} AwSun8iEmacState;
+
+#endif /* HW_NET_ALLWINNER_SUN8I_H */
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index 8c7ac61517a..d1245d2b016 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -54,6 +54,7 @@ const hwaddr allwinner_h3_memmap[] =3D {
[AW_H3_UART1] =3D 0x01c28400,
[AW_H3_UART2] =3D 0x01c28800,
[AW_H3_UART3] =3D 0x01c28c00,
+ [AW_H3_EMAC] =3D 0x01c30000,
[AW_H3_GIC_DIST] =3D 0x01c81000,
[AW_H3_GIC_CPU] =3D 0x01c82000,
[AW_H3_GIC_HYP] =3D 0x01c84000,
@@ -106,7 +107,6 @@ struct AwH3Unimplemented {
{ "twi1", 0x01c2b000, 1 * KiB },
{ "twi2", 0x01c2b400, 1 * KiB },
{ "scr", 0x01c2c400, 1 * KiB },
- { "emac", 0x01c30000, 64 * KiB },
{ "gpu", 0x01c40000, 64 * KiB },
{ "hstmr", 0x01c60000, 4 * KiB },
{ "dramcom", 0x01c62000, 4 * KiB },
@@ -162,6 +162,7 @@ enum {
AW_H3_GIC_SPI_OHCI2 =3D 77,
AW_H3_GIC_SPI_EHCI3 =3D 78,
AW_H3_GIC_SPI_OHCI3 =3D 79,
+ AW_H3_GIC_SPI_EMAC =3D 82
};
=20
/* Allwinner H3 general constants */
@@ -207,6 +208,9 @@ static void allwinner_h3_init(Object *obj)
=20
sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
TYPE_AW_SDHOST_SUN5I);
+
+ sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
+ TYPE_AW_SUN8I_EMAC);
}
=20
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -337,6 +341,16 @@ static void allwinner_h3_realize(DeviceState *dev, Err=
or **errp)
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
"sd-bus", &error_abort);
=20
+ /* EMAC */
+ if (nd_table[0].used) {
+ qemu_check_nic_model(&nd_table[0], TYPE_AW_SUN8I_EMAC);
+ qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
+ }
+ qdev_init_nofail(DEVICE(&s->emac));
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
+ qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMA=
C));
+
/* Universal Serial Bus */
sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
qdev_get_gpio_in(DEVICE(&s->gic),
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index e7ac7b1d148..d65bbf8a2fe 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -77,6 +77,9 @@ static void orangepi_init(MachineState *machine)
warn_report("Security Identifier value does not include H3 prefix"=
);
}
=20
+ /* Setup EMAC properties */
+ object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort=
);
+
/* Mark H3 object realized */
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
=20
diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c
new file mode 100644
index 00000000000..3fc5e346401
--- /dev/null
+++ b/hw/net/allwinner-sun8i-emac.c
@@ -0,0 +1,871 @@
+/*
+ * Allwinner Sun8i Ethernet MAC emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "net/net.h"
+#include "hw/irq.h"
+#include "hw/qdev-properties.h"
+#include "qemu/log.h"
+#include "trace.h"
+#include "net/checksum.h"
+#include "qemu/module.h"
+#include "exec/cpu-common.h"
+#include "hw/net/allwinner-sun8i-emac.h"
+
+/* EMAC register offsets */
+enum {
+ REG_BASIC_CTL_0 =3D 0x0000, /* Basic Control 0 */
+ REG_BASIC_CTL_1 =3D 0x0004, /* Basic Control 1 */
+ REG_INT_STA =3D 0x0008, /* Interrupt Status */
+ REG_INT_EN =3D 0x000C, /* Interrupt Enable */
+ REG_TX_CTL_0 =3D 0x0010, /* Transmit Control 0 */
+ REG_TX_CTL_1 =3D 0x0014, /* Transmit Control 1 */
+ REG_TX_FLOW_CTL =3D 0x001C, /* Transmit Flow Control */
+ REG_TX_DMA_DESC_LIST =3D 0x0020, /* Transmit Descriptor List Address=
*/
+ REG_RX_CTL_0 =3D 0x0024, /* Receive Control 0 */
+ REG_RX_CTL_1 =3D 0x0028, /* Receive Control 1 */
+ REG_RX_DMA_DESC_LIST =3D 0x0034, /* Receive Descriptor List Address =
*/
+ REG_FRM_FLT =3D 0x0038, /* Receive Frame Filter */
+ REG_RX_HASH_0 =3D 0x0040, /* Receive Hash Table 0 */
+ REG_RX_HASH_1 =3D 0x0044, /* Receive Hash Table 1 */
+ REG_MII_CMD =3D 0x0048, /* Management Interface Command */
+ REG_MII_DATA =3D 0x004C, /* Management Interface Data */
+ REG_ADDR_HIGH =3D 0x0050, /* MAC Address High */
+ REG_ADDR_LOW =3D 0x0054, /* MAC Address Low */
+ REG_TX_DMA_STA =3D 0x00B0, /* Transmit DMA Status */
+ REG_TX_CUR_DESC =3D 0x00B4, /* Transmit Current Descriptor */
+ REG_TX_CUR_BUF =3D 0x00B8, /* Transmit Current Buffer */
+ REG_RX_DMA_STA =3D 0x00C0, /* Receive DMA Status */
+ REG_RX_CUR_DESC =3D 0x00C4, /* Receive Current Descriptor */
+ REG_RX_CUR_BUF =3D 0x00C8, /* Receive Current Buffer */
+ REG_RGMII_STA =3D 0x00D0, /* RGMII Status */
+};
+
+/* EMAC register flags */
+enum {
+ BASIC_CTL0_100Mbps =3D (0b11 << 2),
+ BASIC_CTL0_FD =3D (1 << 0),
+ BASIC_CTL1_SOFTRST =3D (1 << 0),
+};
+
+enum {
+ INT_STA_RGMII_LINK =3D (1 << 16),
+ INT_STA_RX_EARLY =3D (1 << 13),
+ INT_STA_RX_OVERFLOW =3D (1 << 12),
+ INT_STA_RX_TIMEOUT =3D (1 << 11),
+ INT_STA_RX_DMA_STOP =3D (1 << 10),
+ INT_STA_RX_BUF_UA =3D (1 << 9),
+ INT_STA_RX =3D (1 << 8),
+ INT_STA_TX_EARLY =3D (1 << 5),
+ INT_STA_TX_UNDERFLOW =3D (1 << 4),
+ INT_STA_TX_TIMEOUT =3D (1 << 3),
+ INT_STA_TX_BUF_UA =3D (1 << 2),
+ INT_STA_TX_DMA_STOP =3D (1 << 1),
+ INT_STA_TX =3D (1 << 0),
+};
+
+enum {
+ INT_EN_RX_EARLY =3D (1 << 13),
+ INT_EN_RX_OVERFLOW =3D (1 << 12),
+ INT_EN_RX_TIMEOUT =3D (1 << 11),
+ INT_EN_RX_DMA_STOP =3D (1 << 10),
+ INT_EN_RX_BUF_UA =3D (1 << 9),
+ INT_EN_RX =3D (1 << 8),
+ INT_EN_TX_EARLY =3D (1 << 5),
+ INT_EN_TX_UNDERFLOW =3D (1 << 4),
+ INT_EN_TX_TIMEOUT =3D (1 << 3),
+ INT_EN_TX_BUF_UA =3D (1 << 2),
+ INT_EN_TX_DMA_STOP =3D (1 << 1),
+ INT_EN_TX =3D (1 << 0),
+};
+
+enum {
+ TX_CTL0_TX_EN =3D (1 << 31),
+ TX_CTL1_TX_DMA_START =3D (1 << 31),
+ TX_CTL1_TX_DMA_EN =3D (1 << 30),
+ TX_CTL1_TX_FLUSH =3D (1 << 0),
+};
+
+enum {
+ RX_CTL0_RX_EN =3D (1 << 31),
+ RX_CTL0_STRIP_FCS =3D (1 << 28),
+ RX_CTL0_CRC_IPV4 =3D (1 << 27),
+};
+
+enum {
+ RX_CTL1_RX_DMA_START =3D (1 << 31),
+ RX_CTL1_RX_DMA_EN =3D (1 << 30),
+ RX_CTL1_RX_MD =3D (1 << 1),
+};
+
+enum {
+ RX_FRM_FLT_DIS_ADDR =3D (1 << 31),
+};
+
+enum {
+ MII_CMD_PHY_ADDR_SHIFT =3D (12),
+ MII_CMD_PHY_ADDR_MASK =3D (0xf000),
+ MII_CMD_PHY_REG_SHIFT =3D (4),
+ MII_CMD_PHY_REG_MASK =3D (0xf0),
+ MII_CMD_PHY_RW =3D (1 << 1),
+ MII_CMD_PHY_BUSY =3D (1 << 0),
+};
+
+enum {
+ TX_DMA_STA_STOP =3D (0b000),
+ TX_DMA_STA_RUN_FETCH =3D (0b001),
+ TX_DMA_STA_WAIT_STA =3D (0b010),
+};
+
+enum {
+ RX_DMA_STA_STOP =3D (0b000),
+ RX_DMA_STA_RUN_FETCH =3D (0b001),
+ RX_DMA_STA_WAIT_FRM =3D (0b011),
+};
+
+/* EMAC register reset values */
+enum {
+ REG_BASIC_CTL_1_RST =3D 0x08000000,
+};
+
+/* EMAC constants */
+enum {
+ AW_SUN8I_EMAC_MIN_PKT_SZ =3D 64
+};
+
+/* Transmit/receive frame descriptor */
+typedef struct FrameDescriptor {
+ uint32_t status;
+ uint32_t status2;
+ uint32_t addr;
+ uint32_t next;
+} FrameDescriptor;
+
+/* Frame descriptor flags */
+enum {
+ DESC_STATUS_CTL =3D (1 << 31),
+ DESC_STATUS2_BUF_SIZE_MASK =3D (0x7ff),
+};
+
+/* Transmit frame descriptor flags */
+enum {
+ TX_DESC_STATUS_LENGTH_ERR =3D (1 << 14),
+ TX_DESC_STATUS2_FIRST_DESC =3D (1 << 29),
+ TX_DESC_STATUS2_LAST_DESC =3D (1 << 30),
+ TX_DESC_STATUS2_CHECKSUM_MASK =3D (0x3 << 27),
+};
+
+/* Receive frame descriptor flags */
+enum {
+ RX_DESC_STATUS_FIRST_DESC =3D (1 << 9),
+ RX_DESC_STATUS_LAST_DESC =3D (1 << 8),
+ RX_DESC_STATUS_FRM_LEN_MASK =3D (0x3fff0000),
+ RX_DESC_STATUS_FRM_LEN_SHIFT =3D (16),
+ RX_DESC_STATUS_NO_BUF =3D (1 << 14),
+ RX_DESC_STATUS_HEADER_ERR =3D (1 << 7),
+ RX_DESC_STATUS_LENGTH_ERR =3D (1 << 4),
+ RX_DESC_STATUS_CRC_ERR =3D (1 << 1),
+ RX_DESC_STATUS_PAYLOAD_ERR =3D (1 << 0),
+ RX_DESC_STATUS2_RX_INT_CTL =3D (1 << 31),
+};
+
+/* MII register offsets */
+enum {
+ MII_REG_CR =3D (0x0), /* Control */
+ MII_REG_ST =3D (0x1), /* Status */
+ MII_REG_ID_HIGH =3D (0x2), /* Identifier High */
+ MII_REG_ID_LOW =3D (0x3), /* Identifier Low */
+ MII_REG_ADV =3D (0x4), /* Advertised abilities */
+ MII_REG_LPA =3D (0x5), /* Link partner abilities */
+};
+
+/* MII register flags */
+enum {
+ MII_REG_CR_RESET =3D (1 << 15),
+ MII_REG_CR_POWERDOWN =3D (1 << 11),
+ MII_REG_CR_10Mbit =3D (0),
+ MII_REG_CR_100Mbit =3D (1 << 13),
+ MII_REG_CR_1000Mbit =3D (1 << 6),
+ MII_REG_CR_AUTO_NEG =3D (1 << 12),
+ MII_REG_CR_AUTO_NEG_RESTART =3D (1 << 9),
+ MII_REG_CR_FULLDUPLEX =3D (1 << 8),
+};
+
+enum {
+ MII_REG_ST_100BASE_T4 =3D (1 << 15),
+ MII_REG_ST_100BASE_X_FD =3D (1 << 14),
+ MII_REG_ST_100BASE_X_HD =3D (1 << 13),
+ MII_REG_ST_10_FD =3D (1 << 12),
+ MII_REG_ST_10_HD =3D (1 << 11),
+ MII_REG_ST_100BASE_T2_FD =3D (1 << 10),
+ MII_REG_ST_100BASE_T2_HD =3D (1 << 9),
+ MII_REG_ST_AUTONEG_COMPLETE =3D (1 << 5),
+ MII_REG_ST_AUTONEG_AVAIL =3D (1 << 3),
+ MII_REG_ST_LINK_UP =3D (1 << 2),
+};
+
+enum {
+ MII_REG_LPA_10_HD =3D (1 << 5),
+ MII_REG_LPA_10_FD =3D (1 << 6),
+ MII_REG_LPA_100_HD =3D (1 << 7),
+ MII_REG_LPA_100_FD =3D (1 << 8),
+ MII_REG_LPA_PAUSE =3D (1 << 10),
+ MII_REG_LPA_ASYMPAUSE =3D (1 << 11),
+};
+
+/* MII constants */
+enum {
+ MII_PHY_ID_HIGH =3D 0x0044,
+ MII_PHY_ID_LOW =3D 0x1400,
+};
+
+static void allwinner_sun8i_emac_mii_set_link(AwSun8iEmacState *s,
+ bool link_active)
+{
+ if (link_active) {
+ s->mii_st |=3D MII_REG_ST_LINK_UP;
+ } else {
+ s->mii_st &=3D ~MII_REG_ST_LINK_UP;
+ }
+}
+
+static void allwinner_sun8i_emac_mii_reset(AwSun8iEmacState *s,
+ bool link_active)
+{
+ s->mii_cr =3D MII_REG_CR_100Mbit | MII_REG_CR_AUTO_NEG |
+ MII_REG_CR_FULLDUPLEX;
+ s->mii_st =3D MII_REG_ST_100BASE_T4 | MII_REG_ST_100BASE_X_FD |
+ MII_REG_ST_100BASE_X_HD | MII_REG_ST_10_FD | MII_REG_ST_10=
_HD |
+ MII_REG_ST_100BASE_T2_FD | MII_REG_ST_100BASE_T2_HD |
+ MII_REG_ST_AUTONEG_COMPLETE | MII_REG_ST_AUTONEG_AVAIL;
+ s->mii_adv =3D 0;
+
+ allwinner_sun8i_emac_mii_set_link(s, link_active);
+}
+
+static void allwinner_sun8i_emac_mii_cmd(AwSun8iEmacState *s)
+{
+ uint8_t addr, reg;
+
+ addr =3D (s->mii_cmd & MII_CMD_PHY_ADDR_MASK) >> MII_CMD_PHY_ADDR_SHIF=
T;
+ reg =3D (s->mii_cmd & MII_CMD_PHY_REG_MASK) >> MII_CMD_PHY_REG_SHIFT;
+
+ if (addr !=3D s->mii_phy_addr) {
+ return;
+ }
+
+ /* Read or write a PHY register? */
+ if (s->mii_cmd & MII_CMD_PHY_RW) {
+ trace_allwinner_sun8i_emac_mii_write_reg(reg, s->mii_data);
+
+ switch (reg) {
+ case MII_REG_CR:
+ if (s->mii_data & MII_REG_CR_RESET) {
+ allwinner_sun8i_emac_mii_reset(s, s->mii_st &
+ MII_REG_ST_LINK_UP);
+ } else {
+ s->mii_cr =3D s->mii_data & ~(MII_REG_CR_RESET |
+ MII_REG_CR_AUTO_NEG_RESTART);
+ }
+ break;
+ case MII_REG_ADV:
+ s->mii_adv =3D s->mii_data;
+ break;
+ case MII_REG_ID_HIGH:
+ case MII_REG_ID_LOW:
+ case MII_REG_LPA:
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to "
+ "unknown MII register 0x%x\n", reg);
+ break;
+ }
+ } else {
+ switch (reg) {
+ case MII_REG_CR:
+ s->mii_data =3D s->mii_cr;
+ break;
+ case MII_REG_ST:
+ s->mii_data =3D s->mii_st;
+ break;
+ case MII_REG_ID_HIGH:
+ s->mii_data =3D MII_PHY_ID_HIGH;
+ break;
+ case MII_REG_ID_LOW:
+ s->mii_data =3D MII_PHY_ID_LOW;
+ break;
+ case MII_REG_ADV:
+ s->mii_data =3D s->mii_adv;
+ break;
+ case MII_REG_LPA:
+ s->mii_data =3D MII_REG_LPA_10_HD | MII_REG_LPA_10_FD |
+ MII_REG_LPA_100_HD | MII_REG_LPA_100_FD |
+ MII_REG_LPA_PAUSE | MII_REG_LPA_ASYMPAUSE;
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to "
+ "unknown MII register 0x%x\n", reg);
+ s->mii_data =3D 0;
+ break;
+ }
+
+ trace_allwinner_sun8i_emac_mii_read_reg(reg, s->mii_data);
+ }
+}
+
+static void allwinner_sun8i_emac_update_irq(AwSun8iEmacState *s)
+{
+ qemu_set_irq(s->irq, (s->int_sta & s->int_en) !=3D 0);
+}
+
+static uint32_t allwinner_sun8i_emac_next_desc(FrameDescriptor *desc,
+ size_t min_size)
+{
+ uint32_t paddr =3D desc->next;
+
+ cpu_physical_memory_read(paddr, desc, sizeof(*desc));
+
+ if ((desc->status & DESC_STATUS_CTL) &&
+ (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >=3D min_size) {
+ return paddr;
+ } else {
+ return 0;
+ }
+}
+
+static uint32_t allwinner_sun8i_emac_get_desc(FrameDescriptor *desc,
+ uint32_t start_addr,
+ size_t min_size)
+{
+ uint32_t desc_addr =3D start_addr;
+
+ /* Note that the list is a cycle. Last entry points back to the head. =
*/
+ while (desc_addr !=3D 0) {
+ cpu_physical_memory_read(desc_addr, desc, sizeof(*desc));
+
+ if ((desc->status & DESC_STATUS_CTL) &&
+ (desc->status2 & DESC_STATUS2_BUF_SIZE_MASK) >=3D min_size) {
+ return desc_addr;
+ } else if (desc->next =3D=3D start_addr) {
+ break;
+ } else {
+ desc_addr =3D desc->next;
+ }
+ }
+
+ return 0;
+}
+
+static uint32_t allwinner_sun8i_emac_rx_desc(AwSun8iEmacState *s,
+ FrameDescriptor *desc,
+ size_t min_size)
+{
+ return allwinner_sun8i_emac_get_desc(desc, s->rx_desc_curr, min_size);
+}
+
+static uint32_t allwinner_sun8i_emac_tx_desc(AwSun8iEmacState *s,
+ FrameDescriptor *desc,
+ size_t min_size)
+{
+ return allwinner_sun8i_emac_get_desc(desc, s->tx_desc_head, min_size);
+}
+
+static void allwinner_sun8i_emac_flush_desc(FrameDescriptor *desc,
+ uint32_t phys_addr)
+{
+ cpu_physical_memory_write(phys_addr, desc, sizeof(*desc));
+}
+
+static int allwinner_sun8i_emac_can_receive(NetClientState *nc)
+{
+ AwSun8iEmacState *s =3D qemu_get_nic_opaque(nc);
+ FrameDescriptor desc;
+
+ return (s->rx_ctl0 & RX_CTL0_RX_EN) &&
+ (allwinner_sun8i_emac_rx_desc(s, &desc, 0) !=3D 0);
+}
+
+static ssize_t allwinner_sun8i_emac_receive(NetClientState *nc,
+ const uint8_t *buf,
+ size_t size)
+{
+ AwSun8iEmacState *s =3D qemu_get_nic_opaque(nc);
+ FrameDescriptor desc;
+ size_t bytes_left =3D size;
+ size_t desc_bytes =3D 0;
+ size_t pad_fcs_size =3D 4;
+ size_t padding =3D 0;
+
+ if (!(s->rx_ctl0 & RX_CTL0_RX_EN)) {
+ return -1;
+ }
+
+ s->rx_desc_curr =3D allwinner_sun8i_emac_rx_desc(s, &desc,
+ AW_SUN8I_EMAC_MIN_PKT_S=
Z);
+ if (!s->rx_desc_curr) {
+ s->int_sta |=3D INT_STA_RX_BUF_UA;
+ }
+
+ /* Keep filling RX descriptors until the whole frame is written */
+ while (s->rx_desc_curr && bytes_left > 0) {
+ desc.status &=3D ~DESC_STATUS_CTL;
+ desc.status &=3D ~RX_DESC_STATUS_FRM_LEN_MASK;
+
+ if (bytes_left =3D=3D size) {
+ desc.status |=3D RX_DESC_STATUS_FIRST_DESC;
+ }
+
+ if ((desc.status2 & DESC_STATUS2_BUF_SIZE_MASK) <
+ (bytes_left + pad_fcs_size)) {
+ desc_bytes =3D desc.status2 & DESC_STATUS2_BUF_SIZE_MASK;
+ desc.status |=3D desc_bytes << RX_DESC_STATUS_FRM_LEN_SHIFT;
+ } else {
+ padding =3D pad_fcs_size;
+ if (bytes_left < AW_SUN8I_EMAC_MIN_PKT_SZ) {
+ padding +=3D (AW_SUN8I_EMAC_MIN_PKT_SZ - bytes_left);
+ }
+
+ desc_bytes =3D (bytes_left);
+ desc.status |=3D RX_DESC_STATUS_LAST_DESC;
+ desc.status |=3D (bytes_left + padding)
+ << RX_DESC_STATUS_FRM_LEN_SHIFT;
+ }
+
+ cpu_physical_memory_write(desc.addr, buf, desc_bytes);
+ allwinner_sun8i_emac_flush_desc(&desc, s->rx_desc_curr);
+ trace_allwinner_sun8i_emac_receive(s->rx_desc_curr, desc.addr,
+ desc_bytes);
+
+ /* Check if frame needs to raise the receive interrupt */
+ if (!(desc.status2 & RX_DESC_STATUS2_RX_INT_CTL)) {
+ s->int_sta |=3D INT_STA_RX;
+ }
+
+ /* Increment variables */
+ buf +=3D desc_bytes;
+ bytes_left -=3D desc_bytes;
+
+ /* Move to the next descriptor */
+ s->rx_desc_curr =3D allwinner_sun8i_emac_next_desc(&desc, 64);
+ if (!s->rx_desc_curr) {
+ /* Not enough buffer space available */
+ s->int_sta |=3D INT_STA_RX_BUF_UA;
+ s->rx_desc_curr =3D s->rx_desc_head;
+ break;
+ }
+ }
+
+ /* Report receive DMA is finished */
+ s->rx_ctl1 &=3D ~RX_CTL1_RX_DMA_START;
+ allwinner_sun8i_emac_update_irq(s);
+
+ return size;
+}
+
+static void allwinner_sun8i_emac_transmit(AwSun8iEmacState *s)
+{
+ NetClientState *nc =3D qemu_get_queue(s->nic);
+ FrameDescriptor desc;
+ size_t bytes =3D 0;
+ size_t packet_bytes =3D 0;
+ size_t transmitted =3D 0;
+ static uint8_t packet_buf[2048];
+
+ s->tx_desc_curr =3D allwinner_sun8i_emac_tx_desc(s, &desc, 0);
+
+ /* Read all transmit descriptors */
+ while (s->tx_desc_curr !=3D 0) {
+
+ /* Read from physical memory into packet buffer */
+ bytes =3D desc.status2 & DESC_STATUS2_BUF_SIZE_MASK;
+ if (bytes + packet_bytes > sizeof(packet_buf)) {
+ desc.status |=3D TX_DESC_STATUS_LENGTH_ERR;
+ break;
+ }
+ cpu_physical_memory_read(desc.addr, packet_buf + packet_bytes, byt=
es);
+ packet_bytes +=3D bytes;
+ desc.status &=3D ~DESC_STATUS_CTL;
+ allwinner_sun8i_emac_flush_desc(&desc, s->tx_desc_curr);
+
+ /* After the last descriptor, send the packet */
+ if (desc.status2 & TX_DESC_STATUS2_LAST_DESC) {
+ if (desc.status2 & TX_DESC_STATUS2_CHECKSUM_MASK) {
+ net_checksum_calculate(packet_buf, packet_bytes);
+ }
+
+ qemu_send_packet(nc, packet_buf, packet_bytes);
+ trace_allwinner_sun8i_emac_transmit(s->tx_desc_curr, desc.addr,
+ bytes);
+
+ packet_bytes =3D 0;
+ transmitted++;
+ }
+ s->tx_desc_curr =3D allwinner_sun8i_emac_next_desc(&desc, 0);
+ }
+
+ /* Raise transmit completed interrupt */
+ if (transmitted > 0) {
+ s->int_sta |=3D INT_STA_TX;
+ s->tx_ctl1 &=3D ~TX_CTL1_TX_DMA_START;
+ allwinner_sun8i_emac_update_irq(s);
+ }
+}
+
+static void allwinner_sun8i_emac_reset(DeviceState *dev)
+{
+ AwSun8iEmacState *s =3D AW_SUN8I_EMAC(dev);
+ NetClientState *nc =3D qemu_get_queue(s->nic);
+
+ trace_allwinner_sun8i_emac_reset();
+
+ s->mii_cmd =3D 0;
+ s->mii_data =3D 0;
+ s->basic_ctl0 =3D 0;
+ s->basic_ctl1 =3D REG_BASIC_CTL_1_RST;
+ s->int_en =3D 0;
+ s->int_sta =3D 0;
+ s->frm_flt =3D 0;
+ s->rx_ctl0 =3D 0;
+ s->rx_ctl1 =3D RX_CTL1_RX_MD;
+ s->rx_desc_head =3D 0;
+ s->rx_desc_curr =3D 0;
+ s->tx_ctl0 =3D 0;
+ s->tx_ctl1 =3D 0;
+ s->tx_desc_head =3D 0;
+ s->tx_desc_curr =3D 0;
+ s->tx_flowctl =3D 0;
+
+ allwinner_sun8i_emac_mii_reset(s, !nc->link_down);
+}
+
+static uint64_t allwinner_sun8i_emac_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ AwSun8iEmacState *s =3D AW_SUN8I_EMAC(opaque);
+ uint64_t value =3D 0;
+ FrameDescriptor desc;
+
+ switch (offset) {
+ case REG_BASIC_CTL_0: /* Basic Control 0 */
+ value =3D s->basic_ctl0;
+ break;
+ case REG_BASIC_CTL_1: /* Basic Control 1 */
+ value =3D s->basic_ctl1;
+ break;
+ case REG_INT_STA: /* Interrupt Status */
+ value =3D s->int_sta;
+ break;
+ case REG_INT_EN: /* Interupt Enable */
+ value =3D s->int_en;
+ break;
+ case REG_TX_CTL_0: /* Transmit Control 0 */
+ value =3D s->tx_ctl0;
+ break;
+ case REG_TX_CTL_1: /* Transmit Control 1 */
+ value =3D s->tx_ctl1;
+ break;
+ case REG_TX_FLOW_CTL: /* Transmit Flow Control */
+ value =3D s->tx_flowctl;
+ break;
+ case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */
+ value =3D s->tx_desc_head;
+ break;
+ case REG_RX_CTL_0: /* Receive Control 0 */
+ value =3D s->rx_ctl0;
+ break;
+ case REG_RX_CTL_1: /* Receive Control 1 */
+ value =3D s->rx_ctl1;
+ break;
+ case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */
+ value =3D s->rx_desc_head;
+ break;
+ case REG_FRM_FLT: /* Receive Frame Filter */
+ value =3D s->frm_flt;
+ break;
+ case REG_RX_HASH_0: /* Receive Hash Table 0 */
+ case REG_RX_HASH_1: /* Receive Hash Table 1 */
+ break;
+ case REG_MII_CMD: /* Management Interface Command */
+ value =3D s->mii_cmd;
+ break;
+ case REG_MII_DATA: /* Management Interface Data */
+ value =3D s->mii_data;
+ break;
+ case REG_ADDR_HIGH: /* MAC Address High */
+ value =3D *(((uint32_t *) (s->conf.macaddr.a)) + 1);
+ break;
+ case REG_ADDR_LOW: /* MAC Address Low */
+ value =3D *(uint32_t *) (s->conf.macaddr.a);
+ break;
+ case REG_TX_DMA_STA: /* Transmit DMA Status */
+ break;
+ case REG_TX_CUR_DESC: /* Transmit Current Descriptor */
+ value =3D s->tx_desc_curr;
+ break;
+ case REG_TX_CUR_BUF: /* Transmit Current Buffer */
+ if (s->tx_desc_curr !=3D 0) {
+ cpu_physical_memory_read(s->tx_desc_curr, &desc, sizeof(desc));
+ value =3D desc.addr;
+ } else {
+ value =3D 0;
+ }
+ break;
+ case REG_RX_DMA_STA: /* Receive DMA Status */
+ break;
+ case REG_RX_CUR_DESC: /* Receive Current Descriptor */
+ value =3D s->rx_desc_curr;
+ break;
+ case REG_RX_CUR_BUF: /* Receive Current Buffer */
+ if (s->rx_desc_curr !=3D 0) {
+ cpu_physical_memory_read(s->rx_desc_curr, &desc, sizeof(desc));
+ value =3D desc.addr;
+ } else {
+ value =3D 0;
+ }
+ break;
+ case REG_RGMII_STA: /* RGMII Status */
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: read access to unknow=
n "
+ "EMAC register 0x" TARGET_FMT_plx "\n",
+ offset);
+ }
+
+ trace_allwinner_sun8i_emac_read(offset, value);
+ return value;
+}
+
+static void allwinner_sun8i_emac_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
+{
+ AwSun8iEmacState *s =3D AW_SUN8I_EMAC(opaque);
+ NetClientState *nc =3D qemu_get_queue(s->nic);
+
+ trace_allwinner_sun8i_emac_write(offset, value);
+
+ switch (offset) {
+ case REG_BASIC_CTL_0: /* Basic Control 0 */
+ s->basic_ctl0 =3D value;
+ break;
+ case REG_BASIC_CTL_1: /* Basic Control 1 */
+ if (value & BASIC_CTL1_SOFTRST) {
+ allwinner_sun8i_emac_reset(DEVICE(s));
+ value &=3D ~BASIC_CTL1_SOFTRST;
+ }
+ s->basic_ctl1 =3D value;
+ if (allwinner_sun8i_emac_can_receive(nc)) {
+ qemu_flush_queued_packets(nc);
+ }
+ break;
+ case REG_INT_STA: /* Interrupt Status */
+ s->int_sta &=3D ~value;
+ allwinner_sun8i_emac_update_irq(s);
+ break;
+ case REG_INT_EN: /* Interrupt Enable */
+ s->int_en =3D value;
+ allwinner_sun8i_emac_update_irq(s);
+ break;
+ case REG_TX_CTL_0: /* Transmit Control 0 */
+ s->tx_ctl0 =3D value;
+ break;
+ case REG_TX_CTL_1: /* Transmit Control 1 */
+ s->tx_ctl1 =3D value;
+ if (value & TX_CTL1_TX_DMA_EN) {
+ allwinner_sun8i_emac_transmit(s);
+ }
+ break;
+ case REG_TX_FLOW_CTL: /* Transmit Flow Control */
+ s->tx_flowctl =3D value;
+ break;
+ case REG_TX_DMA_DESC_LIST: /* Transmit Descriptor List Address */
+ s->tx_desc_head =3D value;
+ s->tx_desc_curr =3D value;
+ break;
+ case REG_RX_CTL_0: /* Receive Control 0 */
+ s->rx_ctl0 =3D value;
+ break;
+ case REG_RX_CTL_1: /* Receive Control 1 */
+ s->rx_ctl1 =3D value | RX_CTL1_RX_MD;
+ if ((value & RX_CTL1_RX_DMA_EN) &&
+ allwinner_sun8i_emac_can_receive(nc)) {
+ qemu_flush_queued_packets(nc);
+ }
+ break;
+ case REG_RX_DMA_DESC_LIST: /* Receive Descriptor List Address */
+ s->rx_desc_head =3D value;
+ s->rx_desc_curr =3D value;
+ break;
+ case REG_FRM_FLT: /* Receive Frame Filter */
+ s->frm_flt =3D value;
+ break;
+ case REG_RX_HASH_0: /* Receive Hash Table 0 */
+ case REG_RX_HASH_1: /* Receive Hash Table 1 */
+ break;
+ case REG_MII_CMD: /* Management Interface Command */
+ s->mii_cmd =3D value & ~MII_CMD_PHY_BUSY;
+ allwinner_sun8i_emac_mii_cmd(s);
+ break;
+ case REG_MII_DATA: /* Management Interface Data */
+ s->mii_data =3D value;
+ break;
+ case REG_ADDR_HIGH: /* MAC Address High */
+ s->conf.macaddr.a[4] =3D (value & 0xff);
+ s->conf.macaddr.a[5] =3D (value & 0xff00) >> 8;
+ break;
+ case REG_ADDR_LOW: /* MAC Address Low */
+ s->conf.macaddr.a[0] =3D (value & 0xff);
+ s->conf.macaddr.a[1] =3D (value & 0xff00) >> 8;
+ s->conf.macaddr.a[2] =3D (value & 0xff0000) >> 16;
+ s->conf.macaddr.a[3] =3D (value & 0xff000000) >> 24;
+ break;
+ case REG_TX_DMA_STA: /* Transmit DMA Status */
+ case REG_TX_CUR_DESC: /* Transmit Current Descriptor */
+ case REG_TX_CUR_BUF: /* Transmit Current Buffer */
+ case REG_RX_DMA_STA: /* Receive DMA Status */
+ case REG_RX_CUR_DESC: /* Receive Current Descriptor */
+ case REG_RX_CUR_BUF: /* Receive Current Buffer */
+ case REG_RGMII_STA: /* RGMII Status */
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP, "allwinner-h3-emac: write access to unkno=
wn "
+ "EMAC register 0x" TARGET_FMT_plx "\n",
+ offset);
+ }
+}
+
+static void allwinner_sun8i_emac_set_link(NetClientState *nc)
+{
+ AwSun8iEmacState *s =3D qemu_get_nic_opaque(nc);
+
+ trace_allwinner_sun8i_emac_set_link(!nc->link_down);
+ allwinner_sun8i_emac_mii_set_link(s, !nc->link_down);
+}
+
+static const MemoryRegionOps allwinner_sun8i_emac_mem_ops =3D {
+ .read =3D allwinner_sun8i_emac_read,
+ .write =3D allwinner_sun8i_emac_write,
+ .endianness =3D DEVICE_NATIVE_ENDIAN,
+ .valid =3D {
+ .min_access_size =3D 4,
+ .max_access_size =3D 4,
+ },
+ .impl.min_access_size =3D 4,
+};
+
+static NetClientInfo net_allwinner_sun8i_emac_info =3D {
+ .type =3D NET_CLIENT_DRIVER_NIC,
+ .size =3D sizeof(NICState),
+ .can_receive =3D allwinner_sun8i_emac_can_receive,
+ .receive =3D allwinner_sun8i_emac_receive,
+ .link_status_changed =3D allwinner_sun8i_emac_set_link,
+};
+
+static void allwinner_sun8i_emac_init(Object *obj)
+{
+ SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj);
+ AwSun8iEmacState *s =3D AW_SUN8I_EMAC(obj);
+
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_sun8i_emac_mem_=
ops,
+ s, TYPE_AW_SUN8I_EMAC, 64 * KiB);
+ sysbus_init_mmio(sbd, &s->iomem);
+ sysbus_init_irq(sbd, &s->irq);
+}
+
+static void allwinner_sun8i_emac_realize(DeviceState *dev, Error **errp)
+{
+ AwSun8iEmacState *s =3D AW_SUN8I_EMAC(dev);
+
+ qemu_macaddr_default_if_unset(&s->conf.macaddr);
+ s->nic =3D qemu_new_nic(&net_allwinner_sun8i_emac_info, &s->conf,
+ object_get_typename(OBJECT(dev)), dev->id, s);
+ qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
+}
+
+static Property allwinner_sun8i_emac_properties[] =3D {
+ DEFINE_NIC_PROPERTIES(AwSun8iEmacState, conf),
+ DEFINE_PROP_UINT8("phy-addr", AwSun8iEmacState, mii_phy_addr, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static int allwinner_sun8i_emac_post_load(void *opaque, int version_id)
+{
+ AwSun8iEmacState *s =3D opaque;
+
+ allwinner_sun8i_emac_set_link(qemu_get_queue(s->nic));
+
+ return 0;
+}
+
+static const VMStateDescription vmstate_aw_emac =3D {
+ .name =3D "allwinner-sun8i-emac",
+ .version_id =3D 1,
+ .minimum_version_id =3D 1,
+ .post_load =3D allwinner_sun8i_emac_post_load,
+ .fields =3D (VMStateField[]) {
+ VMSTATE_UINT8(mii_phy_addr, AwSun8iEmacState),
+ VMSTATE_UINT32(mii_cmd, AwSun8iEmacState),
+ VMSTATE_UINT32(mii_data, AwSun8iEmacState),
+ VMSTATE_UINT32(mii_cr, AwSun8iEmacState),
+ VMSTATE_UINT32(mii_st, AwSun8iEmacState),
+ VMSTATE_UINT32(mii_adv, AwSun8iEmacState),
+ VMSTATE_UINT32(basic_ctl0, AwSun8iEmacState),
+ VMSTATE_UINT32(basic_ctl1, AwSun8iEmacState),
+ VMSTATE_UINT32(int_en, AwSun8iEmacState),
+ VMSTATE_UINT32(int_sta, AwSun8iEmacState),
+ VMSTATE_UINT32(frm_flt, AwSun8iEmacState),
+ VMSTATE_UINT32(rx_ctl0, AwSun8iEmacState),
+ VMSTATE_UINT32(rx_ctl1, AwSun8iEmacState),
+ VMSTATE_UINT32(rx_desc_head, AwSun8iEmacState),
+ VMSTATE_UINT32(rx_desc_curr, AwSun8iEmacState),
+ VMSTATE_UINT32(tx_ctl0, AwSun8iEmacState),
+ VMSTATE_UINT32(tx_ctl1, AwSun8iEmacState),
+ VMSTATE_UINT32(tx_desc_head, AwSun8iEmacState),
+ VMSTATE_UINT32(tx_desc_curr, AwSun8iEmacState),
+ VMSTATE_UINT32(tx_flowctl, AwSun8iEmacState),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void allwinner_sun8i_emac_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc =3D DEVICE_CLASS(klass);
+
+ dc->realize =3D allwinner_sun8i_emac_realize;
+ dc->reset =3D allwinner_sun8i_emac_reset;
+ dc->vmsd =3D &vmstate_aw_emac;
+ device_class_set_props(dc, allwinner_sun8i_emac_properties);
+}
+
+static const TypeInfo allwinner_sun8i_emac_info =3D {
+ .name =3D TYPE_AW_SUN8I_EMAC,
+ .parent =3D TYPE_SYS_BUS_DEVICE,
+ .instance_size =3D sizeof(AwSun8iEmacState),
+ .instance_init =3D allwinner_sun8i_emac_init,
+ .class_init =3D allwinner_sun8i_emac_class_init,
+};
+
+static void allwinner_sun8i_emac_register_types(void)
+{
+ type_register_static(&allwinner_sun8i_emac_info);
+}
+
+type_init(allwinner_sun8i_emac_register_types)
diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig
index dd22fffdb0f..e5a876c8d14 100644
--- a/hw/arm/Kconfig
+++ b/hw/arm/Kconfig
@@ -300,6 +300,7 @@ config ALLWINNER_A10
config ALLWINNER_H3
bool
select ALLWINNER_A10_PIT
+ select ALLWINNER_SUN8I_EMAC
select SERIAL
select ARM_TIMER
select ARM_GIC
diff --git a/hw/net/Kconfig b/hw/net/Kconfig
index 54411d3dcc8..e43c96dae0b 100644
--- a/hw/net/Kconfig
+++ b/hw/net/Kconfig
@@ -79,6 +79,9 @@ config MIPSNET
config ALLWINNER_EMAC
bool
=20
+config ALLWINNER_SUN8I_EMAC
+ bool
+
config IMX_FEC
bool
=20
diff --git a/hw/net/trace-events b/hw/net/trace-events
index a1da98a643d..e18f883cfd4 100644
--- a/hw/net/trace-events
+++ b/hw/net/trace-events
@@ -1,5 +1,15 @@
# See docs/devel/tracing.txt for syntax documentation.
=20
+# allwinner-sun8i-emac.c
+allwinner_sun8i_emac_mii_write_reg(uint32_t reg, uint32_t value) "MII writ=
e: reg=3D0x%" PRIx32 " value=3D0x%" PRIx32
+allwinner_sun8i_emac_mii_read_reg(uint32_t reg, uint32_t value) "MII read:=
reg=3D0x%" PRIx32 " value=3D0x%" PRIx32
+allwinner_sun8i_emac_receive(uint32_t desc, uint32_t paddr, uint32_t bytes=
) "RX packet: desc=3D0x%" PRIx32 " paddr=3D0x%" PRIx32 " bytes=3D%" PRIu32
+allwinner_sun8i_emac_transmit(uint32_t desc, uint32_t paddr, uint32_t byte=
s) "TX packet: desc=3D0x%" PRIx32 " paddr=3D0x%" PRIx32 " bytes=3D%" PRIu32
+allwinner_sun8i_emac_reset(void) "HW reset"
+allwinner_sun8i_emac_set_link(bool active) "Set link: active=3D%u"
+allwinner_sun8i_emac_read(uint64_t offset, uint64_t val) "MMIO read: offse=
t=3D0x%" PRIx64 " value=3D0x%" PRIx64
+allwinner_sun8i_emac_write(uint64_t offset, uint64_t val) "MMIO write: off=
set=3D0x%" PRIx64 " value=3D0x%" PRIx64
+
# etraxfs_eth.c
mdio_phy_read(int regnum, uint16_t value) "read phy_reg:%d value:0x%04x"
mdio_phy_write(int regnum, uint16_t value) "write phy_reg:%d value:0x%04x"
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 21/36] hw/arm/allwinner-h3: add Boot ROM support
Date: Thu, 12 Mar 2020 16:44:44 +0000
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From: Niek Linnenbank <nieklinnenbank@gmail.com>
A real Allwinner H3 SoC contains a Boot ROM which is the
first code that runs right after the SoC is powered on.
The Boot ROM is responsible for loading user code (e.g. a bootloader)
from any of the supported external devices and writing the downloaded
code to internal SRAM. After loading the SoC begins executing the code
written to SRAM.
This commits adds emulation of the Boot ROM firmware setup functionality
by loading user code from SD card in the A1 SRAM. While the A1 SRAM is
64KiB, we limit the size to 32KiB because the real H3 Boot ROM also rejects
sizes larger than 32KiB. For reference, this behaviour is documented
by the Linux Sunxi project wiki at:
https://linux-sunxi.org/BROM#U-Boot_SPL_limitations
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Message-id: 20200311221854.30370-11-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/allwinner-h3.h | 21 +++++++++++++++++++++
hw/arm/allwinner-h3.c | 17 +++++++++++++++++
hw/arm/orangepi.c | 5 +++++
3 files changed, 43 insertions(+)
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index f9b9a023734..d338003724e 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -46,6 +46,7 @@
#include "hw/sd/allwinner-sdhost.h"
#include "hw/net/allwinner-sun8i-emac.h"
#include "target/arm/cpu.h"
+#include "sysemu/block-backend.h"
=20
/**
* Allwinner H3 device list
@@ -129,4 +130,24 @@ typedef struct AwH3State {
MemoryRegion sram_c;
} AwH3State;
=20
+/**
+ * Emulate Boot ROM firmware setup functionality.
+ *
+ * A real Allwinner H3 SoC contains a Boot ROM
+ * which is the first code that runs right after
+ * the SoC is powered on. The Boot ROM is responsible
+ * for loading user code (e.g. a bootloader) from any
+ * of the supported external devices and writing the
+ * downloaded code to internal SRAM. After loading the SoC
+ * begins executing the code written to SRAM.
+ *
+ * This function emulates the Boot ROM by copying 32 KiB
+ * of data from the given block device and writes it to
+ * the start of the first internal SRAM memory.
+ *
+ * @s: Allwinner H3 state object pointer
+ * @blk: Block backend device object pointer
+ */
+void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk);
+
#endif /* HW_ARM_ALLWINNER_H3_H */
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index d1245d2b016..a9767c70c08 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -29,6 +29,7 @@
#include "hw/char/serial.h"
#include "hw/misc/unimp.h"
#include "hw/usb/hcd-ehci.h"
+#include "hw/loader.h"
#include "sysemu/sysemu.h"
#include "hw/arm/allwinner-h3.h"
=20
@@ -170,6 +171,22 @@ enum {
AW_H3_GIC_NUM_SPI =3D 128
};
=20
+void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk)
+{
+ const int64_t rom_size =3D 32 * KiB;
+ g_autofree uint8_t *buffer =3D g_new0(uint8_t, rom_size);
+
+ if (blk_pread(blk, 8 * KiB, buffer, rom_size) < 0) {
+ error_setg(&error_fatal, "%s: failed to read BlockBackend data",
+ __func__);
+ return;
+ }
+
+ rom_add_blob("allwinner-h3.bootrom", buffer, rom_size,
+ rom_size, s->memmap[AW_H3_SRAM_A1],
+ NULL, NULL, NULL, NULL, false);
+}
+
static void allwinner_h3_init(Object *obj)
{
AwH3State *s =3D AW_H3(obj);
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index d65bbf8a2fe..b8ebcb08b76 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -97,6 +97,11 @@ static void orangepi_init(MachineState *machine)
memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRA=
M],
machine->ram);
=20
+ /* Load target kernel or start using BootROM */
+ if (!machine->kernel_filename && blk_is_available(blk)) {
+ /* Use Boot ROM to copy data from SD card to SRAM */
+ allwinner_h3_bootrom_setup(h3, blk);
+ }
orangepi_binfo.loader_start =3D h3->memmap[AW_H3_SDRAM];
orangepi_binfo.ram_size =3D machine->ram_size;
arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 22/36] hw/arm/allwinner-h3: add SDRAM controller device
Date: Thu, 12 Mar 2020 16:44:45 +0000
Message-Id: <20200312164459.25924-23-peter.maydell@linaro.org>
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From: Niek Linnenbank <nieklinnenbank@gmail.com>
In the Allwinner H3 SoC the SDRAM controller is responsible
for interfacing with the external Synchronous Dynamic Random
Access Memory (SDRAM). Types of memory that the SDRAM controller
supports are DDR2/DDR3 and capacities of up to 2GiB. This commit
adds emulation support of the Allwinner H3 SDRAM controller.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Message-id: 20200311221854.30370-12-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/misc/Makefile.objs | 1 +
include/hw/arm/allwinner-h3.h | 5 +
include/hw/misc/allwinner-h3-dramc.h | 106 ++++++++
hw/arm/allwinner-h3.c | 19 +-
hw/arm/orangepi.c | 6 +
hw/misc/allwinner-h3-dramc.c | 358 +++++++++++++++++++++++++++
hw/misc/trace-events | 10 +
7 files changed, 502 insertions(+), 3 deletions(-)
create mode 100644 include/hw/misc/allwinner-h3-dramc.h
create mode 100644 hw/misc/allwinner-h3-dramc.c
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index daa734036eb..68aae2eabbc 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -30,6 +30,7 @@ common-obj-$(CONFIG_IVSHMEM_DEVICE) +=3D ivshmem.o
=20
common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-ccu.o
obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-cpucfg.o
+common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-dramc.o
common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-h3-sysctrl.o
common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-sid.o
common-obj-$(CONFIG_REALVIEW) +=3D arm_sysctl.o
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index d338003724e..065d020c738 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -41,6 +41,7 @@
#include "hw/intc/arm_gic.h"
#include "hw/misc/allwinner-h3-ccu.h"
#include "hw/misc/allwinner-cpucfg.h"
+#include "hw/misc/allwinner-h3-dramc.h"
#include "hw/misc/allwinner-h3-sysctrl.h"
#include "hw/misc/allwinner-sid.h"
#include "hw/sd/allwinner-sdhost.h"
@@ -80,6 +81,9 @@ enum {
AW_H3_UART2,
AW_H3_UART3,
AW_H3_EMAC,
+ AW_H3_DRAMCOM,
+ AW_H3_DRAMCTL,
+ AW_H3_DRAMPHY,
AW_H3_GIC_DIST,
AW_H3_GIC_CPU,
AW_H3_GIC_HYP,
@@ -120,6 +124,7 @@ typedef struct AwH3State {
AwA10PITState timer;
AwH3ClockCtlState ccu;
AwCpuCfgState cpucfg;
+ AwH3DramCtlState dramc;
AwH3SysCtrlState sysctrl;
AwSidState sid;
AwSdHostState mmc0;
diff --git a/include/hw/misc/allwinner-h3-dramc.h b/include/hw/misc/allwinn=
er-h3-dramc.h
new file mode 100644
index 00000000000..bacdf236b78
--- /dev/null
+++ b/include/hw/misc/allwinner-h3-dramc.h
@@ -0,0 +1,106 @@
+/*
+ * Allwinner H3 SDRAM Controller emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_MISC_ALLWINNER_H3_DRAMC_H
+#define HW_MISC_ALLWINNER_H3_DRAMC_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+#include "exec/hwaddr.h"
+
+/**
+ * Constants
+ * @{
+ */
+
+/** Highest register address used by DRAMCOM module */
+#define AW_H3_DRAMCOM_REGS_MAXADDR (0x804)
+
+/** Total number of known DRAMCOM registers */
+#define AW_H3_DRAMCOM_REGS_NUM (AW_H3_DRAMCOM_REGS_MAXADDR / \
+ sizeof(uint32_t))
+
+/** Highest register address used by DRAMCTL module */
+#define AW_H3_DRAMCTL_REGS_MAXADDR (0x88c)
+
+/** Total number of known DRAMCTL registers */
+#define AW_H3_DRAMCTL_REGS_NUM (AW_H3_DRAMCTL_REGS_MAXADDR / \
+ sizeof(uint32_t))
+
+/** Highest register address used by DRAMPHY module */
+#define AW_H3_DRAMPHY_REGS_MAXADDR (0x4)
+
+/** Total number of known DRAMPHY registers */
+#define AW_H3_DRAMPHY_REGS_NUM (AW_H3_DRAMPHY_REGS_MAXADDR / \
+ sizeof(uint32_t))
+
+/** @} */
+
+/**
+ * Object model
+ * @{
+ */
+
+#define TYPE_AW_H3_DRAMC "allwinner-h3-dramc"
+#define AW_H3_DRAMC(obj) \
+ OBJECT_CHECK(AwH3DramCtlState, (obj), TYPE_AW_H3_DRAMC)
+
+/** @} */
+
+/**
+ * Allwinner H3 SDRAM Controller object instance state.
+ */
+typedef struct AwH3DramCtlState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ /** Physical base address for start of RAM */
+ hwaddr ram_addr;
+
+ /** Total RAM size in megabytes */
+ uint32_t ram_size;
+
+ /**
+ * @name Memory Regions
+ * @{
+ */
+
+ MemoryRegion row_mirror; /**< Simulates rows for RAM size detect=
ion */
+ MemoryRegion row_mirror_alias; /**< Alias of the row which is mirrored=
*/
+ MemoryRegion dramcom_iomem; /**< DRAMCOM module I/O registers */
+ MemoryRegion dramctl_iomem; /**< DRAMCTL module I/O registers */
+ MemoryRegion dramphy_iomem; /**< DRAMPHY module I/O registers */
+
+ /** @} */
+
+ /**
+ * @name Hardware Registers
+ * @{
+ */
+
+ uint32_t dramcom[AW_H3_DRAMCOM_REGS_NUM]; /**< Array of DRAMCOM regist=
ers */
+ uint32_t dramctl[AW_H3_DRAMCTL_REGS_NUM]; /**< Array of DRAMCTL regist=
ers */
+ uint32_t dramphy[AW_H3_DRAMPHY_REGS_NUM] ;/**< Array of DRAMPHY regist=
ers */
+
+ /** @} */
+
+} AwH3DramCtlState;
+
+#endif /* HW_MISC_ALLWINNER_H3_DRAMC_H */
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index a9767c70c08..c0a2ecfee81 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -56,6 +56,9 @@ const hwaddr allwinner_h3_memmap[] =3D {
[AW_H3_UART2] =3D 0x01c28800,
[AW_H3_UART3] =3D 0x01c28c00,
[AW_H3_EMAC] =3D 0x01c30000,
+ [AW_H3_DRAMCOM] =3D 0x01c62000,
+ [AW_H3_DRAMCTL] =3D 0x01c63000,
+ [AW_H3_DRAMPHY] =3D 0x01c65000,
[AW_H3_GIC_DIST] =3D 0x01c81000,
[AW_H3_GIC_CPU] =3D 0x01c82000,
[AW_H3_GIC_HYP] =3D 0x01c84000,
@@ -110,9 +113,6 @@ struct AwH3Unimplemented {
{ "scr", 0x01c2c400, 1 * KiB },
{ "gpu", 0x01c40000, 64 * KiB },
{ "hstmr", 0x01c60000, 4 * KiB },
- { "dramcom", 0x01c62000, 4 * KiB },
- { "dramctl0", 0x01c63000, 4 * KiB },
- { "dramphy0", 0x01c65000, 4 * KiB },
{ "spi0", 0x01c68000, 4 * KiB },
{ "spi1", 0x01c69000, 4 * KiB },
{ "csi", 0x01cb0000, 320 * KiB },
@@ -228,6 +228,13 @@ static void allwinner_h3_init(Object *obj)
=20
sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac),
TYPE_AW_SUN8I_EMAC);
+
+ sysbus_init_child_obj(obj, "dramc", &s->dramc, sizeof(s->dramc),
+ TYPE_AW_H3_DRAMC);
+ object_property_add_alias(obj, "ram-addr", OBJECT(&s->dramc),
+ "ram-addr", &error_abort);
+ object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
+ "ram-size", &error_abort);
}
=20
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -412,6 +419,12 @@ static void allwinner_h3_realize(DeviceState *dev, Err=
or **errp)
qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
=20
+ /* DRAMC */
+ qdev_init_nofail(DEVICE(&s->dramc));
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DRAMCOM]=
);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]=
);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]=
);
+
/* Unimplemented devices */
for (i =3D 0; i < ARRAY_SIZE(unimplemented); i++) {
create_unimplemented_device(unimplemented[i].device_name,
diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c
index b8ebcb08b76..181f5badab7 100644
--- a/hw/arm/orangepi.c
+++ b/hw/arm/orangepi.c
@@ -80,6 +80,12 @@ static void orangepi_init(MachineState *machine)
/* Setup EMAC properties */
object_property_set_int(OBJECT(&h3->emac), 1, "phy-addr", &error_abort=
);
=20
+ /* DRAMC */
+ object_property_set_uint(OBJECT(h3), h3->memmap[AW_H3_SDRAM],
+ "ram-addr", &error_abort);
+ object_property_set_int(OBJECT(h3), machine->ram_size / MiB, "ram-size=
",
+ &error_abort);
+
/* Mark H3 object realized */
object_property_set_bool(OBJECT(h3), true, "realized", &error_abort);
=20
diff --git a/hw/misc/allwinner-h3-dramc.c b/hw/misc/allwinner-h3-dramc.c
new file mode 100644
index 00000000000..2b5260260e7
--- /dev/null
+++ b/hw/misc/allwinner-h3-dramc.c
@@ -0,0 +1,358 @@
+/*
+ * Allwinner H3 SDRAM Controller emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "qemu/error-report.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "exec/address-spaces.h"
+#include "hw/qdev-properties.h"
+#include "qapi/error.h"
+#include "hw/misc/allwinner-h3-dramc.h"
+#include "trace.h"
+
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
+
+/* DRAMCOM register offsets */
+enum {
+ REG_DRAMCOM_CR =3D 0x0000, /* Control Register */
+};
+
+/* DRAMCTL register offsets */
+enum {
+ REG_DRAMCTL_PIR =3D 0x0000, /* PHY Initialization Register */
+ REG_DRAMCTL_PGSR =3D 0x0010, /* PHY General Status Register */
+ REG_DRAMCTL_STATR =3D 0x0018, /* Status Register */
+};
+
+/* DRAMCTL register flags */
+enum {
+ REG_DRAMCTL_PGSR_INITDONE =3D (1 << 0),
+};
+
+enum {
+ REG_DRAMCTL_STATR_ACTIVE =3D (1 << 0),
+};
+
+static void allwinner_h3_dramc_map_rows(AwH3DramCtlState *s, uint8_t row_b=
its,
+ uint8_t bank_bits, uint16_t page_s=
ize)
+{
+ /*
+ * This function simulates row addressing behavior when bootloader
+ * software attempts to detect the amount of available SDRAM. In U-Boot
+ * the controller is configured with the widest row addressing availab=
le.
+ * Then a pattern is written to RAM at an offset on the row boundary s=
ize.
+ * If the value read back equals the value read back from the
+ * start of RAM, the bootloader knows the amount of row bits.
+ *
+ * This function inserts a mirrored memory region when the configured =
row
+ * bits are not matching the actual emulated memory, to simulate the
+ * same behavior on hardware as expected by the bootloader.
+ */
+ uint8_t row_bits_actual =3D 0;
+
+ /* Calculate the actual row bits using the ram_size property */
+ for (uint8_t i =3D 8; i < 12; i++) {
+ if (1 << i =3D=3D s->ram_size) {
+ row_bits_actual =3D i + 3;
+ break;
+ }
+ }
+
+ if (s->ram_size =3D=3D (1 << (row_bits - 3))) {
+ /* When row bits is the expected value, remove the mirror */
+ memory_region_set_enabled(&s->row_mirror_alias, false);
+ trace_allwinner_h3_dramc_rowmirror_disable();
+
+ } else if (row_bits_actual) {
+ /* Row bits not matching ram_size, install the rows mirror */
+ hwaddr row_mirror =3D s->ram_addr + ((1 << (row_bits_actual +
+ bank_bits)) * page_size);
+
+ memory_region_set_enabled(&s->row_mirror_alias, true);
+ memory_region_set_address(&s->row_mirror_alias, row_mirror);
+
+ trace_allwinner_h3_dramc_rowmirror_enable(row_mirror);
+ }
+}
+
+static uint64_t allwinner_h3_dramcom_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ const AwH3DramCtlState *s =3D AW_H3_DRAMC(opaque);
+ const uint32_t idx =3D REG_INDEX(offset);
+
+ if (idx >=3D AW_H3_DRAMCOM_REGS_NUM) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return 0;
+ }
+
+ trace_allwinner_h3_dramcom_read(offset, s->dramcom[idx], size);
+
+ return s->dramcom[idx];
+}
+
+static void allwinner_h3_dramcom_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AwH3DramCtlState *s =3D AW_H3_DRAMC(opaque);
+ const uint32_t idx =3D REG_INDEX(offset);
+
+ trace_allwinner_h3_dramcom_write(offset, val, size);
+
+ if (idx >=3D AW_H3_DRAMCOM_REGS_NUM) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return;
+ }
+
+ switch (offset) {
+ case REG_DRAMCOM_CR: /* Control Register */
+ allwinner_h3_dramc_map_rows(s, ((val >> 4) & 0xf) + 1,
+ ((val >> 2) & 0x1) + 2,
+ 1 << (((val >> 8) & 0xf) + 3));
+ break;
+ default:
+ break;
+ };
+
+ s->dramcom[idx] =3D (uint32_t) val;
+}
+
+static uint64_t allwinner_h3_dramctl_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ const AwH3DramCtlState *s =3D AW_H3_DRAMC(opaque);
+ const uint32_t idx =3D REG_INDEX(offset);
+
+ if (idx >=3D AW_H3_DRAMCTL_REGS_NUM) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return 0;
+ }
+
+ trace_allwinner_h3_dramctl_read(offset, s->dramctl[idx], size);
+
+ return s->dramctl[idx];
+}
+
+static void allwinner_h3_dramctl_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AwH3DramCtlState *s =3D AW_H3_DRAMC(opaque);
+ const uint32_t idx =3D REG_INDEX(offset);
+
+ trace_allwinner_h3_dramctl_write(offset, val, size);
+
+ if (idx >=3D AW_H3_DRAMCTL_REGS_NUM) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return;
+ }
+
+ switch (offset) {
+ case REG_DRAMCTL_PIR: /* PHY Initialization Register */
+ s->dramctl[REG_INDEX(REG_DRAMCTL_PGSR)] |=3D REG_DRAMCTL_PGSR_INIT=
DONE;
+ s->dramctl[REG_INDEX(REG_DRAMCTL_STATR)] |=3D REG_DRAMCTL_STATR_AC=
TIVE;
+ break;
+ default:
+ break;
+ }
+
+ s->dramctl[idx] =3D (uint32_t) val;
+}
+
+static uint64_t allwinner_h3_dramphy_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ const AwH3DramCtlState *s =3D AW_H3_DRAMC(opaque);
+ const uint32_t idx =3D REG_INDEX(offset);
+
+ if (idx >=3D AW_H3_DRAMPHY_REGS_NUM) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return 0;
+ }
+
+ trace_allwinner_h3_dramphy_read(offset, s->dramphy[idx], size);
+
+ return s->dramphy[idx];
+}
+
+static void allwinner_h3_dramphy_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AwH3DramCtlState *s =3D AW_H3_DRAMC(opaque);
+ const uint32_t idx =3D REG_INDEX(offset);
+
+ trace_allwinner_h3_dramphy_write(offset, val, size);
+
+ if (idx >=3D AW_H3_DRAMPHY_REGS_NUM) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return;
+ }
+
+ s->dramphy[idx] =3D (uint32_t) val;
+}
+
+static const MemoryRegionOps allwinner_h3_dramcom_ops =3D {
+ .read =3D allwinner_h3_dramcom_read,
+ .write =3D allwinner_h3_dramcom_write,
+ .endianness =3D DEVICE_NATIVE_ENDIAN,
+ .valid =3D {
+ .min_access_size =3D 4,
+ .max_access_size =3D 4,
+ },
+ .impl.min_access_size =3D 4,
+};
+
+static const MemoryRegionOps allwinner_h3_dramctl_ops =3D {
+ .read =3D allwinner_h3_dramctl_read,
+ .write =3D allwinner_h3_dramctl_write,
+ .endianness =3D DEVICE_NATIVE_ENDIAN,
+ .valid =3D {
+ .min_access_size =3D 4,
+ .max_access_size =3D 4,
+ },
+ .impl.min_access_size =3D 4,
+};
+
+static const MemoryRegionOps allwinner_h3_dramphy_ops =3D {
+ .read =3D allwinner_h3_dramphy_read,
+ .write =3D allwinner_h3_dramphy_write,
+ .endianness =3D DEVICE_NATIVE_ENDIAN,
+ .valid =3D {
+ .min_access_size =3D 4,
+ .max_access_size =3D 4,
+ },
+ .impl.min_access_size =3D 4,
+};
+
+static void allwinner_h3_dramc_reset(DeviceState *dev)
+{
+ AwH3DramCtlState *s =3D AW_H3_DRAMC(dev);
+
+ /* Set default values for registers */
+ memset(&s->dramcom, 0, sizeof(s->dramcom));
+ memset(&s->dramctl, 0, sizeof(s->dramctl));
+ memset(&s->dramphy, 0, sizeof(s->dramphy));
+}
+
+static void allwinner_h3_dramc_realize(DeviceState *dev, Error **errp)
+{
+ AwH3DramCtlState *s =3D AW_H3_DRAMC(dev);
+
+ /* Only power of 2 RAM sizes from 256MiB up to 2048MiB are supported */
+ for (uint8_t i =3D 8; i < 13; i++) {
+ if (1 << i =3D=3D s->ram_size) {
+ break;
+ } else if (i =3D=3D 12) {
+ error_report("%s: ram-size %u MiB is not supported",
+ __func__, s->ram_size);
+ exit(1);
+ }
+ }
+
+ /* Setup row mirror mappings */
+ memory_region_init_ram(&s->row_mirror, OBJECT(s),
+ "allwinner-h3-dramc.row-mirror",
+ 4 * KiB, &error_abort);
+ memory_region_add_subregion_overlap(get_system_memory(), s->ram_addr,
+ &s->row_mirror, 10);
+
+ memory_region_init_alias(&s->row_mirror_alias, OBJECT(s),
+ "allwinner-h3-dramc.row-mirror-alias",
+ &s->row_mirror, 0, 4 * KiB);
+ memory_region_add_subregion_overlap(get_system_memory(),
+ s->ram_addr + 1 * MiB,
+ &s->row_mirror_alias, 10);
+ memory_region_set_enabled(&s->row_mirror_alias, false);
+}
+
+static void allwinner_h3_dramc_init(Object *obj)
+{
+ SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj);
+ AwH3DramCtlState *s =3D AW_H3_DRAMC(obj);
+
+ /* DRAMCOM registers */
+ memory_region_init_io(&s->dramcom_iomem, OBJECT(s),
+ &allwinner_h3_dramcom_ops, s,
+ TYPE_AW_H3_DRAMC, 4 * KiB);
+ sysbus_init_mmio(sbd, &s->dramcom_iomem);
+
+ /* DRAMCTL registers */
+ memory_region_init_io(&s->dramctl_iomem, OBJECT(s),
+ &allwinner_h3_dramctl_ops, s,
+ TYPE_AW_H3_DRAMC, 4 * KiB);
+ sysbus_init_mmio(sbd, &s->dramctl_iomem);
+
+ /* DRAMPHY registers */
+ memory_region_init_io(&s->dramphy_iomem, OBJECT(s),
+ &allwinner_h3_dramphy_ops, s,
+ TYPE_AW_H3_DRAMC, 4 * KiB);
+ sysbus_init_mmio(sbd, &s->dramphy_iomem);
+}
+
+static Property allwinner_h3_dramc_properties[] =3D {
+ DEFINE_PROP_UINT64("ram-addr", AwH3DramCtlState, ram_addr, 0x0),
+ DEFINE_PROP_UINT32("ram-size", AwH3DramCtlState, ram_size, 256 * MiB),
+ DEFINE_PROP_END_OF_LIST()
+};
+
+static const VMStateDescription allwinner_h3_dramc_vmstate =3D {
+ .name =3D "allwinner-h3-dramc",
+ .version_id =3D 1,
+ .minimum_version_id =3D 1,
+ .fields =3D (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(dramcom, AwH3DramCtlState, AW_H3_DRAMCOM_REGS=
_NUM),
+ VMSTATE_UINT32_ARRAY(dramctl, AwH3DramCtlState, AW_H3_DRAMCTL_REGS=
_NUM),
+ VMSTATE_UINT32_ARRAY(dramphy, AwH3DramCtlState, AW_H3_DRAMPHY_REGS=
_NUM),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void allwinner_h3_dramc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc =3D DEVICE_CLASS(klass);
+
+ dc->reset =3D allwinner_h3_dramc_reset;
+ dc->vmsd =3D &allwinner_h3_dramc_vmstate;
+ dc->realize =3D allwinner_h3_dramc_realize;
+ device_class_set_props(dc, allwinner_h3_dramc_properties);
+}
+
+static const TypeInfo allwinner_h3_dramc_info =3D {
+ .name =3D TYPE_AW_H3_DRAMC,
+ .parent =3D TYPE_SYS_BUS_DEVICE,
+ .instance_init =3D allwinner_h3_dramc_init,
+ .instance_size =3D sizeof(AwH3DramCtlState),
+ .class_init =3D allwinner_h3_dramc_class_init,
+};
+
+static void allwinner_h3_dramc_register(void)
+{
+ type_register_static(&allwinner_h3_dramc_info);
+}
+
+type_init(allwinner_h3_dramc_register)
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 4f38328d9c3..a5862b2bed1 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -5,6 +5,16 @@ allwinner_cpucfg_cpu_reset(uint8_t cpu_id, uint32_t reset_=
addr) "id %u, reset_ad
allwinner_cpucfg_read(uint64_t offset, uint64_t data, unsigned size) "offs=
et 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
allwinner_cpucfg_write(uint64_t offset, uint64_t data, unsigned size) "off=
set 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
=20
+# allwinner-h3-dramc.c
+allwinner_h3_dramc_rowmirror_disable(void) "Disable row mirror"
+allwinner_h3_dramc_rowmirror_enable(uint64_t addr) "Enable row mirror: add=
r 0x%" PRIx64
+allwinner_h3_dramcom_read(uint64_t offset, uint64_t data, unsigned size) "=
Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+allwinner_h3_dramcom_write(uint64_t offset, uint64_t data, unsigned size) =
"Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+allwinner_h3_dramctl_read(uint64_t offset, uint64_t data, unsigned size) "=
Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+allwinner_h3_dramctl_write(uint64_t offset, uint64_t data, unsigned size) =
"Write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+allwinner_h3_dramphy_read(uint64_t offset, uint64_t data, unsigned size) "=
Read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+allwinner_h3_dramphy_write(uint64_t offset, uint64_t data, unsigned size) =
"write: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
+
# allwinner-sid.c
allwinner_sid_read(uint64_t offset, uint64_t data, unsigned size) "offset =
0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
allwinner_sid_write(uint64_t offset, uint64_t data, unsigned size) "offset=
0x%" PRIx64 " data 0x%" PRIx64 " size %" PRIu32
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 23/36] hw/arm/allwinner: add RTC device support
Date: Thu, 12 Mar 2020 16:44:46 +0000
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From: Niek Linnenbank <nieklinnenbank@gmail.com>
Allwinner System-on-Chips usually contain a Real Time Clock (RTC)
for non-volatile system date and time keeping. This commit adds a generic
Allwinner RTC device that supports the RTC devices found in Allwinner SoC
family sun4i (A10), sun7i (A20) and sun6i and newer (A31, H2+, H3, etc).
The following RTC functionality and features are implemented:
* Year-Month-Day read/write
* Hour-Minute-Second read/write
* General Purpose storage
The following boards are extended with the RTC device:
* Cubieboard (hw/arm/cubieboard.c)
* Orange Pi PC (hw/arm/orangepi.c)
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Message-id: 20200311221854.30370-13-nieklinnenbank@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/rtc/Makefile.objs | 1 +
include/hw/arm/allwinner-a10.h | 2 +
include/hw/arm/allwinner-h3.h | 3 +
include/hw/rtc/allwinner-rtc.h | 134 +++++++++++
hw/arm/allwinner-a10.c | 8 +
hw/arm/allwinner-h3.c | 9 +-
hw/rtc/allwinner-rtc.c | 411 +++++++++++++++++++++++++++++++++
hw/rtc/trace-events | 4 +
8 files changed, 571 insertions(+), 1 deletion(-)
create mode 100644 include/hw/rtc/allwinner-rtc.h
create mode 100644 hw/rtc/allwinner-rtc.c
diff --git a/hw/rtc/Makefile.objs b/hw/rtc/Makefile.objs
index aa208d0d10a..e4c1b8617c8 100644
--- a/hw/rtc/Makefile.objs
+++ b/hw/rtc/Makefile.objs
@@ -12,3 +12,4 @@ obj-$(CONFIG_MC146818RTC) +=3D mc146818rtc.o
common-obj-$(CONFIG_SUN4V_RTC) +=3D sun4v-rtc.o
common-obj-$(CONFIG_ASPEED_SOC) +=3D aspeed_rtc.o
common-obj-$(CONFIG_GOLDFISH_RTC) +=3D goldfish_rtc.o
+common-obj-$(CONFIG_ALLWINNER_H3) +=3D allwinner-rtc.o
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index ae33a84b18b..77c82a99828 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -11,6 +11,7 @@
#include "hw/ide/ahci.h"
#include "hw/usb/hcd-ohci.h"
#include "hw/usb/hcd-ehci.h"
+#include "hw/rtc/allwinner-rtc.h"
=20
#include "target/arm/cpu.h"
=20
@@ -33,6 +34,7 @@ typedef struct AwA10State {
AwEmacState emac;
AllwinnerAHCIState sata;
AwSdHostState mmc0;
+ AwRtcState rtc;
MemoryRegion sram_a;
EHCISysBusState ehci[AW_A10_NUM_USB];
OHCISysBusState ohci[AW_A10_NUM_USB];
diff --git a/include/hw/arm/allwinner-h3.h b/include/hw/arm/allwinner-h3.h
index 065d020c738..82e4e592166 100644
--- a/include/hw/arm/allwinner-h3.h
+++ b/include/hw/arm/allwinner-h3.h
@@ -46,6 +46,7 @@
#include "hw/misc/allwinner-sid.h"
#include "hw/sd/allwinner-sdhost.h"
#include "hw/net/allwinner-sun8i-emac.h"
+#include "hw/rtc/allwinner-rtc.h"
#include "target/arm/cpu.h"
#include "sysemu/block-backend.h"
=20
@@ -88,6 +89,7 @@ enum {
AW_H3_GIC_CPU,
AW_H3_GIC_HYP,
AW_H3_GIC_VCPU,
+ AW_H3_RTC,
AW_H3_CPUCFG,
AW_H3_SDRAM
};
@@ -129,6 +131,7 @@ typedef struct AwH3State {
AwSidState sid;
AwSdHostState mmc0;
AwSun8iEmacState emac;
+ AwRtcState rtc;
GICState gic;
MemoryRegion sram_a1;
MemoryRegion sram_a2;
diff --git a/include/hw/rtc/allwinner-rtc.h b/include/hw/rtc/allwinner-rtc.h
new file mode 100644
index 00000000000..7893f74795c
--- /dev/null
+++ b/include/hw/rtc/allwinner-rtc.h
@@ -0,0 +1,134 @@
+/*
+ * Allwinner Real Time Clock emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_MISC_ALLWINNER_RTC_H
+#define HW_MISC_ALLWINNER_RTC_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+
+/**
+ * Constants
+ * @{
+ */
+
+/** Highest register address used by RTC device */
+#define AW_RTC_REGS_MAXADDR (0x200)
+
+/** Total number of known registers */
+#define AW_RTC_REGS_NUM (AW_RTC_REGS_MAXADDR / sizeof(uint32_t))
+
+/** @} */
+
+/**
+ * Object model types
+ * @{
+ */
+
+/** Generic Allwinner RTC device (abstract) */
+#define TYPE_AW_RTC "allwinner-rtc"
+
+/** Allwinner RTC sun4i family (A10, A12) */
+#define TYPE_AW_RTC_SUN4I TYPE_AW_RTC "-sun4i"
+
+/** Allwinner RTC sun6i family and newer (A31, H2+, H3, etc) */
+#define TYPE_AW_RTC_SUN6I TYPE_AW_RTC "-sun6i"
+
+/** Allwinner RTC sun7i family (A20) */
+#define TYPE_AW_RTC_SUN7I TYPE_AW_RTC "-sun7i"
+
+/** @} */
+
+/**
+ * Object model macros
+ * @{
+ */
+
+#define AW_RTC(obj) \
+ OBJECT_CHECK(AwRtcState, (obj), TYPE_AW_RTC)
+#define AW_RTC_CLASS(klass) \
+ OBJECT_CLASS_CHECK(AwRtcClass, (klass), TYPE_AW_RTC)
+#define AW_RTC_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(AwRtcClass, (obj), TYPE_AW_RTC)
+
+/** @} */
+
+/**
+ * Allwinner RTC per-object instance state.
+ */
+typedef struct AwRtcState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+
+ /**
+ * Actual year represented by the device when year counter is zero
+ *
+ * Can be overridden by the user using the corresponding 'base-year'
+ * property. The base year used by the target OS driver can vary, for
+ * example the Linux driver for sun6i uses 1970 while NetBSD uses 2000.
+ */
+ int base_year;
+
+ /** Maps I/O registers in physical memory */
+ MemoryRegion iomem;
+
+ /** Array of hardware registers */
+ uint32_t regs[AW_RTC_REGS_NUM];
+
+} AwRtcState;
+
+/**
+ * Allwinner RTC class-level struct.
+ *
+ * This struct is filled by each sunxi device specific code
+ * such that the generic code can use this struct to support
+ * all devices.
+ */
+typedef struct AwRtcClass {
+ /*< private >*/
+ SysBusDeviceClass parent_class;
+ /*< public >*/
+
+ /** Defines device specific register map */
+ const uint8_t *regmap;
+
+ /** Size of the regmap in bytes */
+ size_t regmap_size;
+
+ /**
+ * Read device specific register
+ *
+ * @offset: register offset to read
+ * @return true if register read successful, false otherwise
+ */
+ bool (*read)(AwRtcState *s, uint32_t offset);
+
+ /**
+ * Write device specific register
+ *
+ * @offset: register offset to write
+ * @data: value to set in register
+ * @return true if register write successful, false otherwise
+ */
+ bool (*write)(AwRtcState *s, uint32_t offset, uint32_t data);
+
+} AwRtcClass;
+
+#endif /* HW_MISC_ALLWINNER_RTC_H */
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index dc62c764167..62a67a3e1a6 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -35,6 +35,7 @@
#define AW_A10_EHCI_BASE 0x01c14000
#define AW_A10_OHCI_BASE 0x01c14400
#define AW_A10_SATA_BASE 0x01c18000
+#define AW_A10_RTC_BASE 0x01c20d00
=20
static void aw_a10_init(Object *obj)
{
@@ -68,6 +69,9 @@ static void aw_a10_init(Object *obj)
=20
sysbus_init_child_obj(obj, "mmc0", &s->mmc0, sizeof(s->mmc0),
TYPE_AW_SDHOST_SUN4I);
+
+ sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
+ TYPE_AW_RTC_SUN4I);
}
=20
static void aw_a10_realize(DeviceState *dev, Error **errp)
@@ -175,6 +179,10 @@ static void aw_a10_realize(DeviceState *dev, Error **e=
rrp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0, qdev_get_gpio_in(dev, =
32));
object_property_add_alias(OBJECT(s), "sd-bus", OBJECT(&s->mmc0),
"sd-bus", &error_abort);
+
+ /* RTC */
+ qdev_init_nofail(DEVICE(&s->rtc));
+ sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->rtc), 0, AW_A10_RTC_BASE, 1=
0);
}
=20
static void aw_a10_class_init(ObjectClass *oc, void *data)
diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c
index c0a2ecfee81..9e4ce36093b 100644
--- a/hw/arm/allwinner-h3.c
+++ b/hw/arm/allwinner-h3.c
@@ -63,6 +63,7 @@ const hwaddr allwinner_h3_memmap[] =3D {
[AW_H3_GIC_CPU] =3D 0x01c82000,
[AW_H3_GIC_HYP] =3D 0x01c84000,
[AW_H3_GIC_VCPU] =3D 0x01c86000,
+ [AW_H3_RTC] =3D 0x01f00000,
[AW_H3_CPUCFG] =3D 0x01f01c00,
[AW_H3_SDRAM] =3D 0x40000000
};
@@ -118,7 +119,6 @@ struct AwH3Unimplemented {
{ "csi", 0x01cb0000, 320 * KiB },
{ "tve", 0x01e00000, 64 * KiB },
{ "hdmi", 0x01ee0000, 128 * KiB },
- { "rtc", 0x01f00000, 1 * KiB },
{ "r_timer", 0x01f00800, 1 * KiB },
{ "r_intc", 0x01f00c00, 1 * KiB },
{ "r_wdog", 0x01f01000, 1 * KiB },
@@ -235,6 +235,9 @@ static void allwinner_h3_init(Object *obj)
"ram-addr", &error_abort);
object_property_add_alias(obj, "ram-size", OBJECT(&s->dramc),
"ram-size", &error_abort);
+
+ sysbus_init_child_obj(obj, "rtc", &s->rtc, sizeof(s->rtc),
+ TYPE_AW_RTC_SUN6I);
}
=20
static void allwinner_h3_realize(DeviceState *dev, Error **errp)
@@ -425,6 +428,10 @@ static void allwinner_h3_realize(DeviceState *dev, Err=
or **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]=
);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]=
);
=20
+ /* RTC */
+ qdev_init_nofail(DEVICE(&s->rtc));
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_RTC]);
+
/* Unimplemented devices */
for (i =3D 0; i < ARRAY_SIZE(unimplemented); i++) {
create_unimplemented_device(unimplemented[i].device_name,
diff --git a/hw/rtc/allwinner-rtc.c b/hw/rtc/allwinner-rtc.c
new file mode 100644
index 00000000000..5606a51d5c5
--- /dev/null
+++ b/hw/rtc/allwinner-rtc.c
@@ -0,0 +1,411 @@
+/*
+ * Allwinner Real Time Clock emulation
+ *
+ * Copyright (C) 2019 Niek Linnenbank <nieklinnenbank@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "qemu-common.h"
+#include "hw/qdev-properties.h"
+#include "hw/rtc/allwinner-rtc.h"
+#include "trace.h"
+
+/* RTC registers */
+enum {
+ REG_LOSC =3D 1, /* Low Oscillator Control */
+ REG_YYMMDD, /* RTC Year-Month-Day */
+ REG_HHMMSS, /* RTC Hour-Minute-Second */
+ REG_ALARM1_WKHHMMSS, /* Alarm1 Week Hour-Minute-Second */
+ REG_ALARM1_EN, /* Alarm1 Enable */
+ REG_ALARM1_IRQ_EN, /* Alarm1 IRQ Enable */
+ REG_ALARM1_IRQ_STA, /* Alarm1 IRQ Status */
+ REG_GP0, /* General Purpose Register 0 */
+ REG_GP1, /* General Purpose Register 1 */
+ REG_GP2, /* General Purpose Register 2 */
+ REG_GP3, /* General Purpose Register 3 */
+
+ /* sun4i registers */
+ REG_ALARM1_DDHHMMSS, /* Alarm1 Day Hour-Minute-Second */
+ REG_CPUCFG, /* CPU Configuration Register */
+
+ /* sun6i registers */
+ REG_LOSC_AUTOSTA, /* LOSC Auto Switch Status */
+ REG_INT_OSC_PRE, /* Internal OSC Clock Prescaler */
+ REG_ALARM0_COUNTER, /* Alarm0 Counter */
+ REG_ALARM0_CUR_VLU, /* Alarm0 Counter Current Value */
+ REG_ALARM0_ENABLE, /* Alarm0 Enable */
+ REG_ALARM0_IRQ_EN, /* Alarm0 IRQ Enable */
+ REG_ALARM0_IRQ_STA, /* Alarm0 IRQ Status */
+ REG_ALARM_CONFIG, /* Alarm Config */
+ REG_LOSC_OUT_GATING, /* LOSC Output Gating Register */
+ REG_GP4, /* General Purpose Register 4 */
+ REG_GP5, /* General Purpose Register 5 */
+ REG_GP6, /* General Purpose Register 6 */
+ REG_GP7, /* General Purpose Register 7 */
+ REG_RTC_DBG, /* RTC Debug Register */
+ REG_GPL_HOLD_OUT, /* GPL Hold Output Register */
+ REG_VDD_RTC, /* VDD RTC Regulate Register */
+ REG_IC_CHARA, /* IC Characteristics Register */
+};
+
+/* RTC register flags */
+enum {
+ REG_LOSC_YMD =3D (1 << 7),
+ REG_LOSC_HMS =3D (1 << 8),
+};
+
+/* RTC sun4i register map (offset to name) */
+const uint8_t allwinner_rtc_sun4i_regmap[] =3D {
+ [0x0000] =3D REG_LOSC,
+ [0x0004] =3D REG_YYMMDD,
+ [0x0008] =3D REG_HHMMSS,
+ [0x000C] =3D REG_ALARM1_DDHHMMSS,
+ [0x0010] =3D REG_ALARM1_WKHHMMSS,
+ [0x0014] =3D REG_ALARM1_EN,
+ [0x0018] =3D REG_ALARM1_IRQ_EN,
+ [0x001C] =3D REG_ALARM1_IRQ_STA,
+ [0x0020] =3D REG_GP0,
+ [0x0024] =3D REG_GP1,
+ [0x0028] =3D REG_GP2,
+ [0x002C] =3D REG_GP3,
+ [0x003C] =3D REG_CPUCFG,
+};
+
+/* RTC sun6i register map (offset to name) */
+const uint8_t allwinner_rtc_sun6i_regmap[] =3D {
+ [0x0000] =3D REG_LOSC,
+ [0x0004] =3D REG_LOSC_AUTOSTA,
+ [0x0008] =3D REG_INT_OSC_PRE,
+ [0x0010] =3D REG_YYMMDD,
+ [0x0014] =3D REG_HHMMSS,
+ [0x0020] =3D REG_ALARM0_COUNTER,
+ [0x0024] =3D REG_ALARM0_CUR_VLU,
+ [0x0028] =3D REG_ALARM0_ENABLE,
+ [0x002C] =3D REG_ALARM0_IRQ_EN,
+ [0x0030] =3D REG_ALARM0_IRQ_STA,
+ [0x0040] =3D REG_ALARM1_WKHHMMSS,
+ [0x0044] =3D REG_ALARM1_EN,
+ [0x0048] =3D REG_ALARM1_IRQ_EN,
+ [0x004C] =3D REG_ALARM1_IRQ_STA,
+ [0x0050] =3D REG_ALARM_CONFIG,
+ [0x0060] =3D REG_LOSC_OUT_GATING,
+ [0x0100] =3D REG_GP0,
+ [0x0104] =3D REG_GP1,
+ [0x0108] =3D REG_GP2,
+ [0x010C] =3D REG_GP3,
+ [0x0110] =3D REG_GP4,
+ [0x0114] =3D REG_GP5,
+ [0x0118] =3D REG_GP6,
+ [0x011C] =3D REG_GP7,
+ [0x0170] =3D REG_RTC_DBG,
+ [0x0180] =3D REG_GPL_HOLD_OUT,
+ [0x0190] =3D REG_VDD_RTC,
+ [0x01F0] =3D REG_IC_CHARA,
+};
+
+static bool allwinner_rtc_sun4i_read(AwRtcState *s, uint32_t offset)
+{
+ /* no sun4i specific registers currently implemented */
+ return false;
+}
+
+static bool allwinner_rtc_sun4i_write(AwRtcState *s, uint32_t offset,
+ uint32_t data)
+{
+ /* no sun4i specific registers currently implemented */
+ return false;
+}
+
+static bool allwinner_rtc_sun6i_read(AwRtcState *s, uint32_t offset)
+{
+ const AwRtcClass *c =3D AW_RTC_GET_CLASS(s);
+
+ switch (c->regmap[offset]) {
+ case REG_GP4: /* General Purpose Register 4 */
+ case REG_GP5: /* General Purpose Register 5 */
+ case REG_GP6: /* General Purpose Register 6 */
+ case REG_GP7: /* General Purpose Register 7 */
+ return true;
+ default:
+ break;
+ }
+ return false;
+}
+
+static bool allwinner_rtc_sun6i_write(AwRtcState *s, uint32_t offset,
+ uint32_t data)
+{
+ const AwRtcClass *c =3D AW_RTC_GET_CLASS(s);
+
+ switch (c->regmap[offset]) {
+ case REG_GP4: /* General Purpose Register 4 */
+ case REG_GP5: /* General Purpose Register 5 */
+ case REG_GP6: /* General Purpose Register 6 */
+ case REG_GP7: /* General Purpose Register 7 */
+ return true;
+ default:
+ break;
+ }
+ return false;
+}
+
+static uint64_t allwinner_rtc_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ AwRtcState *s =3D AW_RTC(opaque);
+ const AwRtcClass *c =3D AW_RTC_GET_CLASS(s);
+ uint64_t val =3D 0;
+
+ if (offset >=3D c->regmap_size) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return 0;
+ }
+
+ if (!c->regmap[offset]) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return 0;
+ }
+
+ switch (c->regmap[offset]) {
+ case REG_LOSC: /* Low Oscillator Control */
+ val =3D s->regs[REG_LOSC];
+ s->regs[REG_LOSC] &=3D ~(REG_LOSC_YMD | REG_LOSC_HMS);
+ break;
+ case REG_YYMMDD: /* RTC Year-Month-Day */
+ case REG_HHMMSS: /* RTC Hour-Minute-Second */
+ case REG_GP0: /* General Purpose Register 0 */
+ case REG_GP1: /* General Purpose Register 1 */
+ case REG_GP2: /* General Purpose Register 2 */
+ case REG_GP3: /* General Purpose Register 3 */
+ val =3D s->regs[c->regmap[offset]];
+ break;
+ default:
+ if (!c->read(s, offset)) {
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",
+ __func__, (uint32_t)offset);
+ }
+ val =3D s->regs[c->regmap[offset]];
+ break;
+ }
+
+ trace_allwinner_rtc_read(offset, val);
+ return val;
+}
+
+static void allwinner_rtc_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AwRtcState *s =3D AW_RTC(opaque);
+ const AwRtcClass *c =3D AW_RTC_GET_CLASS(s);
+
+ if (offset >=3D c->regmap_size) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return;
+ }
+
+ if (!c->regmap[offset]) {
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: invalid register 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return;
+ }
+
+ trace_allwinner_rtc_write(offset, val);
+
+ switch (c->regmap[offset]) {
+ case REG_YYMMDD: /* RTC Year-Month-Day */
+ s->regs[REG_YYMMDD] =3D val;
+ s->regs[REG_LOSC] |=3D REG_LOSC_YMD;
+ break;
+ case REG_HHMMSS: /* RTC Hour-Minute-Second */
+ s->regs[REG_HHMMSS] =3D val;
+ s->regs[REG_LOSC] |=3D REG_LOSC_HMS;
+ break;
+ case REG_GP0: /* General Purpose Register 0 */
+ case REG_GP1: /* General Purpose Register 1 */
+ case REG_GP2: /* General Purpose Register 2 */
+ case REG_GP3: /* General Purpose Register 3 */
+ s->regs[c->regmap[offset]] =3D val;
+ break;
+ default:
+ if (!c->write(s, offset, val)) {
+ qemu_log_mask(LOG_UNIMP, "%s: unimplemented register 0x%04x\n",
+ __func__, (uint32_t)offset);
+ }
+ break;
+ }
+}
+
+static const MemoryRegionOps allwinner_rtc_ops =3D {
+ .read =3D allwinner_rtc_read,
+ .write =3D allwinner_rtc_write,
+ .endianness =3D DEVICE_NATIVE_ENDIAN,
+ .valid =3D {
+ .min_access_size =3D 4,
+ .max_access_size =3D 4,
+ },
+ .impl.min_access_size =3D 4,
+};
+
+static void allwinner_rtc_reset(DeviceState *dev)
+{
+ AwRtcState *s =3D AW_RTC(dev);
+ struct tm now;
+
+ /* Clear registers */
+ memset(s->regs, 0, sizeof(s->regs));
+
+ /* Get current datetime */
+ qemu_get_timedate(&now, 0);
+
+ /* Set RTC with current datetime */
+ if (s->base_year > 1900) {
+ s->regs[REG_YYMMDD] =3D ((now.tm_year + 1900 - s->base_year) << 1=
6) |
+ ((now.tm_mon + 1) << 8) |
+ now.tm_mday;
+ s->regs[REG_HHMMSS] =3D (((now.tm_wday + 6) % 7) << 29) |
+ (now.tm_hour << 16) |
+ (now.tm_min << 8) |
+ now.tm_sec;
+ }
+}
+
+static void allwinner_rtc_init(Object *obj)
+{
+ SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj);
+ AwRtcState *s =3D AW_RTC(obj);
+
+ /* Memory mapping */
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_rtc_ops, s,
+ TYPE_AW_RTC, 1 * KiB);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static const VMStateDescription allwinner_rtc_vmstate =3D {
+ .name =3D "allwinner-rtc",
+ .version_id =3D 1,
+ .minimum_version_id =3D 1,
+ .fields =3D (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, AwRtcState, AW_RTC_REGS_NUM),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property allwinner_rtc_properties[] =3D {
+ DEFINE_PROP_INT32("base-year", AwRtcState, base_year, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void allwinner_rtc_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc =3D DEVICE_CLASS(klass);
+
+ dc->reset =3D allwinner_rtc_reset;
+ dc->vmsd =3D &allwinner_rtc_vmstate;
+ device_class_set_props(dc, allwinner_rtc_properties);
+}
+
+static void allwinner_rtc_sun4i_init(Object *obj)
+{
+ AwRtcState *s =3D AW_RTC(obj);
+ s->base_year =3D 2010;
+}
+
+static void allwinner_rtc_sun4i_class_init(ObjectClass *klass, void *data)
+{
+ AwRtcClass *arc =3D AW_RTC_CLASS(klass);
+
+ arc->regmap =3D allwinner_rtc_sun4i_regmap;
+ arc->regmap_size =3D sizeof(allwinner_rtc_sun4i_regmap);
+ arc->read =3D allwinner_rtc_sun4i_read;
+ arc->write =3D allwinner_rtc_sun4i_write;
+}
+
+static void allwinner_rtc_sun6i_init(Object *obj)
+{
+ AwRtcState *s =3D AW_RTC(obj);
+ s->base_year =3D 1970;
+}
+
+static void allwinner_rtc_sun6i_class_init(ObjectClass *klass, void *data)
+{
+ AwRtcClass *arc =3D AW_RTC_CLASS(klass);
+
+ arc->regmap =3D allwinner_rtc_sun6i_regmap;
+ arc->regmap_size =3D sizeof(allwinner_rtc_sun6i_regmap);
+ arc->read =3D allwinner_rtc_sun6i_read;
+ arc->write =3D allwinner_rtc_sun6i_write;
+}
+
+static void allwinner_rtc_sun7i_init(Object *obj)
+{
+ AwRtcState *s =3D AW_RTC(obj);
+ s->base_year =3D 1970;
+}
+
+static void allwinner_rtc_sun7i_class_init(ObjectClass *klass, void *data)
+{
+ AwRtcClass *arc =3D AW_RTC_CLASS(klass);
+ allwinner_rtc_sun4i_class_init(klass, arc);
+}
+
+static const TypeInfo allwinner_rtc_info =3D {
+ .name =3D TYPE_AW_RTC,
+ .parent =3D TYPE_SYS_BUS_DEVICE,
+ .instance_init =3D allwinner_rtc_init,
+ .instance_size =3D sizeof(AwRtcState),
+ .class_init =3D allwinner_rtc_class_init,
+ .class_size =3D sizeof(AwRtcClass),
+ .abstract =3D true,
+};
+
+static const TypeInfo allwinner_rtc_sun4i_info =3D {
+ .name =3D TYPE_AW_RTC_SUN4I,
+ .parent =3D TYPE_AW_RTC,
+ .class_init =3D allwinner_rtc_sun4i_class_init,
+ .instance_init =3D allwinner_rtc_sun4i_init,
+};
+
+static const TypeInfo allwinner_rtc_sun6i_info =3D {
+ .name =3D TYPE_AW_RTC_SUN6I,
+ .parent =3D TYPE_AW_RTC,
+ .class_init =3D allwinner_rtc_sun6i_class_init,
+ .instance_init =3D allwinner_rtc_sun6i_init,
+};
+
+static const TypeInfo allwinner_rtc_sun7i_info =3D {
+ .name =3D TYPE_AW_RTC_SUN7I,
+ .parent =3D TYPE_AW_RTC,
+ .class_init =3D allwinner_rtc_sun7i_class_init,
+ .instance_init =3D allwinner_rtc_sun7i_init,
+};
+
+static void allwinner_rtc_register(void)
+{
+ type_register_static(&allwinner_rtc_info);
+ type_register_static(&allwinner_rtc_sun4i_info);
+ type_register_static(&allwinner_rtc_sun6i_info);
+ type_register_static(&allwinner_rtc_sun7i_info);
+}
+
+type_init(allwinner_rtc_register)
diff --git a/hw/rtc/trace-events b/hw/rtc/trace-events
index c9894e17478..1bc7147d0e0 100644
--- a/hw/rtc/trace-events
+++ b/hw/rtc/trace-events
@@ -1,5 +1,9 @@
# See docs/devel/tracing.txt for syntax documentation.
=20
+# allwinner-rtc.c
+allwinner_rtc_read(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " valu=
e 0x%" PRIx64
+allwinner_rtc_write(uint64_t addr, uint64_t value) "addr 0x%" PRIx64 " val=
ue 0x%" PRIx64
+
# sun4v-rtc.c
sun4v_rtc_read(uint64_t addr, uint64_t value) "read: addr 0x%" PRIx64 " va=
lue 0x%" PRIx64
sun4v_rtc_write(uint64_t addr, uint64_t value) "write: addr 0x%" PRIx64 " =
value 0x%" PRIx64
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 24/36] tests/boot_linux_console: Add a quick test for the
OrangePi PC board
Date: Thu, 12 Mar 2020 16:44:47 +0000
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From: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
This test boots a Linux kernel on a OrangePi PC board and verify
the serial output is working.
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
If ARM is a target being built, "make check-acceptance" will
automatically include this test by the use of the "arch:arm" tags.
Alternatively, this test can be run using:
$ make check-venv
$ ./tests/venv/bin/avocado --show=3Dconsole,app run -t machine:orangepi-p=
c tests/acceptance/boot_linux_console.py
JOB ID : 2e4d15eceb13c33672af406f08171e6e9de1414a
JOB LOG : ~/job-results/job-2019-12-17T05.46-2e4d15e/job.log
(1/1) tests/acceptance/boot_linux_console.py:BootLinuxConsole.test_arm_or=
angepi:
console: Uncompressing Linux... done, booting the kernel.
console: Booting Linux on physical CPU 0x0
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1=
20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D50c5387d
console: CPU: div instructions available: patching division code
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instructi=
on cache
console: OF: fdt: Machine model: Xunlong Orange Pi PC
console: Memory policy: Data cache writealloc
console: OF: reserved mem: failed to allocate memory for node 'cma@4a0000=
00'
console: cma: Failed to reserve 128 MiB
console: psci: probing for conduit method from DT.
console: psci: PSCIv0.2 detected in firmware.
console: psci: Using standard PSCI v0.2 function IDs
console: psci: Trusted OS migration not required
console: random: get_random_bytes called from start_kernel+0x8d/0x3c2 wit=
h crng_init=3D0
console: percpu: Embedded 18 pages/cpu @(ptrval) s41228 r8192 d24308 u737=
28
console: Built 1 zonelists, mobility grouping on. Total pages: 32480
console: Kernel command line: printk.time=3D0 console=3DttyS0,115200
PASS (8.59 s)
JOB TIME : 8.81 s
Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Message-id: 20200311221854.30370-14-nieklinnenbank@gmail.com
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/acceptance/boot_linux_console.py | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot=
_linux_console.py
index 34d37eba3b0..6f5af582f3b 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -507,6 +507,31 @@ class BootLinuxConsole(Test):
exec_command_and_wait_for_pattern(self, 'reboot',
'reboot: Restarting system=
')
=20
+ def test_arm_orangepi(self):
+ """
+ :avocado: tags=3Darch:arm
+ :avocado: tags=3Dmachine:orangepi-pc
+ """
+ deb_url =3D ('https://apt.armbian.com/pool/main/l/'
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.de=
b')
+ deb_hash =3D '1334c29c44d984ffa05ed10de8c3361f33d78315'
+ deb_path =3D self.fetch_asset(deb_url, asset_hash=3Ddeb_hash)
+ kernel_path =3D self.extract_from_deb(deb_path,
+ '/boot/vmlinuz-4.20.7-sunxi')
+ dtb_path =3D '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.=
dtb'
+ dtb_path =3D self.extract_from_deb(deb_path, dtb_path)
+
+ self.vm.set_console()
+ kernel_command_line =3D (self.KERNEL_COMMON_COMMAND_LINE +
+ 'console=3DttyS0,115200n8 '
+ 'earlycon=3Duart,mmio32,0x1c28000')
+ self.vm.add_args('-kernel', kernel_path,
+ '-dtb', dtb_path,
+ '-append', kernel_command_line)
+ self.vm.launch()
+ console_pattern =3D 'Kernel command line: %s' % kernel_command_line
+ self.wait_for_console_pattern(console_pattern)
+
def test_s390x_s390_ccw_virtio(self):
"""
:avocado: tags=3Darch:s390x
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 25/36] tests/boot_linux_console: Add initrd test for the Orange
Pi PC board
Date: Thu, 12 Mar 2020 16:44:48 +0000
Message-Id: <20200312164459.25924-26-peter.maydell@linaro.org>
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From: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
This test boots a Linux kernel on a OrangePi PC board and verify
the serial output is working.
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
The cpio image used comes from the linux-build-test project:
https://github.com/groeck/linux-build-test
If ARM is a target being built, "make check-acceptance" will
automatically include this test by the use of the "arch:arm" tags.
Alternatively, this test can be run using:
$ avocado --show=3Dconsole run -t machine:orangepi-pc tests/acceptance/bo=
ot_linux_console.py
console: Uncompressing Linux... done, booting the kernel.
console: Booting Linux on physical CPU 0x0
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1=
20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D50c5387d
console: CPU: div instructions available: patching division code
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instructi=
on cache
console: OF: fdt: Machine model: Xunlong Orange Pi PC
[...]
console: Trying to unpack rootfs image as initramfs...
console: Freeing initrd memory: 3256K
console: Freeing unused kernel memory: 1024K
console: Run /init as init process
console: mount: mounting devtmpfs on /dev failed: Device or resource busy
console: Starting logging: OK
console: Initializing random number generator... random: dd: uninitialize=
d urandom read (512 bytes read)
console: done.
console: Starting network: OK
console: Found console ttyS0
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1=
20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
console: Boot successful.
console: cat /proc/cpuinfo
console: / # cat /proc/cpuinfo
console: processor : 0
console: model name : ARMv7 Processor rev 5 (v7l)
console: BogoMIPS : 125.00
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfp=
v4 idiva idivt vfpd32 lpae evtstrm
console: CPU implementer : 0x41
console: CPU architecture: 7
console: CPU variant : 0x0
console: CPU part : 0xc07
console: CPU revision : 5
[...]
console: processor : 3
console: model name : ARMv7 Processor rev 5 (v7l)
console: BogoMIPS : 125.00
console: Features : half thumb fastmult vfp edsp neon vfpv3 tls vfp=
v4 idiva idivt vfpd32 lpae evtstrm
console: CPU implementer : 0x41
console: CPU architecture: 7
console: CPU variant : 0x0
console: CPU part : 0xc07
console: CPU revision : 5
console: Hardware : Allwinner sun8i Family
console: Revision : 0000
console: Serial : 0000000000000000
console: cat /proc/iomem
console: / # cat /proc/iomem
console: 01000000-010fffff : clock@1000000
console: 01c00000-01c00fff : system-control@1c00000
console: 01c02000-01c02fff : dma-controller@1c02000
[...]
console: reboot
console: / # reboot
console: / # Found console ttyS0
console: Stopping network: OK
console: hrtimer: interrupt took 21852064 ns
console: Saving random seed... random: dd: uninitialized urandom read (51=
2 bytes read)
console: done.
console: Stopping logging: OK
console: umount: devtmpfs busy - remounted read-only
console: umount: can't unmount /: Invalid argument
console: The system is going down NOW!
console: Sent SIGTERM to all processes
console: Sent SIGKILL to all processes
console: Requesting system reboot
console: reboot: Restarting system
PASS (48.32 s)
JOB TIME : 49.16 s
Signed-off-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Message-id: 20200311221854.30370-15-nieklinnenbank@gmail.com
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/acceptance/boot_linux_console.py | 40 ++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot=
_linux_console.py
index 6f5af582f3b..dabc8ef2afb 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -532,6 +532,46 @@ class BootLinuxConsole(Test):
console_pattern =3D 'Kernel command line: %s' % kernel_command_line
self.wait_for_console_pattern(console_pattern)
=20
+ def test_arm_orangepi_initrd(self):
+ """
+ :avocado: tags=3Darch:arm
+ :avocado: tags=3Dmachine:orangepi-pc
+ """
+ deb_url =3D ('https://apt.armbian.com/pool/main/l/'
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.de=
b')
+ deb_hash =3D '1334c29c44d984ffa05ed10de8c3361f33d78315'
+ deb_path =3D self.fetch_asset(deb_url, asset_hash=3Ddeb_hash)
+ kernel_path =3D self.extract_from_deb(deb_path,
+ '/boot/vmlinuz-4.20.7-sunxi')
+ dtb_path =3D '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.=
dtb'
+ dtb_path =3D self.extract_from_deb(deb_path, dtb_path)
+ initrd_url =3D ('https://github.com/groeck/linux-build-test/raw/'
+ '2eb0a73b5d5a28df3170c546ddaaa9757e1e0848/rootfs/'
+ 'arm/rootfs-armv7a.cpio.gz')
+ initrd_hash =3D '604b2e45cdf35045846b8bbfbf2129b1891bdc9c'
+ initrd_path_gz =3D self.fetch_asset(initrd_url, asset_hash=3Dinitr=
d_hash)
+ initrd_path =3D os.path.join(self.workdir, 'rootfs.cpio')
+ archive.gzip_uncompress(initrd_path_gz, initrd_path)
+
+ self.vm.set_console()
+ kernel_command_line =3D (self.KERNEL_COMMON_COMMAND_LINE +
+ 'console=3DttyS0,115200 '
+ 'panic=3D-1 noreboot')
+ self.vm.add_args('-kernel', kernel_path,
+ '-dtb', dtb_path,
+ '-initrd', initrd_path,
+ '-append', kernel_command_line,
+ '-no-reboot')
+ self.vm.launch()
+ self.wait_for_console_pattern('Boot successful.')
+
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
+ 'Allwinner sun8i Family')
+ exec_command_and_wait_for_pattern(self, 'cat /proc/iomem',
+ 'system-control@1c00000')
+ exec_command_and_wait_for_pattern(self, 'reboot',
+ 'reboot: Restarting system=
')
+
def test_s390x_s390_ccw_virtio(self):
"""
:avocado: tags=3Darch:s390x
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 26/36] tests/boot_linux_console: Add a SD card test for the
OrangePi PC board
Date: Thu, 12 Mar 2020 16:44:49 +0000
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From: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
The SD image is from the kernelci.org project:
https://kernelci.org/faq/#the-code
If ARM is a target being built, "make check-acceptance" will
automatically include this test by the use of the "arch:arm" tags.
Alternatively, this test can be run using:
$ avocado --show=3Dconsole run -t machine:orangepi-pc tests/acceptance/bo=
ot_linux_console.py
console: Uncompressing Linux... done, booting the kernel.
console: Booting Linux on physical CPU 0x0
console: Linux version 4.20.7-sunxi (root@armbian.com) (gcc version 7.2.1=
20171011 (Linaro GCC 7.2-2017.11)) #5.75 SMP Fri Feb 8 09:02:10 CET 2019
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D50c5387d
[...]
console: sunxi-wdt 1c20ca0.watchdog: Watchdog enabled (timeout=3D16 sec, =
nowayout=3D0)
console: sunxi-mmc 1c0f000.mmc: Linked as a consumer to regulator.2
console: sunxi-mmc 1c0f000.mmc: Got CD GPIO
console: ledtrig-cpu: registered to indicate activity on CPUs
console: hidraw: raw HID events driver (C) Jiri Kosina
console: usbcore: registered new interface driver usbhid
console: usbhid: USB HID core driver
console: Initializing XFRM netlink socket
console: sunxi-mmc 1c0f000.mmc: initialized, max. request size: 16384 KB
console: NET: Registered protocol family 10
console: mmc0: host does not support reading read-only switch, assuming w=
rite-enable
console: mmc0: Problem switching card into high-speed mode!
console: mmc0: new SD card at address 4567
console: mmcblk0: mmc0:4567 QEMU! 60.0 MiB
[...]
console: EXT4-fs (mmcblk0): mounting ext2 file system using the ext4 subs=
ystem
console: EXT4-fs (mmcblk0): mounted filesystem without journal. Opts: (nu=
ll)
console: VFS: Mounted root (ext2 filesystem) on device 179:0.
console: Run /sbin/init as init process
console: EXT4-fs (mmcblk0): re-mounted. Opts: block_validity,barrier,user=
_xattr,acl
console: Starting syslogd: OK
console: Starting klogd: OK
console: Populating /dev using udev: udevd[203]: starting version 3.2.7
console: /bin/sh: can't access tty; job control turned off
console: cat /proc/partitions
console: / # cat /proc/partitions
console: major minor #blocks name
console: 1 0 4096 ram0
console: 1 1 4096 ram1
console: 1 2 4096 ram2
console: 1 3 4096 ram3
console: 179 0 61440 mmcblk0
console: reboot
console: / # reboot
console: umount: devtmpfs busy - remounted read-only
console: EXT4-fs (mmcblk0): re-mounted. Opts: (null)
console: The system is going down NOW!
console: Sent SIGTERM to all processes
console: Sent SIGKILL to all processes
console: Requesting system reboot
console: reboot: Restarting system
JOB TIME : 68.64 s
Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Message-id: 20200311221854.30370-16-nieklinnenbank@gmail.com
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
[NL: extend test with ethernet device checks]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/acceptance/boot_linux_console.py | 47 ++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot=
_linux_console.py
index dabc8ef2afb..0762dbe83a5 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -572,6 +572,53 @@ class BootLinuxConsole(Test):
exec_command_and_wait_for_pattern(self, 'reboot',
'reboot: Restarting system=
')
=20
+ def test_arm_orangepi_sd(self):
+ """
+ :avocado: tags=3Darch:arm
+ :avocado: tags=3Dmachine:orangepi-pc
+ """
+ deb_url =3D ('https://apt.armbian.com/pool/main/l/'
+ 'linux-4.20.7-sunxi/linux-image-dev-sunxi_5.75_armhf.de=
b')
+ deb_hash =3D '1334c29c44d984ffa05ed10de8c3361f33d78315'
+ deb_path =3D self.fetch_asset(deb_url, asset_hash=3Ddeb_hash)
+ kernel_path =3D self.extract_from_deb(deb_path,
+ '/boot/vmlinuz-4.20.7-sunxi')
+ dtb_path =3D '/usr/lib/linux-image-dev-sunxi/sun8i-h3-orangepi-pc.=
dtb'
+ dtb_path =3D self.extract_from_deb(deb_path, dtb_path)
+ rootfs_url =3D ('http://storage.kernelci.org/images/rootfs/buildro=
ot/'
+ 'kci-2019.02/armel/base/rootfs.ext2.xz')
+ rootfs_hash =3D '692510cb625efda31640d1de0a8d60e26040f061'
+ rootfs_path_xz =3D self.fetch_asset(rootfs_url, asset_hash=3Drootf=
s_hash)
+ rootfs_path =3D os.path.join(self.workdir, 'rootfs.cpio')
+ archive.lzma_uncompress(rootfs_path_xz, rootfs_path)
+
+ self.vm.set_console()
+ kernel_command_line =3D (self.KERNEL_COMMON_COMMAND_LINE +
+ 'console=3DttyS0,115200 '
+ 'root=3D/dev/mmcblk0 rootwait rw '
+ 'panic=3D-1 noreboot')
+ self.vm.add_args('-kernel', kernel_path,
+ '-dtb', dtb_path,
+ '-drive', 'file=3D' + rootfs_path + ',if=3Dsd,for=
mat=3Draw',
+ '-append', kernel_command_line,
+ '-no-reboot')
+ self.vm.launch()
+ shell_ready =3D "/bin/sh: can't access tty; job control turned off"
+ self.wait_for_console_pattern(shell_ready)
+
+ exec_command_and_wait_for_pattern(self, 'cat /proc/cpuinfo',
+ 'Allwinner sun8i Family')
+ exec_command_and_wait_for_pattern(self, 'cat /proc/partitions',
+ 'mmcblk0')
+ exec_command_and_wait_for_pattern(self, 'ifconfig eth0 up',
+ 'eth0: Link is Up')
+ exec_command_and_wait_for_pattern(self, 'udhcpc eth0',
+ 'udhcpc: lease of 10.0.2.15 obtained')
+ exec_command_and_wait_for_pattern(self, 'ping -c 3 10.0.2.2',
+ '3 packets transmitted, 3 packets received, 0% packet loss')
+ exec_command_and_wait_for_pattern(self, 'reboot',
+ 'reboot: Restarting system=
')
+
def test_s390x_s390_ccw_virtio(self):
"""
:avocado: tags=3Darch:s390x
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 27/36] tests/boot_linux_console: Add a SLOW test booting Ubuntu
on OrangePi PC
Date: Thu, 12 Mar 2020 16:44:50 +0000
Message-Id: <20200312164459.25924-28-peter.maydell@linaro.org>
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From: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
This test boots Ubuntu Bionic on a OrangePi PC board.
As it requires 1GB of storage, and is slow, this test is disabled
on automatic CI testing.
It is useful for workstation testing. Currently Avocado timeouts too
quickly, so we can't run userland commands.
The kernel image and DeviceTree blob are built by the Armbian
project (based on Debian):
https://www.armbian.com/orange-pi-pc/
The Ubuntu image is downloaded from:
https://dl.armbian.com/orangepipc/Bionic_current
This test can be run using:
$ AVOCADO_ALLOW_LARGE_STORAGE=3Dyes \
avocado --show=3Dapp,console run -t machine:orangepi-pc \
tests/acceptance/boot_linux_console.py
console: U-Boot SPL 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100)
console: DRAM: 1024 MiB
console: Failed to set core voltage! Can't set CPU frequency
console: Trying to boot from MMC1
console: U-Boot 2019.04-armbian (Nov 18 2019 - 23:08:35 +0100) Allwinner =
Technology
console: CPU: Allwinner H3 (SUN8I 0000)
console: Model: Xunlong Orange Pi PC
console: DRAM: 1 GiB
console: MMC: mmc@1c0f000: 0
[...]
console: Uncompressing Linux... done, booting the kernel.
console: Booting Linux on physical CPU 0x0
console: Linux version 5.3.9-sunxi (root@builder) (gcc version 8.3.0 (GNU=
Toolchain for the A-profile Architecture 8.3-2019.03 (arm-rel-8.36))) #19.=
11.3 SMP Mon Nov 18 18:49:43 CET 2019
console: CPU: ARMv7 Processor [410fc075] revision 5 (ARMv7), cr=3D50c5387d
console: CPU: div instructions available: patching division code
console: CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instructi=
on cache
console: OF: fdt: Machine model: Xunlong Orange Pi PC
[...]
console: EXT4-fs (mmcblk0p1): mounted filesystem with writeback data mode=
. Opts: (null)
console: done.
console: Begin: Running /scripts/local-bottom ... done.
console: Begin: Running /scripts/init-bottom ... done.
console: systemd[1]: systemd 237 running in system mode. (...)
console: systemd[1]: Detected architecture arm.
console: Welcome to Ubuntu 18.04.3 LTS!
console: systemd[1]: Set hostname to <orangepipc>.
Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Message-id: 20200311221854.30370-17-nieklinnenbank@gmail.com
[NL: rename in commit message Raspbian to Armbian, remove vm.set_machine()]
[NL: changed test to boot from SD card via BootROM, added check for 7z]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/acceptance/boot_linux_console.py | 48 ++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot=
_linux_console.py
index 0762dbe83a5..e035c88b078 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -19,7 +19,13 @@ from avocado_qemu import exec_command_and_wait_for_patte=
rn
from avocado_qemu import wait_for_console_pattern
from avocado.utils import process
from avocado.utils import archive
+from avocado.utils.path import find_command, CmdNotFoundError
=20
+P7ZIP_AVAILABLE =3D True
+try:
+ find_command('7z')
+except CmdNotFoundError:
+ P7ZIP_AVAILABLE =3D False
=20
class BootLinuxConsole(Test):
"""
@@ -619,6 +625,48 @@ class BootLinuxConsole(Test):
exec_command_and_wait_for_pattern(self, 'reboot',
'reboot: Restarting system=
')
=20
+ @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited=
')
+ @skipUnless(P7ZIP_AVAILABLE, '7z not installed')
+ def test_arm_orangepi_bionic(self):
+ """
+ :avocado: tags=3Darch:arm
+ :avocado: tags=3Dmachine:orangepi-pc
+ """
+
+ # This test download a 196MB compressed image and expand it to 932=
MB...
+ image_url =3D ('https://dl.armbian.com/orangepipc/archive/'
+ 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.7z')
+ image_hash =3D '196a8ffb72b0123d92cea4a070894813d305c71e'
+ image_path_7z =3D self.fetch_asset(image_url, asset_hash=3Dimage_h=
ash)
+ image_name =3D 'Armbian_19.11.3_Orangepipc_bionic_current_5.3.9.im=
g'
+ image_path =3D os.path.join(self.workdir, image_name)
+ process.run("7z e -o%s %s" % (self.workdir, image_path_7z))
+
+ self.vm.set_console()
+ self.vm.add_args('-drive', 'file=3D' + image_path + ',if=3Dsd,form=
at=3Draw',
+ '-nic', 'user',
+ '-no-reboot')
+ self.vm.launch()
+
+ kernel_command_line =3D (self.KERNEL_COMMON_COMMAND_LINE +
+ 'console=3DttyS0,115200 '
+ 'loglevel=3D7 '
+ 'nosmp '
+ 'systemd.default_timeout_start_sec=3D9000 '
+ 'systemd.mask=3Darmbian-zram-config.service=
'
+ 'systemd.mask=3Darmbian-ramlog.service')
+
+ self.wait_for_console_pattern('U-Boot SPL')
+ self.wait_for_console_pattern('Autoboot in ')
+ exec_command_and_wait_for_pattern(self, ' ', '=3D>')
+ exec_command_and_wait_for_pattern(self, "setenv extraargs '" +
+ kernel_command_line + "'",=
'=3D>')
+ exec_command_and_wait_for_pattern(self, 'boot', 'Starting kernel .=
..');
+
+ self.wait_for_console_pattern('systemd[1]: Set hostname ' +
+ 'to <orangepipc>')
+ self.wait_for_console_pattern('Starting Load Kernel Modules...')
+
def test_s390x_s390_ccw_virtio(self):
"""
:avocado: tags=3Darch:s390x
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 28/36] tests/boot_linux_console: Test booting NetBSD via U-Boot
on OrangePi PC
Date: Thu, 12 Mar 2020 16:44:51 +0000
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From: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
This test boots U-Boot then NetBSD (stored on a SD card) on
a OrangePi PC board.
As it requires ~1.3GB of storage, it is disabled by default.
U-Boot is built by the Debian project [1], and the SD card image
is provided by the NetBSD organization [2].
Once the compressed SD card image is downloaded (304MB) and
extracted, this test is fast:
$ AVOCADO_ALLOW_LARGE_STORAGE=3Dyes \
avocado --show=3Dapp,console run -t machine:orangepi-pc \
tests/acceptance/boot_linux_console.py
console: U-Boot SPL 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000)
console: DRAM: 1024 MiB
console: U-Boot 2020.01+dfsg-1 (Jan 08 2020 - 08:19:44 +0000) Allwinner T=
echnology
console: CPU: Allwinner H3 (SUN8I 0000)
console: scanning bus usb@1c1b000 for devices... 1 USB Device(s) found
console: scanning bus usb@1c1d000 for devices... 1 USB Device(s) found
console: scanning usb for storage devices... 0 Storage Device(s) found
console: Hit any key to stop autoboot: 0
console: =3D> setenv bootargs root=3Dld0a
console: =3D> setenv kernel netbsd-GENERIC.ub
console: =3D> setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb
console: =3D> boot
console: ## Booting kernel from Legacy Image at 42000000 ...
console: Image Name: NetBSD/earmv7hf 9.0_RC1
console: Image Type: ARM Linux Kernel Image (no loading done) (uncompre=
ssed)
console: XIP Kernel Image (no loading done)
console: Loading Device Tree to 49ff6000, end 49fffe01 ... OK
console: Starting kernel ...
console: [ 1.0000000] NetBSD/evbarm (fdt) booting ...
console: [ 1.0000000] NetBSD 9.0 (GENERIC) #0: Fri Feb 14 00:06:28 UTC =
2020
console: [ 1.0000000] mkrepro@mkrepro.NetBSD.org:/usr/src/sys/a=
rch/evbarm/compile/GENERIC
console: [ 1.0000000] total memory =3D 1024 MB
console: [ 1.0000000] avail memory =3D 1003 MB
console: [ 1.0000000] armfdt0 (root)
console: [ 1.0000000] simplebus0 at armfdt0: Xunlong Orange Pi PC
console: [ 1.0000000] cpu0 at cpus0: Cortex-A7 r0p5 (Cortex V7A core)
console: [ 1.0000000] cpu0: DC enabled IC enabled WB enabled LABT branc=
h prediction enabled
console: [ 1.0000000] cpu0: 32KB/64B 2-way L1 VIPT Instruction cache
console: [ 1.0000000] cpu0: 32KB/64B 2-way write-back-locking-C L1 PIPT=
Data cache
console: [ 1.0000000] cpu0: 2304KB/64B 16-way write-through L2 PIPT Uni=
fied cache
console: [ 1.0000000] vfp0 at cpu0: NEON MPE (VFP 3.0+), rounding, NaN =
propagation, denormals
...
console: [ 2.3812082] sdmmc0: SD card status: 4-bit, C0
console: [ 2.3812082] ld0 at sdmmc0: <0xaa:0x5859:QEMU!:0x01:0xdeadbeef=
:0x062>
console: [ 2.4012856] ld0: 1226 MB, 622 cyl, 64 head, 63 sec, 512 bytes=
/sect x 2511872 sectors
console: [ 2.5321222] ld0: 4-bit width, High-Speed/SDR25, 50.000 MHz
console: [ 3.1068718] WARNING: 4 errors while detecting hardware; check=
system log.
console: [ 3.1179868] boot device: ld0
console: [ 3.1470623] root on ld0a dumps on ld0b
console: [ 3.2464436] root file system type: ffs
console: [ 3.2897123] kern.module.path=3D/stand/evbarm/9.0/modules
console: Mon Feb 17 20:33:35 UTC 2020
console: Starting root file system check:
PASS (35.96 s)
RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | =
CANCEL 0
JOB TIME : 36.09 s
Note, this test only took ~65 seconds to run on Travis-CI, see: [3].
This test is based on a description from Niek Linnenbank from [4].
[1] https://wiki.debian.org/InstallingDebianOn/Allwinner#Creating_a_bootabl=
e_SD_Card_with_u-boot
[2] https://wiki.netbsd.org/ports/evbarm/allwinner/
[3] https://travis-ci.org/philmd/qemu/jobs/638823612#L3778
[4] https://www.mail-archive.com/qemu-devel@nongnu.org/msg669347.html
Signed-off-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Tested-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Message-id: 20200311221854.30370-18-nieklinnenbank@gmail.com
[NL: changed test to use NetBSD 9.0 final release and -global allwinner-rtc=
.base-year]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
tests/acceptance/boot_linux_console.py | 70 ++++++++++++++++++++++++++
1 file changed, 70 insertions(+)
diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot=
_linux_console.py
index e035c88b078..f825cd9ef55 100644
--- a/tests/acceptance/boot_linux_console.py
+++ b/tests/acceptance/boot_linux_console.py
@@ -16,6 +16,7 @@ import shutil
from avocado import skipUnless
from avocado_qemu import Test
from avocado_qemu import exec_command_and_wait_for_pattern
+from avocado_qemu import interrupt_interactive_console_until_pattern
from avocado_qemu import wait_for_console_pattern
from avocado.utils import process
from avocado.utils import archive
@@ -667,6 +668,75 @@ class BootLinuxConsole(Test):
'to <orangepipc>')
self.wait_for_console_pattern('Starting Load Kernel Modules...')
=20
+ @skipUnless(os.getenv('AVOCADO_ALLOW_LARGE_STORAGE'), 'storage limited=
')
+ def test_arm_orangepi_uboot_netbsd9(self):
+ """
+ :avocado: tags=3Darch:arm
+ :avocado: tags=3Dmachine:orangepi-pc
+ """
+ # This test download a 304MB compressed image and expand it to 1.3=
GB...
+ deb_url =3D ('http://snapshot.debian.org/archive/debian/'
+ '20200108T145233Z/pool/main/u/u-boot/'
+ 'u-boot-sunxi_2020.01%2Bdfsg-1_armhf.deb')
+ deb_hash =3D 'f67f404a80753ca3d1258f13e38f2b060e13db99'
+ deb_path =3D self.fetch_asset(deb_url, asset_hash=3Ddeb_hash)
+ # We use the common OrangePi PC 'plus' build of U-Boot for our sec=
ondary
+ # program loader (SPL). We will then set the path to the more spec=
ific
+ # OrangePi "PC" device tree blob with 'setenv fdtfile' in U-Boot p=
rompt,
+ # before to boot NetBSD.
+ uboot_path =3D '/usr/lib/u-boot/orangepi_plus/u-boot-sunxi-with-sp=
l.bin'
+ uboot_path =3D self.extract_from_deb(deb_path, uboot_path)
+ image_url =3D ('https://cdn.netbsd.org/pub/NetBSD/NetBSD-9.0/'
+ 'evbarm-earmv7hf/binary/gzimg/armv7.img.gz')
+ image_hash =3D '2babb29d36d8360adcb39c09e31060945259917a'
+ image_path_gz =3D self.fetch_asset(image_url, asset_hash=3Dimage_h=
ash)
+ image_path =3D os.path.join(self.workdir, 'armv7.img')
+ image_drive_args =3D 'if=3Dsd,format=3Draw,snapshot=3Don,file=3D' =
+ image_path
+ archive.gzip_uncompress(image_path_gz, image_path)
+
+ # dd if=3Du-boot-sunxi-with-spl.bin of=3Darmv7.img bs=3D1K seek=3D=
8 conv=3Dnotrunc
+ with open(uboot_path, 'rb') as f_in:
+ with open(image_path, 'r+b') as f_out:
+ f_out.seek(8 * 1024)
+ shutil.copyfileobj(f_in, f_out)
+
+ # Extend image, to avoid that NetBSD thinks the partition
+ # inside the image is larger than device size itself
+ f_out.seek(0, 2)
+ f_out.seek(64 * 1024 * 1024, 1)
+ f_out.write(bytearray([0x00]))
+
+ self.vm.set_console()
+ self.vm.add_args('-nic', 'user',
+ '-drive', image_drive_args,
+ '-global', 'allwinner-rtc.base-year=3D2000',
+ '-no-reboot')
+ self.vm.launch()
+ wait_for_console_pattern(self, 'U-Boot 2020.01+dfsg-1')
+ interrupt_interactive_console_until_pattern(self,
+ 'Hit any key to stop autoboot:',
+ 'switch to partitions #0, OK')
+
+ exec_command_and_wait_for_pattern(self, '', '=3D>')
+ cmd =3D 'setenv bootargs root=3Dld0a'
+ exec_command_and_wait_for_pattern(self, cmd, '=3D>')
+ cmd =3D 'setenv kernel netbsd-GENERIC.ub'
+ exec_command_and_wait_for_pattern(self, cmd, '=3D>')
+ cmd =3D 'setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb'
+ exec_command_and_wait_for_pattern(self, cmd, '=3D>')
+ cmd =3D ("setenv bootcmd 'fatload mmc 0:1 ${kernel_addr_r} ${kerne=
l}; "
+ "fatload mmc 0:1 ${fdt_addr_r} ${fdtfile}; "
+ "fdt addr ${fdt_addr_r}; "
+ "bootm ${kernel_addr_r} - ${fdt_addr_r}'")
+ exec_command_and_wait_for_pattern(self, cmd, '=3D>')
+
+ exec_command_and_wait_for_pattern(self, 'boot',
+ 'Booting kernel from Legacy Imag=
e')
+ wait_for_console_pattern(self, 'Starting kernel ...')
+ wait_for_console_pattern(self, 'NetBSD 9.0 (GENERIC)')
+ # Wait for user-space
+ wait_for_console_pattern(self, 'Starting root file system check')
+
def test_s390x_s390_ccw_virtio(self):
"""
:avocado: tags=3Darch:s390x
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 29/36] docs: add Orange Pi PC document
Date: Thu, 12 Mar 2020 16:44:52 +0000
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From: Niek Linnenbank <nieklinnenbank@gmail.com>
The Xunlong Orange Pi PC machine is a functional ARM machine
based on the Allwinner H3 System-on-Chip. It supports mainline
Linux, U-Boot, NetBSD and is covered by acceptance tests.
This commit adds a documentation text file with a description
of the machine and instructions for the user.
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Message-id: 20200311221854.30370-19-nieklinnenbank@gmail.com
[PMM: moved file into docs/system/arm to match the reorg
of the arm target part of the docs; tweaked heading to
match other boards]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
MAINTAINERS | 1 +
docs/system/arm/orangepi.rst | 253 +++++++++++++++++++++++++++++++++++
docs/system/target-arm.rst | 2 +
3 files changed, 256 insertions(+)
create mode 100644 docs/system/arm/orangepi.rst
diff --git a/MAINTAINERS b/MAINTAINERS
index d7a26d7171e..32867bc6367 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -499,6 +499,7 @@ S: Maintained
F: hw/*/allwinner-h3*
F: include/hw/*/allwinner-h3*
F: hw/arm/orangepi.c
+F: docs/system/orangepi.rst
=20
ARM PrimeCell and CMSDK devices
M: Peter Maydell <peter.maydell@linaro.org>
diff --git a/docs/system/arm/orangepi.rst b/docs/system/arm/orangepi.rst
new file mode 100644
index 00000000000..c41adad4883
--- /dev/null
+++ b/docs/system/arm/orangepi.rst
@@ -0,0 +1,253 @@
+Orange Pi PC (``orangepi-pc``)
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
+The Xunlong Orange Pi PC is an Allwinner H3 System on Chip
+based embedded computer with mainline support in both U-Boot
+and Linux. The board comes with a Quad Core Cortex-A7 @ 1.3GHz,
+1GiB RAM, 100Mbit ethernet, USB, SD/MMC, USB, HDMI and
+various other I/O.
+
+Supported devices
+"""""""""""""""""
+
+The Orange Pi PC machine supports the following devices:
+
+ * SMP (Quad Core Cortex-A7)
+ * Generic Interrupt Controller configuration
+ * SRAM mappings
+ * SDRAM controller
+ * Real Time Clock
+ * Timer device (re-used from Allwinner A10)
+ * UART
+ * SD/MMC storage controller
+ * EMAC ethernet
+ * USB 2.0 interfaces
+ * Clock Control Unit
+ * System Control module
+ * Security Identifier device
+
+Limitations
+"""""""""""
+
+Currently, Orange Pi PC does *not* support the following features:
+
+- Graphical output via HDMI, GPU and/or the Display Engine
+- Audio output
+- Hardware Watchdog
+
+Also see the 'unimplemented' array in the Allwinner H3 SoC module
+for a complete list of unimplemented I/O devices: ``./hw/arm/allwinner-h3.=
c``
+
+Boot options
+""""""""""""
+
+The Orange Pi PC machine can start using the standard -kernel functionality
+for loading a Linux kernel or ELF executable. Additionally, the Orange Pi =
PC
+machine can also emulate the BootROM which is present on an actual Allwinn=
er H3
+based SoC, which loads the bootloader from a SD card, specified via the -s=
d argument
+to qemu-system-arm.
+
+Machine-specific options
+""""""""""""""""""""""""
+
+The following machine-specific options are supported:
+
+- allwinner-rtc.base-year=3DYYYY
+
+ The Allwinner RTC device is automatically created by the Orange Pi PC ma=
chine
+ and uses a default base year value which can be overridden using the 'ba=
se-year' property.
+ The base year is the actual represented year when the RTC year value is =
zero.
+ This option can be used in case the target operating system driver uses =
a different
+ base year value. The minimum value for the base year is 1900.
+
+- allwinner-sid.identifier=3Dabcd1122-a000-b000-c000-12345678ffff
+
+ The Security Identifier value can be read by the guest.
+ For example, U-Boot uses it to determine a unique MAC address.
+
+The above machine-specific options can be specified in qemu-system-arm
+via the '-global' argument, for example:
+
+.. code-block:: bash
+
+ $ qemu-system-arm -M orangepi-pc -sd mycard.img \
+ -global allwinner-rtc.base-year=3D2000
+
+Running mainline Linux
+""""""""""""""""""""""
+
+Mainline Linux kernels from 4.19 up to latest master are known to work.
+To build a Linux mainline kernel that can be booted by the Orange Pi PC ma=
chine,
+simply configure the kernel using the sunxi_defconfig configuration:
+
+.. code-block:: bash
+
+ $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make mrproper
+ $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make sunxi_defconfig
+
+To be able to use USB storage, you need to manually enable the correspondi=
ng
+configuration item. Start the kconfig configuration tool:
+
+.. code-block:: bash
+
+ $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make menuconfig
+
+Navigate to the following item, enable it and save your configuration:
+
+ Device Drivers > USB support > USB Mass Storage support
+
+Build the Linux kernel with:
+
+.. code-block:: bash
+
+ $ ARCH=3Darm CROSS_COMPILE=3Darm-linux-gnueabi- make
+
+To boot the newly build linux kernel in QEMU with the Orange Pi PC machine=
, use:
+
+.. code-block:: bash
+
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
+ -kernel /path/to/linux/arch/arm/boot/zImage \
+ -append 'console=3DttyS0,115200' \
+ -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb
+
+Orange Pi PC images
+"""""""""""""""""""
+
+Note that the mainline kernel does not have a root filesystem. You may pro=
vide it
+with an official Orange Pi PC image from the official website:
+
+ http://www.orangepi.org/downloadresources/
+
+Another possibility is to run an Armbian image for Orange Pi PC which
+can be downloaded from:
+
+ https://www.armbian.com/orange-pi-pc/
+
+Alternatively, you can also choose to build you own image with buildroot
+using the orangepi_pc_defconfig. Also see https://buildroot.org for more i=
nformation.
+
+You can choose to attach the selected image either as an SD card or as USB=
mass storage.
+For example, to boot using the Orange Pi PC Debian image on SD card, simpl=
y add the -sd
+argument and provide the proper root=3D kernel parameter:
+
+.. code-block:: bash
+
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
+ -kernel /path/to/linux/arch/arm/boot/zImage \
+ -append 'console=3DttyS0,115200 root=3D/dev/mmcblk0p2' \
+ -dtb /path/to/linux/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dtb \
+ -sd OrangePi_pc_debian_stretch_server_linux5.3.5_v1.0.img
+
+To attach the image as an USB mass storage device to the machine,
+simply append to the command:
+
+.. code-block:: bash
+
+ -drive if=3Dnone,id=3Dstick,file=3Dmyimage.img \
+ -device usb-storage,bus=3Dusb-bus.0,drive=3Dstick
+
+Instead of providing a custom Linux kernel via the -kernel command you may=
also
+choose to let the Orange Pi PC machine load the bootloader from SD card, j=
ust like
+a real board would do using the BootROM. Simply pass the selected image vi=
a the -sd
+argument and remove the -kernel, -append, -dbt and -initrd arguments:
+
+.. code-block:: bash
+
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
+ -sd Armbian_19.11.3_Orangepipc_buster_current_5.3.9.img
+
+Note that both the official Orange Pi PC images and Armbian images start
+a lot of userland programs via systemd. Depending on the host hardware and=
OS,
+they may be slow to emulate, especially due to emulating the 4 cores.
+To help reduce the performance slow down due to emulating the 4 cores, you=
can
+give the following kernel parameters via U-Boot (or via -append):
+
+.. code-block:: bash
+
+ =3D> setenv extraargs 'systemd.default_timeout_start_sec=3D9000 loglevel=
=3D7 nosmp console=3DttyS0,115200'
+
+Running U-Boot
+""""""""""""""
+
+U-Boot mainline can be build and configured using the orangepi_pc_defconfig
+using similar commands as describe above for Linux. Note that it is recomm=
ended
+for development/testing to select the following configuration setting in U=
-Boot:
+
+ Device Tree Control > Provider for DTB for DT Control > Embedded DTB
+
+To start U-Boot using the Orange Pi PC machine, provide the
+u-boot binary to the -kernel argument:
+
+.. code-block:: bash
+
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
+ -kernel /path/to/uboot/u-boot -sd disk.img
+
+Use the following U-boot commands to load and boot a Linux kernel from SD =
card:
+
+.. code-block:: bash
+
+ =3D> setenv bootargs console=3DttyS0,115200
+ =3D> ext2load mmc 0 0x42000000 zImage
+ =3D> ext2load mmc 0 0x43000000 sun8i-h3-orangepi-pc.dtb
+ =3D> bootz 0x42000000 - 0x43000000
+
+Running NetBSD
+""""""""""""""
+
+The NetBSD operating system also includes support for Allwinner H3 based b=
oards,
+including the Orange Pi PC. NetBSD 9.0 is known to work best for the Orang=
e Pi PC
+board and provides a fully working system with serial console, networking =
and storage.
+For the Orange Pi PC machine, get the 'evbarm-earmv7hf' based image from:
+
+ https://cdn.netbsd.org/pub/NetBSD/NetBSD-9.0/evbarm-earmv7hf/binary/gzim=
g/armv7.img.gz
+
+The image requires manually installing U-Boot in the image. Build U-Boot w=
ith
+the orangepi_pc_defconfig configuration as described in the previous secti=
on.
+Next, unzip the NetBSD image and write the U-Boot binary including SPL usi=
ng:
+
+.. code-block:: bash
+
+ $ gunzip armv7.img.gz
+ $ dd if=3D/path/to/u-boot-sunxi-with-spl.bin of=3Darmv7.img bs=3D1024 se=
ek=3D8 conv=3Dnotrunc
+
+Finally, before starting the machine the SD image must be extended such
+that the NetBSD kernel will not conclude the NetBSD partition is larger th=
an
+the emulated SD card:
+
+.. code-block:: bash
+
+ $ dd if=3D/dev/zero bs=3D1M count=3D64 >> armv7.img
+
+Start the machine using the following command:
+
+.. code-block:: bash
+
+ $ qemu-system-arm -M orangepi-pc -nic user -nographic \
+ -sd armv7.img -global allwinner-rtc.base-year=3D2000
+
+At the U-Boot stage, interrupt the automatic boot process by pressing a key
+and set the following environment variables before booting:
+
+.. code-block:: bash
+
+ =3D> setenv bootargs root=3Dld0a
+ =3D> setenv kernel netbsd-GENERIC.ub
+ =3D> setenv fdtfile dtb/sun8i-h3-orangepi-pc.dtb
+ =3D> setenv bootcmd 'fatload mmc 0:1 ${kernel_addr_r} ${kernel}; fatload=
mmc 0:1 ${fdt_addr_r} ${fdtfile}; fdt addr ${fdt_addr_r}; bootm ${kernel_a=
ddr_r} - ${fdt_addr_r}'
+
+Optionally you may save the environment variables to SD card with 'saveenv=
'.
+To continue booting simply give the 'boot' command and NetBSD boots.
+
+Orange Pi PC acceptance tests
+"""""""""""""""""""""""""""""
+
+The Orange Pi PC machine has several acceptance tests included.
+To run the whole set of tests, build QEMU from source and simply
+provide the following command:
+
+.. code-block:: bash
+
+ $ AVOCADO_ALLOW_LARGE_STORAGE=3Dyes avocado --show=3Dapp,console run \
+ -t machine:orangepi-pc tests/acceptance/boot_linux_console.py
diff --git a/docs/system/target-arm.rst b/docs/system/target-arm.rst
index 1425bd5303a..324e2af1cbc 100644
--- a/docs/system/target-arm.rst
+++ b/docs/system/target-arm.rst
@@ -68,6 +68,7 @@ undocumented; you can get a complete list by running
``qemu-system-aarch64 --machine help``.
=20
.. toctree::
+ :maxdepth: 1
=20
arm/integratorcp
arm/versatile
@@ -78,6 +79,7 @@ undocumented; you can get a complete list by running
arm/stellaris
arm/musicpal
arm/sx1
+ arm/orangepi
=20
Arm CPU features
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 30/36] hw/arm/virt: Document 'max' value in gic-version
property description
Date: Thu, 12 Mar 2020 16:44:53 +0000
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From: Eric Auger <eric.auger@redhat.com>
Mention 'max' value in the gic-version property description.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20200311131618.7187-2-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 32d865a4886..7c38c6c7f91 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -2146,7 +2146,8 @@ static void virt_instance_init(Object *obj)
virt_set_gic_version, NULL);
object_property_set_description(obj, "gic-version",
"Set GIC version. "
- "Valid values are 2, 3 and host", NULL=
);
+ "Valid values are 2, 3, host and max",
+ NULL);
=20
vms->highmem_ecam =3D !vmc->no_highmem_ecam;
=20
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 31/36] hw/arm/virt: Introduce VirtGICType enum type
Date: Thu, 12 Mar 2020 16:44:54 +0000
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From: Eric Auger <eric.auger@redhat.com>
We plan to introduce yet another value for the gic version (nosel).
As we already use exotic values such as 0 and -1, let's introduce
a dedicated enum type and let vms->gic_version take this
type.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <philmd@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20200311131618.7187-3-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/virt.h | 11 +++++++++--
hw/arm/virt.c | 30 +++++++++++++++---------------
2 files changed, 24 insertions(+), 17 deletions(-)
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 02f500cb8e2..c0827cacdf3 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -95,6 +95,13 @@ typedef enum VirtIOMMUType {
VIRT_IOMMU_VIRTIO,
} VirtIOMMUType;
=20
+typedef enum VirtGICType {
+ VIRT_GIC_VERSION_MAX,
+ VIRT_GIC_VERSION_HOST,
+ VIRT_GIC_VERSION_2,
+ VIRT_GIC_VERSION_3,
+} VirtGICType;
+
typedef struct MemMapEntry {
hwaddr base;
hwaddr size;
@@ -123,7 +130,7 @@ typedef struct {
bool highmem_ecam;
bool its;
bool virt;
- int32_t gic_version;
+ VirtGICType gic_version;
VirtIOMMUType iommu;
uint16_t virtio_iommu_bdf;
struct arm_boot_info bootinfo;
@@ -162,7 +169,7 @@ static inline int virt_gicv3_redist_region_count(VirtMa=
chineState *vms)
uint32_t redist0_capacity =3D
vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
=20
- assert(vms->gic_version =3D=3D 3);
+ assert(vms->gic_version =3D=3D VIRT_GIC_VERSION_3);
=20
return vms->smp_cpus > redist0_capacity ? 2 : 1;
}
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 7c38c6c7f91..4ed1f0cb2e5 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -299,7 +299,7 @@ static void fdt_add_timer_nodes(const VirtMachineState =
*vms)
irqflags =3D GIC_FDT_IRQ_FLAGS_EDGE_LO_HI;
}
=20
- if (vms->gic_version =3D=3D 2) {
+ if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) {
irqflags =3D deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
GIC_FDT_IRQ_PPI_CPU_WIDTH,
(1 << vms->smp_cpus) - 1);
@@ -440,7 +440,7 @@ static void fdt_add_gic_node(VirtMachineState *vms)
qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2);
qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2);
qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0);
- if (vms->gic_version =3D=3D 3) {
+ if (vms->gic_version =3D=3D VIRT_GIC_VERSION_3) {
int nb_redist_regions =3D virt_gicv3_redist_region_count(vms);
=20
qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
@@ -519,7 +519,7 @@ static void fdt_add_pmu_nodes(const VirtMachineState *v=
ms)
}
}
=20
- if (vms->gic_version =3D=3D 2) {
+ if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) {
irqflags =3D deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START,
GIC_FDT_IRQ_PPI_CPU_WIDTH,
(1 << vms->smp_cpus) - 1);
@@ -1470,7 +1470,7 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState=
*vms, int idx)
* purposes are to make TCG consistent (with 64-bit KVM hosts)
* and to improve SGI efficiency.
*/
- if (vms->gic_version =3D=3D 3) {
+ if (vms->gic_version =3D=3D VIRT_GIC_VERSION_3) {
clustersz =3D GICV3_TARGETLIST_BITS;
} else {
clustersz =3D GIC_TARGETLIST_BITS;
@@ -1561,15 +1561,15 @@ static void machvirt_init(MachineState *machine)
/* We can probe only here because during property set
* KVM is not available yet
*/
- if (vms->gic_version <=3D 0) {
- /* "host" or "max" */
+ if (vms->gic_version =3D=3D VIRT_GIC_VERSION_HOST ||
+ vms->gic_version =3D=3D VIRT_GIC_VERSION_MAX) {
if (!kvm_enabled()) {
- if (vms->gic_version =3D=3D 0) {
+ if (vms->gic_version =3D=3D VIRT_GIC_VERSION_HOST) {
error_report("gic-version=3Dhost requires KVM");
exit(1);
} else {
/* "max": currently means 3 for TCG */
- vms->gic_version =3D 3;
+ vms->gic_version =3D VIRT_GIC_VERSION_3;
}
} else {
vms->gic_version =3D kvm_arm_vgic_probe();
@@ -1628,7 +1628,7 @@ static void machvirt_init(MachineState *machine)
/* The maximum number of CPUs depends on the GIC version, or on how
* many redistributors we can fit into the memory map.
*/
- if (vms->gic_version =3D=3D 3) {
+ if (vms->gic_version =3D=3D VIRT_GIC_VERSION_3) {
virt_max_cpus =3D
vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE;
virt_max_cpus +=3D
@@ -1856,7 +1856,7 @@ static void virt_set_its(Object *obj, bool value, Err=
or **errp)
static char *virt_get_gic_version(Object *obj, Error **errp)
{
VirtMachineState *vms =3D VIRT_MACHINE(obj);
- const char *val =3D vms->gic_version =3D=3D 3 ? "3" : "2";
+ const char *val =3D vms->gic_version =3D=3D VIRT_GIC_VERSION_3 ? "3" :=
"2";
=20
return g_strdup(val);
}
@@ -1866,13 +1866,13 @@ static void virt_set_gic_version(Object *obj, const=
char *value, Error **errp)
VirtMachineState *vms =3D VIRT_MACHINE(obj);
=20
if (!strcmp(value, "3")) {
- vms->gic_version =3D 3;
+ vms->gic_version =3D VIRT_GIC_VERSION_3;
} else if (!strcmp(value, "2")) {
- vms->gic_version =3D 2;
+ vms->gic_version =3D VIRT_GIC_VERSION_2;
} else if (!strcmp(value, "host")) {
- vms->gic_version =3D 0; /* Will probe later */
+ vms->gic_version =3D VIRT_GIC_VERSION_HOST; /* Will probe later */
} else if (!strcmp(value, "max")) {
- vms->gic_version =3D -1; /* Will probe later */
+ vms->gic_version =3D VIRT_GIC_VERSION_MAX; /* Will probe later */
} else {
error_setg(errp, "Invalid gic-version value");
error_append_hint(errp, "Valid values are 3, 2, host, max.\n");
@@ -2141,7 +2141,7 @@ static void virt_instance_init(Object *obj)
"physical address space above 32 bits",
NULL);
/* Default GIC type is v2 */
- vms->gic_version =3D 2;
+ vms->gic_version =3D VIRT_GIC_VERSION_2;
object_property_add_str(obj, "gic-version", virt_get_gic_version,
virt_set_gic_version, NULL);
object_property_set_description(obj, "gic-version",
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 32/36] hw/arm/virt: Introduce finalize_gic_version()
Date: Thu, 12 Mar 2020 16:44:55 +0000
Message-Id: <20200312164459.25924-33-peter.maydell@linaro.org>
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From: Eric Auger <eric.auger@redhat.com>
Let's move the code which freezes which gic-version to
be applied in a dedicated function. We also now set by
default the VIRT_GIC_VERSION_NO_SET. This eventually
turns into the legacy v2 choice in the finalize() function.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20200311131618.7187-4-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/virt.h | 1 +
hw/arm/virt.c | 54 ++++++++++++++++++++++++++-----------------
2 files changed, 34 insertions(+), 21 deletions(-)
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index c0827cacdf3..893796d3b06 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -100,6 +100,7 @@ typedef enum VirtGICType {
VIRT_GIC_VERSION_HOST,
VIRT_GIC_VERSION_2,
VIRT_GIC_VERSION_3,
+ VIRT_GIC_VERSION_NOSEL,
} VirtGICType;
=20
typedef struct MemMapEntry {
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 4ed1f0cb2e5..e55cafa014b 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1535,6 +1535,37 @@ static void virt_set_memmap(VirtMachineState *vms)
}
}
=20
+/*
+ * finalize_gic_version - Determines the final gic_version
+ * according to the gic-version property
+ *
+ * Default GIC type is v2
+ */
+static void finalize_gic_version(VirtMachineState *vms)
+{
+ if (vms->gic_version =3D=3D VIRT_GIC_VERSION_HOST ||
+ vms->gic_version =3D=3D VIRT_GIC_VERSION_MAX) {
+ if (!kvm_enabled()) {
+ if (vms->gic_version =3D=3D VIRT_GIC_VERSION_HOST) {
+ error_report("gic-version=3Dhost requires KVM");
+ exit(1);
+ } else {
+ /* "max": currently means 3 for TCG */
+ vms->gic_version =3D VIRT_GIC_VERSION_3;
+ }
+ } else {
+ vms->gic_version =3D kvm_arm_vgic_probe();
+ if (!vms->gic_version) {
+ error_report(
+ "Unable to determine GIC version supported by host");
+ exit(1);
+ }
+ }
+ } else if (vms->gic_version =3D=3D VIRT_GIC_VERSION_NOSEL) {
+ vms->gic_version =3D VIRT_GIC_VERSION_2;
+ }
+}
+
static void machvirt_init(MachineState *machine)
{
VirtMachineState *vms =3D VIRT_MACHINE(machine);
@@ -1561,25 +1592,7 @@ static void machvirt_init(MachineState *machine)
/* We can probe only here because during property set
* KVM is not available yet
*/
- if (vms->gic_version =3D=3D VIRT_GIC_VERSION_HOST ||
- vms->gic_version =3D=3D VIRT_GIC_VERSION_MAX) {
- if (!kvm_enabled()) {
- if (vms->gic_version =3D=3D VIRT_GIC_VERSION_HOST) {
- error_report("gic-version=3Dhost requires KVM");
- exit(1);
- } else {
- /* "max": currently means 3 for TCG */
- vms->gic_version =3D VIRT_GIC_VERSION_3;
- }
- } else {
- vms->gic_version =3D kvm_arm_vgic_probe();
- if (!vms->gic_version) {
- error_report(
- "Unable to determine GIC version supported by host");
- exit(1);
- }
- }
- }
+ finalize_gic_version(vms);
=20
if (!cpu_type_valid(machine->cpu_type)) {
error_report("mach-virt: CPU type %s not supported", machine->cpu_=
type);
@@ -2140,8 +2153,7 @@ static void virt_instance_init(Object *obj)
"Set on/off to enable/disable using "
"physical address space above 32 bits",
NULL);
- /* Default GIC type is v2 */
- vms->gic_version =3D VIRT_GIC_VERSION_2;
+ vms->gic_version =3D VIRT_GIC_VERSION_NOSEL;
object_property_add_str(obj, "gic-version", virt_get_gic_version,
virt_set_gic_version, NULL);
object_property_set_description(obj, "gic-version",
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 33/36] target/arm/kvm: Let kvm_arm_vgic_probe() return a bitmap
Date: Thu, 12 Mar 2020 16:44:56 +0000
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From: Eric Auger <eric.auger@redhat.com>
Convert kvm_arm_vgic_probe() so that it returns a
bitmap of supported in-kernel emulation VGIC versions instead
of the max version: at the moment values can be v2 and v3.
This allows to expose the case where the host GICv3 also
supports GICv2 emulation. This will be useful to choose the
default version in KVM accelerated mode.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200311131618.7187-5-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/kvm_arm.h | 3 +++
hw/arm/virt.c | 11 +++++++++--
target/arm/kvm.c | 14 ++++++++------
3 files changed, 20 insertions(+), 8 deletions(-)
diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h
index ae9e075d754..48bf5e16d58 100644
--- a/target/arm/kvm_arm.h
+++ b/target/arm/kvm_arm.h
@@ -15,6 +15,9 @@
#include "exec/memory.h"
#include "qemu/error-report.h"
=20
+#define KVM_ARM_VGIC_V2 (1 << 0)
+#define KVM_ARM_VGIC_V3 (1 << 1)
+
/**
* kvm_arm_vcpu_init:
* @cs: CPUState
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index e55cafa014b..a94bc5ddae5 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1554,11 +1554,18 @@ static void finalize_gic_version(VirtMachineState *=
vms)
vms->gic_version =3D VIRT_GIC_VERSION_3;
}
} else {
- vms->gic_version =3D kvm_arm_vgic_probe();
- if (!vms->gic_version) {
+ int probe_bitmap =3D kvm_arm_vgic_probe();
+
+ if (!probe_bitmap) {
error_report(
"Unable to determine GIC version supported by host");
exit(1);
+ } else {
+ if (probe_bitmap & KVM_ARM_VGIC_V3) {
+ vms->gic_version =3D VIRT_GIC_VERSION_3;
+ } else {
+ vms->gic_version =3D VIRT_GIC_VERSION_2;
+ }
}
}
} else if (vms->gic_version =3D=3D VIRT_GIC_VERSION_NOSEL) {
diff --git a/target/arm/kvm.c b/target/arm/kvm.c
index 85860e6f954..390077c5182 100644
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -874,15 +874,17 @@ int kvm_arch_irqchip_create(KVMState *s)
=20
int kvm_arm_vgic_probe(void)
{
+ int val =3D 0;
+
if (kvm_create_device(kvm_state,
KVM_DEV_TYPE_ARM_VGIC_V3, true) =3D=3D 0) {
- return 3;
- } else if (kvm_create_device(kvm_state,
- KVM_DEV_TYPE_ARM_VGIC_V2, true) =3D=3D 0)=
{
- return 2;
- } else {
- return 0;
+ val |=3D KVM_ARM_VGIC_V3;
}
+ if (kvm_create_device(kvm_state,
+ KVM_DEV_TYPE_ARM_VGIC_V2, true) =3D=3D 0) {
+ val |=3D KVM_ARM_VGIC_V2;
+ }
+ return val;
}
=20
int kvm_arm_set_irq(int cpu, int irqtype, int irq, int level)
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 34/36] hw/arm/virt: kvm: Restructure finalize_gic_version()
Date: Thu, 12 Mar 2020 16:44:57 +0000
Message-Id: <20200312164459.25924-35-peter.maydell@linaro.org>
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From: Eric Auger <eric.auger@redhat.com>
Restructure the finalize_gic_version with switch cases and
clearly separate the following cases:
- KVM mode / in-kernel irqchip
- KVM mode / userspace irqchip
- TCG mode
In KVM mode / in-kernel irqchip , we explictly check whether
the chosen version is supported by the host. If the end-user
explicitly sets v2/v3 and this is not supported by the host,
then the user gets an explicit error message. Note that for
old kernels where the CREATE_DEVICE ioctl doesn't exist then
we will now fail if the user specifically asked for gicv2,
where previously we (probably) would have succeeded.
In KVM mode / userspace irqchip we immediatly output an error
in case the end-user explicitly selected v3. Also we warn the
end-user about the unexpected usage of gic-version=3Dhost in
that case as only userspace GICv2 is supported.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20200311131618.7187-6-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt.c | 88 +++++++++++++++++++++++++++++++++++++++------------
1 file changed, 67 insertions(+), 21 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index a94bc5ddae5..90966580a3d 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1543,33 +1543,79 @@ static void virt_set_memmap(VirtMachineState *vms)
*/
static void finalize_gic_version(VirtMachineState *vms)
{
- if (vms->gic_version =3D=3D VIRT_GIC_VERSION_HOST ||
- vms->gic_version =3D=3D VIRT_GIC_VERSION_MAX) {
- if (!kvm_enabled()) {
- if (vms->gic_version =3D=3D VIRT_GIC_VERSION_HOST) {
- error_report("gic-version=3Dhost requires KVM");
- exit(1);
- } else {
- /* "max": currently means 3 for TCG */
- vms->gic_version =3D VIRT_GIC_VERSION_3;
- }
- } else {
- int probe_bitmap =3D kvm_arm_vgic_probe();
+ if (kvm_enabled()) {
+ int probe_bitmap;
=20
- if (!probe_bitmap) {
+ if (!kvm_irqchip_in_kernel()) {
+ switch (vms->gic_version) {
+ case VIRT_GIC_VERSION_HOST:
+ warn_report(
+ "gic-version=3Dhost not relevant with kernel-irqchip=
=3Doff "
+ "as only userspace GICv2 is supported. Using v2 ...");
+ return;
+ case VIRT_GIC_VERSION_MAX:
+ case VIRT_GIC_VERSION_NOSEL:
+ vms->gic_version =3D VIRT_GIC_VERSION_2;
+ return;
+ case VIRT_GIC_VERSION_2:
+ return;
+ case VIRT_GIC_VERSION_3:
error_report(
- "Unable to determine GIC version supported by host");
+ "gic-version=3D3 is not supported with kernel-irqchip=
=3Doff");
exit(1);
- } else {
- if (probe_bitmap & KVM_ARM_VGIC_V3) {
- vms->gic_version =3D VIRT_GIC_VERSION_3;
- } else {
- vms->gic_version =3D VIRT_GIC_VERSION_2;
- }
}
}
- } else if (vms->gic_version =3D=3D VIRT_GIC_VERSION_NOSEL) {
+
+ probe_bitmap =3D kvm_arm_vgic_probe();
+ if (!probe_bitmap) {
+ error_report("Unable to determine GIC version supported by hos=
t");
+ exit(1);
+ }
+
+ switch (vms->gic_version) {
+ case VIRT_GIC_VERSION_HOST:
+ case VIRT_GIC_VERSION_MAX:
+ if (probe_bitmap & KVM_ARM_VGIC_V3) {
+ vms->gic_version =3D VIRT_GIC_VERSION_3;
+ } else {
+ vms->gic_version =3D VIRT_GIC_VERSION_2;
+ }
+ return;
+ case VIRT_GIC_VERSION_NOSEL:
+ vms->gic_version =3D VIRT_GIC_VERSION_2;
+ break;
+ case VIRT_GIC_VERSION_2:
+ case VIRT_GIC_VERSION_3:
+ break;
+ }
+
+ /* Check chosen version is effectively supported by the host */
+ if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2 &&
+ !(probe_bitmap & KVM_ARM_VGIC_V2)) {
+ error_report("host does not support in-kernel GICv2 emulation"=
);
+ exit(1);
+ } else if (vms->gic_version =3D=3D VIRT_GIC_VERSION_3 &&
+ !(probe_bitmap & KVM_ARM_VGIC_V3)) {
+ error_report("host does not support in-kernel GICv3 emulation"=
);
+ exit(1);
+ }
+ return;
+ }
+
+ /* TCG mode */
+ switch (vms->gic_version) {
+ case VIRT_GIC_VERSION_NOSEL:
vms->gic_version =3D VIRT_GIC_VERSION_2;
+ break;
+ case VIRT_GIC_VERSION_MAX:
+ vms->gic_version =3D VIRT_GIC_VERSION_3;
+ break;
+ case VIRT_GIC_VERSION_HOST:
+ error_report("gic-version=3Dhost requires KVM");
+ exit(1);
+ case VIRT_GIC_VERSION_2:
+ case VIRT_GIC_VERSION_3:
+ break;
}
}
=20
--=20
2.20.1
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 35/36] hw/arm/virt: kvm: allow gicv3 by default if v2 cannot
work
Date: Thu, 12 Mar 2020 16:44:58 +0000
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From: Eric Auger <eric.auger@redhat.com>
At the moment if the end-user does not specify the gic-version along
with KVM acceleration, v2 is set by default. However most of the
systems now have GICv3 and sometimes they do not support GICv2
compatibility.
This patch keeps the default v2 selection in all cases except
in the KVM accelerated mode when either
- the host does not support GICv2 in-kernel emulation or
- number of VCPUS exceeds 8.
Those cases did not work anyway so we do not break any compatibility.
Now we get v3 selected in such a case.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reported-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20200311131618.7187-7-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 90966580a3d..94f93dda54f 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -1543,6 +1543,8 @@ static void virt_set_memmap(VirtMachineState *vms)
*/
static void finalize_gic_version(VirtMachineState *vms)
{
+ unsigned int max_cpus =3D MACHINE(vms)->smp.max_cpus;
+
if (kvm_enabled()) {
int probe_bitmap;
=20
@@ -1582,7 +1584,20 @@ static void finalize_gic_version(VirtMachineState *v=
ms)
}
return;
case VIRT_GIC_VERSION_NOSEL:
- vms->gic_version =3D VIRT_GIC_VERSION_2;
+ if ((probe_bitmap & KVM_ARM_VGIC_V2) && max_cpus <=3D GIC_NCPU=
) {
+ vms->gic_version =3D VIRT_GIC_VERSION_2;
+ } else if (probe_bitmap & KVM_ARM_VGIC_V3) {
+ /*
+ * in case the host does not support v2 in-kernel emulatio=
n or
+ * the end-user requested more than 8 VCPUs we now default
+ * to v3. In any case defaulting to v2 would be broken.
+ */
+ vms->gic_version =3D VIRT_GIC_VERSION_3;
+ } else if (max_cpus > GIC_NCPU) {
+ error_report("host only supports in-kernel GICv2 emulation=
"
+ "but more than 8 vcpus are requested");
+ exit(1);
+ }
break;
case VIRT_GIC_VERSION_2:
case VIRT_GIC_VERSION_3:
--=20
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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 36/36] target/arm: kvm: Inject events at the last stage of sync
Date: Thu, 12 Mar 2020 16:44:59 +0000
Message-Id: <20200312164459.25924-37-peter.maydell@linaro.org>
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From: Beata Michalska <beata.michalska@linaro.org>
KVM_SET_VCPU_EVENTS might actually lead to vcpu registers being modified.
As such this should be the last step of sync to avoid potential overwriting
of whatever changes KVM might have done.
Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Message-id: 20200312003401.29017-2-beata.michalska@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/kvm32.c | 15 ++++++++++-----
target/arm/kvm64.c | 15 ++++++++++-----
2 files changed, 20 insertions(+), 10 deletions(-)
diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c
index f703c4fcad8..f271181ab8e 100644
--- a/target/arm/kvm32.c
+++ b/target/arm/kvm32.c
@@ -409,17 +409,22 @@ int kvm_arch_put_registers(CPUState *cs, int level)
return ret;
}
=20
- ret =3D kvm_put_vcpu_events(cpu);
- if (ret) {
- return ret;
- }
-
write_cpustate_to_list(cpu, true);
=20
if (!write_list_to_kvmstate(cpu, level)) {
return EINVAL;
}
=20
+ /*
+ * Setting VCPU events should be triggered after syncing the registers
+ * to avoid overwriting potential changes made by KVM upon calling
+ * KVM_SET_VCPU_EVENTS ioctl
+ */
+ ret =3D kvm_put_vcpu_events(cpu);
+ if (ret) {
+ return ret;
+ }
+
kvm_arm_sync_mpstate_to_kvm(cpu);
=20
return ret;
diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c
index 93ba1448daf..be5b31c2b0f 100644
--- a/target/arm/kvm64.c
+++ b/target/arm/kvm64.c
@@ -1094,17 +1094,22 @@ int kvm_arch_put_registers(CPUState *cs, int level)
return ret;
}
=20
- ret =3D kvm_put_vcpu_events(cpu);
- if (ret) {
- return ret;
- }
-
write_cpustate_to_list(cpu, true);
=20
if (!write_list_to_kvmstate(cpu, level)) {
return -EINVAL;
}
=20
+ /*
+ * Setting VCPU events should be triggered after syncing the registers
+ * to avoid overwriting potential changes made by KVM upon calling
+ * KVM_SET_VCPU_EVENTS ioctl
+ */
+ ret =3D kvm_put_vcpu_events(cpu);
+ if (ret) {
+ return ret;
+ }
+
kvm_arm_sync_mpstate_to_kvm(cpu);
=20
return ret;
--=20
2.20.1