From nobody Tue Feb 10 12:13:44 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1584030961; cv=none; d=zohomail.com; s=zohoarc; b=CHUc4/qjKeNoWKRZNZfBcwln3yslofOqgJiVWS33YxkyzA4x3a/ThUmeP4gSCkd1a4NrFW9tE9DTtzQ1MRbG8L3mSeT6G3uurB7z36t45YsPbnI4c4q4Ncy3LjyYYtEEMVaNrqX3nukxtMhLgoociEL4iwk0CUFbfx4/euusJlE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584030961; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Thu, 12 Mar 2020 12:34:13 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:57740) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jCQmh-0001GW-LS; Thu, 12 Mar 2020 12:34:12 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.H-Q5Mm4_1584030840) by smtp.aliyun-inc.com(10.147.42.253); Fri, 13 Mar 2020 00:34:01 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07462233|-1; CH=blue; DM=||false|; DS=CONTINUE|ham_system_inform|0.00179811-4.04403e-05-0.998161; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03302; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.H-Q5Mm4_1584030840; From: LIU Zhiwei To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Subject: [PATCH v5 47/60] target/riscv: vector widening floating-point reduction instructions Date: Thu, 12 Mar 2020 22:58:47 +0800 Message-Id: <20200312145900.2054-48-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200312145900.2054-1-zhiwei_liu@c-sky.com> References: <20200312145900.2054-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- target/riscv/helper.h | 3 ++ target/riscv/insn32.decode | 2 + target/riscv/insn_trans/trans_rvv.inc.c | 3 ++ target/riscv/vector_helper.c | 50 +++++++++++++++++++++++++ 4 files changed, 58 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 0a1aa30514..b0bb617b42 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1071,3 +1071,6 @@ DEF_HELPER_6(vfredmax_vs_d, void, ptr, ptr, ptr, ptr,= env, i32) DEF_HELPER_6(vfredmin_vs_h, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfredmin_vs_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfredmin_vs_d, void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_6(vfwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 294e55b7ae..f1efc8886d 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -537,6 +537,8 @@ vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 = @r_vm vfredsum_vs 0000-1 . ..... ..... 001 ..... 1010111 @r_vm vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm +# Vector widening ordered and unordered float reduction sum +vfwredsum_vs 1100-1 . ..... ..... 001 ..... 1010111 @r_vm =20 vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index d66ec4a1e4..ad864c9742 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -2049,3 +2049,6 @@ GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check) GEN_OPFVV_TRANS(vfredsum_vs, reduction_check) GEN_OPFVV_TRANS(vfredmax_vs, reduction_check) GEN_OPFVV_TRANS(vfredmin_vs, reduction_check) + +/* Vector Widening Floating-Point Reduction Instructions */ +GEN_OPFVV_WIDEN_TRANS(vfwredsum_vs, reduction_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 948135f60b..d325fe5e2e 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4188,3 +4188,53 @@ GEN_VEXT_FRED(vfredmax_vs_d, uint64_t, uint64_t, H8,= H8, float64_maxnum, clearq) GEN_VEXT_FRED(vfredmin_vs_h, uint16_t, uint16_t, H2, H2, float16_minnum, c= learh) GEN_VEXT_FRED(vfredmin_vs_w, uint32_t, uint32_t, H4, H4, float32_minnum, c= learl) GEN_VEXT_FRED(vfredmin_vs_d, uint64_t, uint64_t, H8, H8, float64_minnum, c= learq) + +/* Vector Widening Floating-Point Reduction Instructions */ +/* Unordered reduce 2*SEW =3D 2*SEW + sum(promote(SEW)) */ +void HELPER(vfwredsum_vs_h)(void *vd, void *v0, void *vs1, + void *vs2, CPURISCVState *env, uint32_t desc) +{ + uint32_t mlen =3D vext_mlen(desc); + uint32_t vm =3D vext_vm(desc); + uint32_t vl =3D env->vl; + uint32_t i; + uint32_t tot =3D env_archcpu(env)->cfg.vlen / 8; + + uint32_t s1 =3D *((uint32_t *)vs1 + H4(0)); + for (i =3D 0; i < vl; i++) { + uint16_t s2 =3D *((uint16_t *)vs2 + H2(i)); + if (!vm && !vext_elem_mask(v0, mlen, i)) { + continue; + } + s1 =3D float32_add(s1, float16_to_float32(s2, true, &env->fp_statu= s), + &env->fp_status); + } + if (i !=3D 0) { + *((uint32_t *)vd + H4(0)) =3D s1; + clearl(vd, 1, sizeof(uint32_t), tot); + } +} + +void HELPER(vfwredsum_vs_w)(void *vd, void *v0, void *vs1, + void *vs2, CPURISCVState *env, uint32_t desc) +{ + uint32_t mlen =3D vext_mlen(desc); + uint32_t vm =3D vext_vm(desc); + uint32_t vl =3D env->vl; + uint32_t i; + uint32_t tot =3D env_archcpu(env)->cfg.vlen / 8; + + uint64_t s1 =3D *((uint64_t *)vs1); + for (i =3D 0; i < vl; i++) { + uint32_t s2 =3D *((uint32_t *)vs2 + H4(i)); + if (!vm && !vext_elem_mask(v0, mlen, i)) { + continue; + } + s1 =3D float64_add(s1, float32_to_float64(s2, &env->fp_status), + &env->fp_status); + } + if (i !=3D 0) { + *((uint64_t *)vd) =3D s1; + clearq(vd, 1, sizeof(uint64_t), tot); + } +} --=20 2.23.0