From nobody Sun Nov 2 10:15:28 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1583904162; cv=none; d=zohomail.com; s=zohoarc; b=WJEJTPWAKKTs7ldXtudCmq+UwqOUhmKv6Fshe0QcwVoQ8YqwVb7FF86FGr956zCh2XkmFf9aIadAS2+AX3Tat65Rs2yhC+TtncEDQ9qGi6ctuHpvUlJLCy1vD5ufYUNBUpo8PFnEVWPF1nM6CZOJChNeFY98t0fU7Th5Lg9wLLE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1583904162; h=Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:Sender:Subject:To; bh=hNUEbJfvomucF6BiwKE6lNUf29qT7mZn2g8flH0nQ3M=; b=VL54xf2pSkkGDEnRPmiHttSgskc6p78KfatuqqFc5duYfFPOP3wEyLRJcZsqWtZPGY2K8emZdmblyPDGrTJHuEcsBWN8pCPIsdp0f0cjGMhnTexb+OyH7CMQqMzUuQk0+G8gaOiv/00Gxj3KOIC8OxAtJhMqin/fuch+yujWRvY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1583904162354631.9077747457928; Tue, 10 Mar 2020 22:22:42 -0700 (PDT) Received: from localhost ([::1]:44254 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jBtpJ-00076J-AI for importer@patchew.org; Wed, 11 Mar 2020 01:22:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34702) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jBtoU-0005kd-H4 for qemu-devel@nongnu.org; Wed, 11 Mar 2020 01:21:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jBtoT-0007Il-7G for qemu-devel@nongnu.org; Wed, 11 Mar 2020 01:21:50 -0400 Received: from mail-pl1-x644.google.com ([2607:f8b0:4864:20::644]:46257) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jBtoS-0007G7-Uj for qemu-devel@nongnu.org; Wed, 11 Mar 2020 01:21:49 -0400 Received: by mail-pl1-x644.google.com with SMTP id w12so500068pll.13 for ; Tue, 10 Mar 2020 22:21:48 -0700 (PDT) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id w17sm7276332pfi.59.2020.03.10.22.21.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 10 Mar 2020 22:21:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id; bh=hNUEbJfvomucF6BiwKE6lNUf29qT7mZn2g8flH0nQ3M=; b=xP5KUi1o/4+iZpMdMXzVUUNmLiGbBcOgAhPcpiKrleyqSXxYIxmm7qwjvCyNSeJVAd qoD53sXGhKrT+Gx7BzW+RemqnEC+8KWBaHX20px02idaHptnIApzJHfLkPj97VItDCda L3CzmUcUdVMsSwb0xozlYlxilh7ENLZkzzklZOs3X4+p82Zlah+FxLXpOJUG0hmAjKTk fBxcP/is7xxE6qATneLgLffTTA2/wLeGcZm958hLNTzfbO+3jM8WQfe4fG7q4k0OsA6l xh52oYgj67yZ4fs+la6Pj4bwlkLtNi1M/CKLiixIoN0lmeBLLiyPRfW5Blwx4ysYCOxc Ys5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id; bh=hNUEbJfvomucF6BiwKE6lNUf29qT7mZn2g8flH0nQ3M=; b=hiruJLgICBYmqm5LjxR3YHIrxQyqCFE8R5R59bmKqM7HQD8Zvg1z+KESYbiApJLPoh fmjObxCgcsQLRpQJ06jux5zF3rBuCbdrHdSKv5I9TtLeJpOCf2e0C7vsUH7rghLwsppE J41lOqGW8atq7ZjtKO/+/q3fDMYgAfUrJz+PhtCK5xkTxRGMvruTBwoKOxDWNC/r27Fj /7GvB9Dyo9FN+nR3XYEhwxsPYwPfXWq6D+NgbLvCbgl/WDZqHFDXeknLrbifJOuZn/ie PCdx4YoNu9oNRNW40J56IAzvGGAlCO6nXG7UOvzFClVgkMReUBICwhCohxQKC1YrVvr1 lEIw== X-Gm-Message-State: ANhLgQ0OysXT3a23quvQFVnY0YKH74VmKxmXxCsloPiYR5C1YG5rk9Mi j7LuvqDSYPsn9xCRJUTZT3z5JiTch90= X-Google-Smtp-Source: ADFU+vssgWb0m6z1I2PuulYEwZ6AjbMiA/5PrwYUuFf0vlPdGh7pVTVqXb4+0p92avl//n50G7/UBw== X-Received: by 2002:a17:90b:238e:: with SMTP id mr14mr1583249pjb.146.1583904107009; Tue, 10 Mar 2020 22:21:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH] tcg/i386: Bound shift count expanding sari_vec Date: Tue, 10 Mar 2020 22:21:45 -0700 Message-Id: <20200311052145.14004-1-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" A given RISU testcase for SVE can produce tcg-op-vec.c:511: do_shifti: Assertion `i >=3D 0 && i < (8 << vece)' failed. because expand_vec_sari gave a shift count of 32 to a MO_32 vector shift. In 44f1441dbe1, we changed from direct expansion of vector opcodes to re-use of the tcg expanders. So while the comment correctly notes that the hw will handle such a shift count, we now have to take our own sanity checks into account. Which is easy in this particular case. Fixes: 44f1441dbe1 Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.inc.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c index cdedcb2b25..223dba9c8c 100644 --- a/tcg/i386/tcg-target.inc.c +++ b/tcg/i386/tcg-target.inc.c @@ -3391,12 +3391,15 @@ static void expand_vec_sari(TCGType type, unsigned = vece, =20 case MO_64: if (imm <=3D 32) { - /* We can emulate a small sign extend by performing an arithme= tic + /* + * We can emulate a small sign extend by performing an arithme= tic * 32-bit shift and overwriting the high half of a 64-bit logi= cal - * shift (note that the ISA says shift of 32 is valid). + * shift. Note that the ISA says shift of 32 is valid, but TCG + * does not, so we have to bound the smaller shift -- we get t= he + * same result in the high half either way. */ t1 =3D tcg_temp_new_vec(type); - tcg_gen_sari_vec(MO_32, t1, v1, imm); + tcg_gen_sari_vec(MO_32, t1, v1, MIN(imm, 31)); tcg_gen_shri_vec(MO_64, v0, v1, imm); vec_gen_4(INDEX_op_x86_blend_vec, type, MO_32, tcgv_vec_arg(v0), tcgv_vec_arg(v0), --=20 2.17.1