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Mon, 09 Mar 2020 08:15:45 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:49984) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jBHJt-0002br-D4; Mon, 09 Mar 2020 08:15:41 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.GyaeXy8_1583756101) by smtp.aliyun-inc.com(10.147.41.199); Mon, 09 Mar 2020 20:15:15 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436294|-1; CH=blue; DM=||false|; DS=CONTINUE|ham_system_inform|0.377255-0.00325374-0.619491; FP=9693965973447181918|1|1|7|0|-1|-1|-1; HT=e02c03299; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.GyaeXy8_1583756101; From: LIU Zhiwei To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Subject: [PATCH v3 26/60] target/riscv: vector widening saturating scaled multiply-add Date: Mon, 9 Mar 2020 20:14:23 +0800 Message-Id: <20200309121457.13719-27-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200309121457.13719-1-zhiwei_liu@c-sky.com> References: <20200309121457.13719-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 22 +++ target/riscv/insn32.decode | 7 + target/riscv/insn_trans/trans_rvv.inc.c | 9 ++ target/riscv/vector_helper.c | 180 ++++++++++++++++++++++++ 4 files changed, 218 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 333eccca57..74c1c695e0 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -733,3 +733,25 @@ DEF_HELPER_6(vsmul_vx_b, void, ptr, ptr, tl, ptr, env,= i32) DEF_HELPER_6(vsmul_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsmul_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsmul_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vwsmaccu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsmaccu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsmaccu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsmaccsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsmaccsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsmaccsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwsmaccu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsmaccu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsmaccu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsmacc_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsmaccsu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsmaccsu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsmaccsu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwsmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 99f70924d6..8798919d3e 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -419,6 +419,13 @@ vasub_vv 100110 . ..... ..... 000 ..... 1010111= @r_vm vasub_vx 100110 . ..... ..... 100 ..... 1010111 @r_vm vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm +vwsmaccu_vv 111100 . ..... ..... 000 ..... 1010111 @r_vm +vwsmaccu_vx 111100 . ..... ..... 100 ..... 1010111 @r_vm +vwsmacc_vv 111101 . ..... ..... 000 ..... 1010111 @r_vm +vwsmacc_vx 111101 . ..... ..... 100 ..... 1010111 @r_vm +vwsmaccsu_vv 111110 . ..... ..... 000 ..... 1010111 @r_vm +vwsmaccsu_vx 111110 . ..... ..... 100 ..... 1010111 @r_vm +vwsmaccus_vx 111111 . ..... ..... 100 ..... 1010111 @r_vm =20 vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index 60e1e63b7b..68bebd3c37 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -1532,3 +1532,12 @@ GEN_OPIVI_TRANS(vaadd_vi, 0, vaadd_vx, opivx_check) /* Vector Single-Width Fractional Multiply with Rounding and Saturation */ GEN_OPIVV_TRANS(vsmul_vv, opivv_check) GEN_OPIVX_TRANS(vsmul_vx, opivx_check) + +/* Vector Widening Saturating Scaled Multiply-Add */ +GEN_OPIVV_WIDEN_TRANS(vwsmaccu_vv, opivv_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwsmacc_vv, opivv_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwsmaccsu_vv, opivv_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwsmaccu_vx) +GEN_OPIVX_WIDEN_TRANS(vwsmacc_vx) +GEN_OPIVX_WIDEN_TRANS(vwsmaccsu_vx) +GEN_OPIVX_WIDEN_TRANS(vwsmaccus_vx) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 74ad07743c..90c19577fa 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -2523,3 +2523,183 @@ GEN_VEXT_VX_ENV(vsmul_vx_b, 1, 1, clearb) GEN_VEXT_VX_ENV(vsmul_vx_h, 2, 2, clearh) GEN_VEXT_VX_ENV(vsmul_vx_w, 4, 4, clearl) GEN_VEXT_VX_ENV(vsmul_vx_d, 8, 8, clearq) + +/* Vector Widening Saturating Scaled Multiply-Add */ +static uint16_t vwsmaccu8(CPURISCVState *env, uint8_t a, uint8_t b, + uint16_t c) +{ + uint8_t round; + uint16_t res =3D (uint16_t)a * (uint16_t)b; + + round =3D get_round(env, res, 4); + res =3D (res >> 4) + round; + return saddu16(env, c, res); +} +static uint32_t vwsmaccu16(CPURISCVState *env, uint16_t a, uint16_t b, + uint32_t c) +{ + uint8_t round; + uint32_t res =3D (uint32_t)a * (uint32_t)b; + + round =3D get_round(env, res, 8); + res =3D (res >> 8) + round; + return saddu32(env, c, res); +} +static uint64_t vwsmaccu32(CPURISCVState *env, uint32_t a, uint32_t b, + uint64_t c) +{ + uint8_t round; + uint64_t res =3D (uint64_t)a * (uint64_t)b; + + round =3D get_round(env, res, 16); + res =3D (res >> 16) + round; + return saddu64(env, c, res); +} + +#define OPIVV3_ENV(NAME, TD, T1, T2, TX1, TX2, HD, HS1, HS2, OP) \ +static void do_##NAME(void *vd, void *vs1, void *vs2, int i, \ + CPURISCVState *env) \ +{ \ + TX1 s1 =3D *((T1 *)vs1 + HS1(i)); \ + TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ + TD d =3D *((TD *)vd + HD(i)); \ + *((TD *)vd + HD(i)) =3D OP(env, s2, s1, d); \ +} +RVVCALL(OPIVV3_ENV, vwsmaccu_vv_b, WOP_UUU_B, H2, H1, H1, vwsmaccu8) +RVVCALL(OPIVV3_ENV, vwsmaccu_vv_h, WOP_UUU_H, H4, H2, H2, vwsmaccu16) +RVVCALL(OPIVV3_ENV, vwsmaccu_vv_w, WOP_UUU_W, H8, H4, H4, vwsmaccu32) +GEN_VEXT_VV_ENV(vwsmaccu_vv_b, 1, 2, clearh) +GEN_VEXT_VV_ENV(vwsmaccu_vv_h, 2, 4, clearl) +GEN_VEXT_VV_ENV(vwsmaccu_vv_w, 4, 8, clearq) + +#define OPIVX3_ENV(NAME, TD, T1, T2, TX1, TX2, HD, HS2, OP) \ +static void do_##NAME(void *vd, target_ulong s1, void *vs2, int i, \ + CPURISCVState *env) \ +{ \ + TX2 s2 =3D *((T2 *)vs2 + HS2(i)); \ + TD d =3D *((TD *)vd + HD(i)); \ + *((TD *)vd + HD(i)) =3D OP(env, s2, (TX1)(T1)(target_long)s1, d); \ +} +RVVCALL(OPIVX3_ENV, vwsmaccu_vx_b, WOP_UUU_B, H2, H1, vwsmaccu8) +RVVCALL(OPIVX3_ENV, vwsmaccu_vx_h, WOP_UUU_H, H4, H2, vwsmaccu16) +RVVCALL(OPIVX3_ENV, vwsmaccu_vx_w, WOP_UUU_W, H8, H4, vwsmaccu32) +GEN_VEXT_VX_ENV(vwsmaccu_vx_b, 1, 2, clearh) +GEN_VEXT_VX_ENV(vwsmaccu_vx_h, 2, 4, clearl) +GEN_VEXT_VX_ENV(vwsmaccu_vx_w, 4, 8, clearq) + +static int16_t vwsmacc8(CPURISCVState *env, int8_t a, int8_t b, int16_t c) +{ + uint8_t round; + int16_t res =3D (int16_t)a * (int16_t)b; + + round =3D get_round(env, res, 4); + res =3D (res >> 4) + round; + return sadd16(env, c, res); +} +static int32_t vwsmacc16(CPURISCVState *env, int16_t a, int16_t b, int32_t= c) +{ + uint8_t round; + int32_t res =3D (int32_t)a * (int32_t)b; + + round =3D get_round(env, res, 8); + res =3D (res >> 8) + round; + return sadd32(env, c, res); + +} +static int64_t vwsmacc32(CPURISCVState *env, int32_t a, int32_t b, int64_t= c) +{ + uint8_t round; + int64_t res =3D (int64_t)a * (int64_t)b; + + round =3D get_round(env, res, 16); + res =3D (res >> 16) + round; + return sadd64(env, c, res); +} +RVVCALL(OPIVV3_ENV, vwsmacc_vv_b, WOP_SSS_B, H2, H1, H1, vwsmacc8) +RVVCALL(OPIVV3_ENV, vwsmacc_vv_h, WOP_SSS_H, H4, H2, H2, vwsmacc16) +RVVCALL(OPIVV3_ENV, vwsmacc_vv_w, WOP_SSS_W, H8, H4, H4, vwsmacc32) +GEN_VEXT_VV_ENV(vwsmacc_vv_b, 1, 2, clearh) +GEN_VEXT_VV_ENV(vwsmacc_vv_h, 2, 4, clearl) +GEN_VEXT_VV_ENV(vwsmacc_vv_w, 4, 8, clearq) +RVVCALL(OPIVX3_ENV, vwsmacc_vx_b, WOP_SSS_B, H2, H1, vwsmacc8) +RVVCALL(OPIVX3_ENV, vwsmacc_vx_h, WOP_SSS_H, H4, H2, vwsmacc16) +RVVCALL(OPIVX3_ENV, vwsmacc_vx_w, WOP_SSS_W, H8, H4, vwsmacc32) +GEN_VEXT_VX_ENV(vwsmacc_vx_b, 1, 2, clearh) +GEN_VEXT_VX_ENV(vwsmacc_vx_h, 2, 4, clearl) +GEN_VEXT_VX_ENV(vwsmacc_vx_w, 4, 8, clearq) + +static int16_t vwsmaccsu8(CPURISCVState *env, uint8_t a, int8_t b, int16_t= c) +{ + uint8_t round; + int16_t res =3D (uint16_t)a * (int16_t)b; + + round =3D get_round(env, res, 4); + res =3D (res >> 4) + round; + return ssub16(env, c, res); +} +static int32_t vwsmaccsu16(CPURISCVState *env, uint16_t a, int16_t b, + uint32_t c) +{ + uint8_t round; + int32_t res =3D (uint32_t)a * (int32_t)b; + + round =3D get_round(env, res, 8); + res =3D (res >> 8) + round; + return ssub32(env, c, res); +} +static int64_t vwsmaccsu32(CPURISCVState *env, uint32_t a, int32_t b, + int64_t c) +{ + uint8_t round; + int64_t res =3D (uint64_t)a * (int64_t)b; + + round =3D get_round(env, res, 16); + res =3D (res >> 16) + round; + return ssub64(env, c, res); +} +RVVCALL(OPIVV3_ENV, vwsmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, vwsmaccsu8) +RVVCALL(OPIVV3_ENV, vwsmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, vwsmaccsu16) +RVVCALL(OPIVV3_ENV, vwsmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, vwsmaccsu32) +GEN_VEXT_VV_ENV(vwsmaccsu_vv_b, 1, 2, clearh) +GEN_VEXT_VV_ENV(vwsmaccsu_vv_h, 2, 4, clearl) +GEN_VEXT_VV_ENV(vwsmaccsu_vv_w, 4, 8, clearq) +RVVCALL(OPIVX3_ENV, vwsmaccsu_vx_b, WOP_SSU_B, H2, H1, vwsmaccsu8) +RVVCALL(OPIVX3_ENV, vwsmaccsu_vx_h, WOP_SSU_H, H4, H2, vwsmaccsu16) +RVVCALL(OPIVX3_ENV, vwsmaccsu_vx_w, WOP_SSU_W, H8, H4, vwsmaccsu32) +GEN_VEXT_VX_ENV(vwsmaccsu_vx_b, 1, 2, clearh) +GEN_VEXT_VX_ENV(vwsmaccsu_vx_h, 2, 4, clearl) +GEN_VEXT_VX_ENV(vwsmaccsu_vx_w, 4, 8, clearq) + +static int16_t vwsmaccus8(CPURISCVState *env, int8_t a, uint8_t b, int16_t= c) +{ + uint8_t round; + int16_t res =3D (int16_t)a * (uint16_t)b; + + round =3D get_round(env, res, 4); + res =3D (res >> 4) + round; + return ssub16(env, c, res); +} +static int32_t vwsmaccus16(CPURISCVState *env, int16_t a, uint16_t b, int3= 2_t c) +{ + uint8_t round; + int32_t res =3D (int32_t)a * (uint32_t)b; + + round =3D get_round(env, res, 8); + res =3D (res >> 8) + round; + return ssub32(env, c, res); +} +static int64_t vwsmaccus32(CPURISCVState *env, int32_t a, uint32_t b, int6= 4_t c) +{ + uint8_t round; + int64_t res =3D (int64_t)a * (uint64_t)b; + + round =3D get_round(env, res, 16); + res =3D (res >> 16) + round; + return ssub64(env, c, res); +} +RVVCALL(OPIVX3_ENV, vwsmaccus_vx_b, WOP_SUS_B, H2, H1, vwsmaccus8) +RVVCALL(OPIVX3_ENV, vwsmaccus_vx_h, WOP_SUS_H, H4, H2, vwsmaccus16) +RVVCALL(OPIVX3_ENV, vwsmaccus_vx_w, WOP_SUS_W, H8, H4, vwsmaccus32) +GEN_VEXT_VX_ENV(vwsmaccus_vx_b, 1, 2, clearh) +GEN_VEXT_VX_ENV(vwsmaccus_vx_h, 2, 4, clearl) +GEN_VEXT_VX_ENV(vwsmaccus_vx_w, 4, 8, clearq) --=20 2.23.0