From nobody Fri Nov 14 00:48:45 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1583745751; cv=none; d=zohomail.com; s=zohoarc; b=bi+WhsHBv0VqN+Q88Qn5F+FQrOrQZhEYLgLmwU4gUPEimEOqgiDxLBZq2NhKe0Nr3HALYlJhyhcAu4lwFa65fn/4wdhj01nn1JIWOcN7BH/zRMUg32QhUJ+wPKC3CPSufqYSGrvEO/7lpIA/q7lq4QEZWGvq9j1SfgggwJLrNbI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1583745751; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nWshV78lC8QtbqE6hsJPZ14Cvq4tJRs1tiFsqcHYwr0=; b=RTYIs2FtqmHqPy8m/a7cZbWCaXObJgZ3OQ6csXe67b8b+Fq+Df1qYhjXF4ysnMtoRuNLEa+ZavmIiRYAAuxbz2DoOv6hqCy88jTRl3N7WNRJFh3mbM1I7buSLdTEwgr4FDU7V2Vkijj5AnNj/+TC7ZLQkukDnBHdEQ7hQcToFiI= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158374575169575.90539817239119; Mon, 9 Mar 2020 02:22:31 -0700 (PDT) Received: from localhost ([::1]:39254 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jBEcH-0001M9-K7 for importer@patchew.org; Mon, 09 Mar 2020 05:22:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56130) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jBEbO-000079-9e for qemu-devel@nongnu.org; Mon, 09 Mar 2020 05:21:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jBEbM-0002Ch-Ha for qemu-devel@nongnu.org; Mon, 09 Mar 2020 05:21:34 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:35083) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jBEbM-0002BO-56; Mon, 09 Mar 2020 05:21:32 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.GyVpCil_1583745606) by smtp.aliyun-inc.com(10.147.41.121); Mon, 09 Mar 2020 17:21:28 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436283|-1; CH=blue; DM=||false|; DS=CONTINUE|ham_system_inform|0.284299-0.00020209-0.715499; FP=9121874194399893506|1|1|7|0|-1|-1|-1; HT=e02c03307; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.GyVpCil_1583745606; From: LIU Zhiwei To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Subject: [PATCH v3 03/60] target/riscv: support vector extension csr Date: Mon, 9 Mar 2020 17:19:07 +0800 Message-Id: <20200309092004.13335-4-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200309092004.13335-1-zhiwei_liu@c-sky.com> References: <20200309092004.13335-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The v0.7.1 specification does not define vector status within mstatus. A future revision will define the privileged portion of the vector status. Signed-off-by: LIU Zhiwei --- target/riscv/cpu_bits.h | 15 +++++++++ target/riscv/csr.c | 75 ++++++++++++++++++++++++++++++++++++++++- 2 files changed, 89 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7f64ee1174..8117e8b5a7 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -29,6 +29,14 @@ #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_N= XA) =20 +/* Vector Fixed-Point round model */ +#define FSR_VXRM_SHIFT 9 +#define FSR_VXRM (0x3 << FSR_VXRM_SHIFT) + +/* Vector Fixed-Point saturation flag */ +#define FSR_VXSAT_SHIFT 8 +#define FSR_VXSAT (0x1 << FSR_VXSAT_SHIFT) + /* Control and Status Registers */ =20 /* User Trap Setup */ @@ -48,6 +56,13 @@ #define CSR_FRM 0x002 #define CSR_FCSR 0x003 =20 +/* User Vector CSRs */ +#define CSR_VSTART 0x008 +#define CSR_VXSAT 0x009 +#define CSR_VXRM 0x00a +#define CSR_VL 0xc20 +#define CSR_VTYPE 0xc21 + /* User Timers and Counters */ #define CSR_CYCLE 0xc00 #define CSR_TIME 0xc01 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 11d184cd16..d71c49dfff 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -46,6 +46,10 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *= ops) static int fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) + /* loose check condition for fcsr in vector extension */ + if ((csrno =3D=3D CSR_FCSR) && (env->misa & RVV)) { + return 0; + } if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } @@ -53,6 +57,14 @@ static int fs(CPURISCVState *env, int csrno) return 0; } =20 +static int vs(CPURISCVState *env, int csrno) +{ + if (env->misa & RVV) { + return 0; + } + return -1; +} + static int ctr(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) @@ -174,6 +186,10 @@ static int read_fcsr(CPURISCVState *env, int csrno, ta= rget_ulong *val) #endif *val =3D (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT) | (env->frm << FSR_RD_SHIFT); + if (vs(env, csrno) >=3D 0) { + *val |=3D (env->vxrm << FSR_VXRM_SHIFT) + | (env->vxsat << FSR_VXSAT_SHIFT); + } return 0; } =20 @@ -186,10 +202,62 @@ static int write_fcsr(CPURISCVState *env, int csrno, = target_ulong val) env->mstatus |=3D MSTATUS_FS; #endif env->frm =3D (val & FSR_RD) >> FSR_RD_SHIFT; + if (vs(env, csrno) >=3D 0) { + env->vxrm =3D (val & FSR_VXRM) >> FSR_VXRM_SHIFT; + env->vxsat =3D (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT; + } riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); return 0; } =20 +static int read_vtype(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vtype; + return 0; +} + +static int read_vl(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vl; + return 0; +} + +static int read_vxrm(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vxrm; + return 0; +} + +static int write_vxrm(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vxrm =3D val; + return 0; +} + +static int read_vxsat(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vxsat; + return 0; +} + +static int write_vxsat(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vxsat =3D val; + return 0; +} + +static int read_vstart(CPURISCVState *env, int csrno, target_ulong *val) +{ + *val =3D env->vstart; + return 0; +} + +static int write_vstart(CPURISCVState *env, int csrno, target_ulong val) +{ + env->vstart =3D val; + return 0; +} + /* User Timers and Counters */ static int read_instret(CPURISCVState *env, int csrno, target_ulong *val) { @@ -1269,7 +1337,12 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = =3D { [CSR_FFLAGS] =3D { fs, read_fflags, write_fflags = }, [CSR_FRM] =3D { fs, read_frm, write_frm = }, [CSR_FCSR] =3D { fs, read_fcsr, write_fcsr = }, - + /* Vector CSRs */ + [CSR_VSTART] =3D { vs, read_vstart, write_vstart = }, + [CSR_VXSAT] =3D { vs, read_vxsat, write_vxsat = }, + [CSR_VXRM] =3D { vs, read_vxrm, write_vxrm = }, + [CSR_VL] =3D { vs, read_vl = }, + [CSR_VTYPE] =3D { vs, read_vtype = }, /* User Timers and Counters */ [CSR_CYCLE] =3D { ctr, read_instret = }, [CSR_INSTRET] =3D { ctr, read_instret = }, --=20 2.23.0