From nobody Fri Nov 14 00:48:45 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1583745702; cv=none; d=zohomail.com; s=zohoarc; b=LfJ8mSNqyZoSse2/bTV+x6jfUZ3KTK2ViJHOfyqOFOmgU+NbyFbYAQcWiOvTmR+HGjX1UfMDS9Sd3ZEgPveldR6LexO6MNbkqrGaiOCBxuo1NgkZ1xWQgb/hKbiIX8uaghZQVTVXOjWytaFnTp8D6wIpcKHo3GqxBKq8krFOiNw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1583745702; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FV2fKVgi+UO3ahyQ8oJjdXFE6WCj7xxtSU0LvvimrfI=; b=EiH5lQPJl3S0hEmWTFterqkXMCGueytPzbp9YaHfZpNF2QSImOSoZuvNoAqFHJw7yd61Fs0fPtBbCfKdPFUzgRzyPGwX+9PtHF7r+xMZeRMom/HIH1j46OiqCtf3WKgfEmrih/6Xzfe1q+U7y8xYO9znMy3gkBPfxv1DscAeQyE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158374570214733.8012948456834; Mon, 9 Mar 2020 02:21:42 -0700 (PDT) Received: from localhost ([::1]:39230 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jBEbV-0008Mx-23 for importer@patchew.org; Mon, 09 Mar 2020 05:21:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55984) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jBEaa-0007Sp-WA for qemu-devel@nongnu.org; Mon, 09 Mar 2020 05:20:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jBEaZ-0001xk-SO for qemu-devel@nongnu.org; Mon, 09 Mar 2020 05:20:44 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:50702) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jBEaZ-0001wX-I5; Mon, 09 Mar 2020 05:20:43 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.GyVpCil_1583745606) by smtp.aliyun-inc.com(10.147.41.121); Mon, 09 Mar 2020 17:20:38 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.09717409|-1; CH=blue; DM=||false|; DS=CONTINUE|ham_system_inform|0.0359546-0.000358177-0.963687; FP=12030644411456161715|2|1|9|0|-1|-1|-1; HT=e02c03312; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=11; RT=11; SR=0; TI=SMTPD_---.GyVpCil_1583745606; From: LIU Zhiwei To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Subject: [PATCH v3 01/60] target/riscv: add vector extension field in CPURISCVState Date: Mon, 9 Mar 2020 17:19:05 +0800 Message-Id: <20200309092004.13335-2-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200309092004.13335-1-zhiwei_liu@c-sky.com> References: <20200309092004.13335-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno, offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3dcdf92227..0c1f7bdd8b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -64,6 +64,7 @@ #define RVA RV('A') #define RVF RV('F') #define RVD RV('D') +#define RVV RV('V') #define RVC RV('C') #define RVS RV('S') #define RVU RV('U') @@ -94,9 +95,20 @@ typedef struct CPURISCVState CPURISCVState; =20 #include "pmp.h" =20 +#define RV_VLEN_MAX 512 + struct CPURISCVState { target_ulong gpr[32]; uint64_t fpr[32]; /* assume both F and D extensions */ + + /* vector coprocessor state. */ + uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); + target_ulong vxrm; + target_ulong vxsat; + target_ulong vl; + target_ulong vstart; + target_ulong vtype; + target_ulong pc; target_ulong load_res; target_ulong load_val; --=20 2.23.0