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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w22sm10310729wmk.34.2020.03.05.08.31.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2020 08:31:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YYHIjy33GB3VuD4wC7Jf/ToNqj5l8tdIAcVXeQg/vp4=; b=EQIwyenBpY9WuM17efhrXAvdjsYUrASNdDg4ZvaHSauPIzmg20IpoGnoSPf5op8PFG z2J5nDEXOOo2lzxdRjcAcafIyBzCDOHRTNz3BLTmvlnPIC2j7XOLETMn2q+NL7C8Pdvs OWsmFt0y2CC7fMAQJFlhPYRdpwRcbBC8jn4dPSmd3sdU4DnIzKsV/U7oKPapF2iqaw4g KovCTAUgSM2NgzBrkgtAIXlATR+SOGn9Cgmm9hrYLyFYcmrCYljAeNVITEykvHrDegEb MDSNXsXmKEUl8+1E0hTE4WHtbN8qQ7w5rRdE6F8wKrS7uS4NCuSoNcBiezSlxhsAdD9a aj0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YYHIjy33GB3VuD4wC7Jf/ToNqj5l8tdIAcVXeQg/vp4=; b=Xi08d7tZtOlYa5ZdgNN3RLD5j4ytCPtD0wUP80uJr9frztA04CVJWu/3YjWYOjiaKl +3LzEGgnJ7AzkjpgUCMY2GZOtjfBJv/VnRYFJX3nQtKR+p038GhfRqy2Weo+sByrCiP3 1DNKAvxOxT09ZUD4wlf4mjZgtZoPbYNW9v5H9V2xnJUQRN3aNJ5sba5qUjQ7r7pUZMQI OwkL+/Lia8qTz9mqaBqgxUrNozNprcuTgr9D82+lixMcfi/p27QzzeCkOSg3HoIulhwV oN+by4TcFPopQVLlkgsyKQsbxMo9jhSxASxZimKV5WtkbaTLo8FJ0iOO0SHyCiqnoDkj Ch2w== X-Gm-Message-State: ANhLgQ0M3linEk70o0374sS3ykxF+66dUUCane383KJCN5yTLhAryeus mpbu6ZUvcGPFKySUmGGNqkOcLYl/OcQjMA== X-Google-Smtp-Source: ADFU+vtZWFhOBwxv/tcea7r1GfUyba79bHPU9j5ldaKnzFaOSFMjh/R7YnSya/kn554R3cJSV6lQAQ== X-Received: by 2002:a7b:c4cb:: with SMTP id g11mr10928624wmk.83.1583425897244; Thu, 05 Mar 2020 08:31:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/37] target/arm: Optimize cpu_mmu_index Date: Thu, 5 Mar 2020 16:30:55 +0000 Message-Id: <20200305163100.22912-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200305163100.22912-1-peter.maydell@linaro.org> References: <20200305163100.22912-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::333 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We now cache the core mmu_idx in env->hflags. Rather than recompute from scratch, extract the field. All of the uses of cpu_mmu_index within target/arm are within helpers, and env->hflags is always stable within a translation block from whence helpers are called. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20200302175829.2183-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 23 +++++++++++++---------- target/arm/helper.c | 5 ----- 2 files changed, 13 insertions(+), 15 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0ae07a72e43..4ffd991b6fc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2943,16 +2943,6 @@ typedef enum ARMMMUIdxBit { =20 #define MMU_USER_IDX 0 =20 -/** - * cpu_mmu_index: - * @env: The cpu environment - * @ifetch: True for code access, false for data access. - * - * Return the core mmu index for the current translation regime. - * This function is used by generic TCG code paths. - */ -int cpu_mmu_index(CPUARMState *env, bool ifetch); - /* Indexes used when registering address spaces with cpu_address_space_ini= t */ typedef enum ARMASIdx { ARMASIdx_NS =3D 0, @@ -3232,6 +3222,19 @@ FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cache= d. */ FIELD(TBFLAG_A64, TBID, 12, 2) FIELD(TBFLAG_A64, UNPRIV, 14, 1) =20 +/** + * cpu_mmu_index: + * @env: The cpu environment + * @ifetch: True for code access, false for data access. + * + * Return the core mmu index for the current translation regime. + * This function is used by generic TCG code paths. + */ +static inline int cpu_mmu_index(CPUARMState *env, bool ifetch) +{ + return FIELD_EX32(env->hflags, TBFLAG_ANY, MMUIDX); +} + static inline bool bswap_code(bool sctlr_b) { #ifdef CONFIG_USER_ONLY diff --git a/target/arm/helper.c b/target/arm/helper.c index f7ba34bbf6d..f91e5d5345f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12274,11 +12274,6 @@ ARMMMUIdx arm_mmu_idx(CPUARMState *env) return arm_mmu_idx_el(env, arm_current_el(env)); } =20 -int cpu_mmu_index(CPUARMState *env, bool ifetch) -{ - return arm_to_core_mmu_idx(arm_mmu_idx(env)); -} - #ifndef CONFIG_USER_ONLY ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) { --=20 2.20.1