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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w22sm10310729wmk.34.2020.03.05.08.31.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2020 08:31:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=cBpCaClb9/Cygo6mKyCev/5pUMwMYtTJNviojF+pUgs=; b=iakjqyEhuffLB3W6UrYStftfKEseihDk7eqC6Us48xyi8i7GHCAbrFIRM7ZjSz2oHW LpIdkMCbuhXgr6RDvXy7Q+4dxALrEYV2AHcv+MTfnigQ/QFhGaMMJoxejXAGHxof8/QH wIBtlTXqCBhPVD+e2CtFl2f58NIhpbMZRUDpvNJ5OpIE8TOsrz0X8B/zJZlQPWq8v1m7 60OJSH5gIEMbAumNe8lAtnTaukYRxBlVep/9bNgKLQ/s929IJ23L1TN65zHkPWKAOpaE ZaoE5o2+Tpzai6pKZszdJDLfM1ZtUJNyEOn1QU44hZfPFHIBUq2g76gSNfTZRmBkEmp1 9Sug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cBpCaClb9/Cygo6mKyCev/5pUMwMYtTJNviojF+pUgs=; b=FRbztYOKhZsWCH4RQ0C/T49rR5gvDazp6JXamttZaJbmqjdPLobo9Ogalghqsw1YU8 kMvpVytkVVAj10WTcKAr/ddQ4e8ZCLkOfhQsEa3GX7P3DFQThoXvYQnLU03D5Hwps1sb FCEVHYwkB/YEL1gz9uWF3xIOgyrMtOlzs6Drz6xJHB5pyOyS6MXOscZfzTJCsHu8D4X0 0JIy2WFUjMkOfntkBGTaHfXOXp9UyvFyxkvMhc++ptKfloJgvbmLMU8S8D53I8gXtfkk BdHIxEWWbz5rWmAj8dj3OTLWdvnQOIqgYG0ru7g3jvMvHvxpYkzZJsJ4ZO16KQHdWKaA wFqQ== X-Gm-Message-State: ANhLgQ0DQ2mnGO4tRaSRwpB75TNg44eDz9bWuj531UkQX63btfG6wtU9 a90rc/K8GfcPGFXnnkW8O+mCO+yH2naHPg== X-Google-Smtp-Source: ADFU+vv4jXOd0B5kPknWeGGDGR6RttbXBDFksxaMh5J0vV6FczDlxh4F7LN/4HHbLXSCMZPanV1Eyw== X-Received: by 2002:adf:ec50:: with SMTP id w16mr11312961wrn.9.1583425886968; Thu, 05 Mar 2020 08:31:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/37] target/arm: Honor the HCR_EL2.TPCP bit Date: Thu, 5 Mar 2020 16:30:46 +0000 Message-Id: <20200305163100.22912-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200305163100.22912-1-peter.maydell@linaro.org> References: <20200305163100.22912-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This bit traps EL1 access to cache maintenance insns that operate to the point of coherency or persistence. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200229012811.24129-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 39 +++++++++++++++++++++++++++++++-------- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e362d420eb4..e6eaec8ad31 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4314,6 +4314,28 @@ static CPAccessResult aa64_cacheop_access(CPUARMStat= e *env, return CP_ACCESS_OK; } =20 +static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* Cache invalidate/clean to Point of Coherency or Persistence... */ + switch (arm_current_el(env)) { + case 0: + /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ + if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { + return CP_ACCESS_TRAP; + } + /* fall through */ + case 1: + /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */ + if (arm_hcr_el2_eff(env) & HCR_TPCP) { + return CP_ACCESS_TRAP_EL2; + } + break; + } + return CP_ACCESS_OK; +} + /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru= ctions * Page D4-1736 (DDI0487A.b) */ @@ -4721,14 +4743,15 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .accessfn =3D aa64_cacheop_access }, { .name =3D "DC_IVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .accessfn =3D aa64_cacheop_poc_access, + .type =3D ARM_CP_NOP }, { .name =3D "DC_ISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, { .name =3D "DC_CVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_access }, + .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, @@ -4739,7 +4762,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DC_CIVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_access }, + .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, @@ -4921,17 +4944,17 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "BPIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 7, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6= , .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, { .name =3D "DCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, = .opc2 =3D 2, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DCCMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 0, .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, { .name =3D "DCCSW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 10,= .opc2 =3D 2, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DCCMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 1, .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D = 14, .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, { .name =3D "DCCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 14= , .opc2 =3D 2, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, /* MMU Domain access control / MPU write buffer control */ @@ -6750,7 +6773,7 @@ static const ARMCPRegInfo dcpop_reg[] =3D { { .name =3D "DC_CVAP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, - .accessfn =3D aa64_cacheop_access, .writefn =3D dccvap_writefn }, + .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, REGINFO_SENTINEL }; =20 @@ -6758,7 +6781,7 @@ static const ARMCPRegInfo dcpodp_reg[] =3D { { .name =3D "DC_CVADP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, - .accessfn =3D aa64_cacheop_access, .writefn =3D dccvap_writefn }, + .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, REGINFO_SENTINEL }; #endif /*CONFIG_USER_ONLY*/ --=20 2.20.1