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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w22sm10310729wmk.34.2020.03.05.08.31.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2020 08:31:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=63BtL3A7s5V/jzIhDC3vd/bTesp/g8P1iFKQFff6LWo=; b=nClBpPxjndfhpoJl1hjUUYvHDudxt3C40qKEBcV0F8m1tHwrctqPTgjSOgxDZX+Tjl X+SxlJGMzcPujcLvLt+tgvhEe3sWUlOec9DZupQote12LvKPANjrzjSc1Gc8udC/LYZ3 I+yHGpCh9POwj3NGS1kIFucmbSJItJYcFfO3ioNzO4di+fMQbE1IoE8yDPSmzoAm7eGI Ki8aAOwdGYQ8LB/Rz16JE8W9Q5dykHpEBZrYHh6KuHiaLv43CsBeRUnAMcH+q7rnWnm9 a1P36iJVlS0dWFlZ7+lpjWX3aiOG4pAzCHdN/ZdB3wFTku4Oui/loBzYYfT5e4jDBUL5 /OUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=63BtL3A7s5V/jzIhDC3vd/bTesp/g8P1iFKQFff6LWo=; b=c4h7oiD/MSaDN1VpeaB5McvTkOjgAlI06/105KeHne9DEOz0aKfD1ndyybMLrKdL4d L4lIJo8oeZYzO1mbILcrgMETOryplwiGI2qQqLGAKuxeG/q3vSQ+HzRXFGwNEAZul7/C lghHuSJB713imt+6F0vo7+8qE0Ey9z5P7vjwuRtu19Jmc420e9ZTCHn2C6p3Xxle0FlN UgkbAfE5+yunB6IG1N82fE/fAWOHbcaBLcplpVpkMfu/HkCVLDfXTQd4zIyjeq+wrqQK QfelKUAoJKOItrBHAGgPgWAks2DJCr3m5R4sjJj6fqitsMVGoTkfgf5Wlt+thK6XGg/A XxHw== X-Gm-Message-State: ANhLgQ36OP4nWgZVDwzSuN4ZZ2NjspZTKug+A6Mvx9rN9yhXrTAG1y4v Z4iPf4gDkPNtsbGbzGvCH3Rygd6Z2uzCLA== X-Google-Smtp-Source: ADFU+vuGyfydR8YAxAutrN36z0+zy9CFsH2Ns9QxkZPmrcrE2WUeuAZ24i9wcVfmfEGghWwaDDYLzg== X-Received: by 2002:adf:dd4d:: with SMTP id u13mr10990247wrm.70.1583425886040; Thu, 05 Mar 2020 08:31:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/37] target/arm: Honor the HCR_EL2.TACR bit Date: Thu, 5 Mar 2020 16:30:45 +0000 Message-Id: <20200305163100.22912-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200305163100.22912-1-peter.maydell@linaro.org> References: <20200305163100.22912-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson This bit traps EL1 access to the auxiliary control registers. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200229012811.24129-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index feb279f44e9..e362d420eb4 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -553,6 +553,16 @@ static CPAccessResult access_tsw(CPUARMState *env, con= st ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +/* Check for traps from EL1 due to HCR_EL2.TACR. */ +static CPAccessResult access_tacr(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TACR))= { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} + static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) { ARMCPU *cpu =3D env_archcpu(env); @@ -6961,8 +6971,8 @@ static const ARMCPRegInfo ats1cp_reginfo[] =3D { static const ARMCPRegInfo actlr2_hactlr2_reginfo[] =3D { { .name =3D "ACTLR2", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, + .access =3D PL1_RW, .accessfn =3D access_tacr, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "HACTLR2", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 3, .access =3D PL2_RW, .type =3D ARM_CP_CONST, @@ -7718,8 +7728,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo auxcr_reginfo[] =3D { { .name =3D "ACTLR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D cpu->reset_auxcr }, + .access =3D PL1_RW, .accessfn =3D access_tacr, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->reset_auxcr }, { .name =3D "ACTLR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, .access =3D PL2_RW, .type =3D ARM_CP_CONST, --=20 2.20.1