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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w22sm10310729wmk.34.2020.03.05.08.31.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2020 08:31:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Y/oEr6VfZD0tMuDYbhpwmohDwbWl4E1kQNKWWMvPtRI=; b=XKqL5+Telvdi3EXFGIMxrMF3dlzl6G8GTClU+b+PWCW4HYWTwFt13vfaDdiatt5aIx NLJIAGTyYHCTTwmztVradp8GyH4eT3W7Q92DRgWeoTVZwBJmZgqkzYymnZKDqlpk0u2J AhxP6fRNsKrAGB5I4qr26By7G1RG+7fLpL9lc/uoGw9VzhyGhU2clO0Xgnw4P6ItzBTB fcEQb6aJvIprkzfypSgn2EUgj9ZuTwOzrBkTsDlqEckUxAGlm7JwsPrhiB4v5BeAtVWW boRge7nxBH0yYYeo2JP8HefY+NPwqHhNzpep+6vQhvLpM4gc7MaQrVzl5Hgx4YjTtAoE ITTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Y/oEr6VfZD0tMuDYbhpwmohDwbWl4E1kQNKWWMvPtRI=; b=unKcuiGoD7DSf+w+RzEnsk8rzTISQb0U2YJmUZDaC0Z8slr8BbkcWdJHPocn+3zqGB E1FPtJq0Zp6H2QkN2LB3emdihAhCe3dUKPC8qf3PWaDKX2I5bnwHCQlkwsdQ1WvpSzWW Ft/D+QSurzG5sLridsYNEavIBKu7dSRQzyLlbyUadgIK0XQQGrCc2o+ZRwFfWywa7WsQ JYteeNELNXwl5GjSP2gvaGAVJpJxcD9/E9MRQFwNXMnhxECMzolp2ZSZUfi813+PrAsh m/KBS9UM3Nts5OO1wlKfM64XT/D5gkEOwQtVjNFO4HB7h82eDpaLTrtdmd32QrS2yyhL wLUw== X-Gm-Message-State: ANhLgQ3uXlKCXyH3G++DlxG17huobZdvjWtkcUYPs1Umb5ht8FYWvrag qn+Vl3PSRftILT4n6eCX3oHP5UeuQN437A== X-Google-Smtp-Source: ADFU+vs38FBZZSCj9+6smHd0ATdQoqRmPNGhcWNXQSD7Kfvf3f3wEG9Ek773NqFt1zZ8Io/aiZz6dg== X-Received: by 2002:a1c:a1c2:: with SMTP id k185mr1542331wme.164.1583425885107; Thu, 05 Mar 2020 08:31:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/37] target/arm: Honor the HCR_EL2.TSW bit Date: Thu, 5 Mar 2020 16:30:44 +0000 Message-Id: <20200305163100.22912-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200305163100.22912-1-peter.maydell@linaro.org> References: <20200305163100.22912-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::333 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson These bits trap EL1 access to set/way cache maintenance insns. Buglink: https://bugs.launchpad.net/bugs/1863685 Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200229012811.24129-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 22 ++++++++++++++++------ 1 file changed, 16 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c78429bca2a..feb279f44e9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -543,6 +543,16 @@ static CPAccessResult access_tvm_trvm(CPUARMState *env= , const ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +/* Check for traps from EL1 due to HCR_EL2.TSW. */ +static CPAccessResult access_tsw(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TSW)) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} + static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) { ARMCPU *cpu =3D env_archcpu(env); @@ -4704,14 +4714,14 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .access =3D PL1_W, .type =3D ARM_CP_NOP }, { .name =3D "DC_ISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, { .name =3D "DC_CVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, .accessfn =3D aa64_cacheop_access }, { .name =3D "DC_CSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, { .name =3D "DC_CVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 11, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, @@ -4722,7 +4732,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .accessfn =3D aa64_cacheop_access }, { .name =3D "DC_CISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, /* TLBI operations */ { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, @@ -4903,17 +4913,17 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6= , .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, = .opc2 =3D 2, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DCCMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 0, .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCCSW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 10,= .opc2 =3D 2, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DCCMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 1, .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D = 14, .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 14= , .opc2 =3D 2, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, /* MMU Domain access control / MPU write buffer control */ { .name =3D "DACR", .cp =3D 15, .opc1 =3D 0, .crn =3D 3, .crm =3D 0, .= opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .resetvalue =3D 0, --=20 2.20.1