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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w22sm10310729wmk.34.2020.03.05.08.31.22 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2020 08:31:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=MW1rCYSxw/00/8UqyAWlM8p39wC7z3ywPKWBwwkAIIw=; b=SvYRjwQMuJ7YMXKczNzyHuM+VA7OdTkL91JrLcRkXS/lCvBDTd7m+ybrETAWX+imX1 v3pMa/VH64zjfvAMNOvmzCd13buRAghiYowP09cTX3f/nBbUTOAexaQlyq1X9NLkNcZ8 a2rIdSukSIbrUJUlHnwdE3QwLI3YBDG+JI3YrLA84QqPxa3g9HhxJNxT2K321ob1z/dv qqkL5FlWPvpNv1O+WdRaJXyDeYT+rLOx4V/K/r/Yn6BNINUCK4Z4u2m2iXYN8EYBSPzp szjE/PmxHtCRHtasnF7syoVMciLcN8F/JT5RaDhATLjIlZfTmBmCuHY2iBalFWThFlsc luuw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MW1rCYSxw/00/8UqyAWlM8p39wC7z3ywPKWBwwkAIIw=; b=HuUp+HDSfQi+4uMPWHcLeuYe4ZPQjYpHsiqjcbKTNKo/Lq91372smQ690rYeBWjZOO KBBf/yZ4DzgHEAkajQVNeIJxpJ85b3HALuMA4QCaigIfMTNPjYfBHO8jHrlxlo+kHaTp 6VDGmVg7YgP+gqTtlnU4BN5eK3Ck+tUomMr2fBfhGHkDMDSXbv18k9WeU++0mOnmdRJe 4yHGtyw5YH77NxOhxP+d9Mf7Fvx3SU6pS4cDlzHrknNP8Q1VJ0x8o4dskADtMVp/ymeC Xc8GaeZTP0QfwKL2LRcSbl3coPdNrjcP1BCecMqGtA8i1XrTuby8RspVs0Jguj19JW3l hZPw== X-Gm-Message-State: ANhLgQ0yqAcFPT4iBq6Uvb7FYEA14aUVr305251UXAqX93BGy0fCH6xC t5+6/OQa5qdrWuIlmrx/O3Hfa/Jg8fVCqw== X-Google-Smtp-Source: ADFU+vtKQcHQbnwWhTvZ2FIMsmPD5od9K+iwwIxWf8j9nXh7dozc6vWOamgKEEDFm+UpfCHkwZiBFQ== X-Received: by 2002:a1c:4b0d:: with SMTP id y13mr10710328wma.4.1583425882945; Thu, 05 Mar 2020 08:31:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/37] target/arm: Improve masking in arm_hcr_el2_eff Date: Thu, 5 Mar 2020 16:30:42 +0000 Message-Id: <20200305163100.22912-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200305163100.22912-1-peter.maydell@linaro.org> References: <20200305163100.22912-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Update the {TGE,E2H} =3D=3D '11' masking to ARMv8.6. If EL2 is configured for aarch32, disable all of the bits that are RES0 in aarch32 mode. Signed-off-by: Richard Henderson Message-id: 20200229012811.24129-6-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 31 +++++++++++++++++++++++++++---- 1 file changed, 27 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 19a8be84938..4ddb9443fbc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5196,14 +5196,37 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) * Since the v8.4 language applies to the entire register, and * appears to be backward compatible, use that. */ - ret =3D 0; - } else if (ret & HCR_TGE) { - /* These bits are up-to-date as of ARMv8.4. */ + return 0; + } + + /* + * For a cpu that supports both aarch64 and aarch32, we can set bits + * in HCR_EL2 (e.g. via EL3) that are RES0 when we enter EL2 as aa32. + * Ignore all of the bits in HCR+HCR2 that are not valid for aarch32. + */ + if (!arm_el_is_aa64(env, 2)) { + uint64_t aa32_valid; + + /* + * These bits are up-to-date as of ARMv8.6. + * For HCR, it's easiest to list just the 2 bits that are invalid. + * For HCR2, list those that are valid. + */ + aa32_valid =3D MAKE_64BIT_MASK(0, 32) & ~(HCR_RW | HCR_TDZ); + aa32_valid |=3D (HCR_CD | HCR_ID | HCR_TERR | HCR_TEA | HCR_MIOCNC= E | + HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_TTLBIS); + ret &=3D aa32_valid; + } + + if (ret & HCR_TGE) { + /* These bits are up-to-date as of ARMv8.6. */ if (ret & HCR_E2H) { ret &=3D ~(HCR_VM | HCR_FMO | HCR_IMO | HCR_AMO | HCR_BSU_MASK | HCR_DC | HCR_TWI | HCR_TWE | HCR_TID0 | HCR_TID2 | HCR_TPCP | HCR_TPU | - HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE); + HCR_TDZ | HCR_CD | HCR_ID | HCR_MIOCNCE | + HCR_TID4 | HCR_TICAB | HCR_TOCU | HCR_ENSCXT | + HCR_TTLBIS | HCR_TTLBOS | HCR_TID5); } else { ret |=3D HCR_FMO | HCR_IMO | HCR_AMO; } --=20 2.20.1