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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id w22sm10310729wmk.34.2020.03.05.08.31.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Mar 2020 08:31:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Jjemy7ru1k2oXG98tCmpSClPpvqk/pa1WkziMWFO4pU=; b=l2Nq4rUag5eksIE9FNjjNSH0/zgz19Yps3MckrIF0WOYepXzSXYpsVzRL1ECt7Uia1 S1K7FvYW1RyTZ4UCzBf1sO0/u2twcOH7x53gGp3b5pmrT8bpf5+OljKSq7I0Z2bBlgn5 lbHwCcP6u7Y1hT7ZIB96lpSzUOvVnJE4qssD7hIa4JsKXEleTbvOmhJg6c3xYFn2J07d 1JXh+liXTyN3net1z8AY+JFPV0Hmqm96of+7GJptyHvTMfM5NtlXkY5CPLRJ48f0trSU VZ1P1JOIpdol+7Nzj8dfZRfVhWL8dFvQMENMLAN7UyLhdtLyuM5r0L5NYwUaKP0YZQdU cgwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Jjemy7ru1k2oXG98tCmpSClPpvqk/pa1WkziMWFO4pU=; b=lkfbp0s4UfPQ52wyYqHJymezno34saHjCJ+o1FY1wFXDs2lZITmqEz/Wh2q2NxS1aG XMmGrPR/C0wlmIMYVhUeMMiV0H72n4Dw1SydgI7TE6u2YkdRqc6Xo9o7gJlRFH6Aho3U A7gn5h6/fp6UN6jOehkYbl5ah2MYHu33arORaMOxlQB2gaUxJ1mn3zKof8sTu/jLlsO3 apnEXroWnd6+KmjhM/13wsTizF+8Eq1gTRHIQb5O5XO55jPA6ju0dt/9AeBSwWg3hkc7 k/OCrwroZOLId8IF0xBvBvhspVKgE57iwNE5Emqhb1r8XDN/A0hZvvhP1Oqg7+h2X6uk ayfA== X-Gm-Message-State: ANhLgQ25EODcPNLB21HhRMk8rvS38m7LeFvsfSE5cH7U5bFb50mAj3YS wUHZ1osbXx99pAXngm6NGCcXuGi90rtaWg== X-Google-Smtp-Source: ADFU+vtU2tNg7s2yWk4TaimOcYSVNl5gbit1/HW083kNmwiXoQe/enQVBUqrhrqOzfXToyyAQV4qWw== X-Received: by 2002:a5d:4484:: with SMTP id j4mr11935691wrq.153.1583425880918; Thu, 05 Mar 2020 08:31:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/37] target/arm: Disable has_el2 and has_el3 for user-only Date: Thu, 5 Mar 2020 16:30:40 +0000 Message-Id: <20200305163100.22912-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200305163100.22912-1-peter.maydell@linaro.org> References: <20200305163100.22912-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson In arm_cpu_reset, we configure many system registers so that user-only behaves as it should with a minimum of ifdefs. However, we do not set all of the system registers as required for a cpu with EL2 and EL3. Disabling EL2 and EL3 mean that we will not look at those registers, which means that we don't have to worry about configuring them. Signed-off-by: Richard Henderson Message-id: 20200229012811.24129-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index de00a45e903..185a46f5abd 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1103,11 +1103,13 @@ static Property arm_cpu_reset_hivecs_property =3D static Property arm_cpu_rvbar_property =3D DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); =20 +#ifndef CONFIG_USER_ONLY static Property arm_cpu_has_el2_property =3D DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); =20 static Property arm_cpu_has_el3_property =3D DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); +#endif =20 static Property arm_cpu_cfgend_property =3D DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); @@ -1222,25 +1224,25 @@ void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); } =20 +#ifndef CONFIG_USER_ONLY if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { /* Add the has_el3 state CPU property only if EL3 is allowed. Thi= s will * prevent "has_el3" from existing on CPUs which cannot support EL= 3. */ qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); =20 -#ifndef CONFIG_USER_ONLY object_property_add_link(obj, "secure-memory", TYPE_MEMORY_REGION, (Object **)&cpu->secure_memory, qdev_prop_allow_set_link_before_realize, OBJ_PROP_LINK_STRONG, &error_abort); -#endif } =20 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); } +#endif =20 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { cpu->has_pmu =3D true; --=20 2.20.1