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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id s18sm99510pjp.24.2020.03.02.09.58.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Mar 2020 09:58:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Xb4MZkBU7c3SsPvbbpOINi23WCHWKuPEyPWHI7rJrJg=; b=lzo2x0RUxzilhpgFVTN4QYmyqJjuqg1RBfGHJzW9ioWN2CpVjgwp/jz/psxx9r+m/2 rdPP2kEKvlq2CfqxQAWsYlAZQUP4AE6HJYBS3dOSu1pfEDMhMQdITg/SjJG3TuuWQRYn fAun+xHZNpHxWDep7FcS8owD75Wn0VDVMau4w2c1nM+Lvw1xOI3NVMaiRKTk3lti1hJ5 BaphvzV1T5ZuuYLC5wWPDWQhm8hvf2/pHshDIVIW6Qedcfhs2NB4wzgNFfgRc22T4kF5 cyucm2PRyh8xygFz8amS86X7NP4+reSephwQs36H/X4zDMo4BFGwjpr2kSK/63PCHUDe TExw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Xb4MZkBU7c3SsPvbbpOINi23WCHWKuPEyPWHI7rJrJg=; b=PXi1+sFGhetszmkVrVRdRy3VQHvE2NR5SJO7Z1qaAAVZSDkURgqzMgvq2M/s+mWoO4 EsHjWkyBjMFgnQxwAHJCqWd2zxhodD+V+Yj59Cyx76Af5KN6fHOojBn5M6UxcWPcxu6X Bdgi2HnxbXv3MdKAn6VC1E9UPunK3uox0JIl/+4gsmRaWwt8IJcK1aOMMbVrWjf9j6Y/ YicjF7uE9BGHZsg28WOPkaSUBhn1bNaUswxhy+kkn1NgJztgJHfhApK5zX/+KTtBpRa/ 9zMa2GEUnr08tRTbgtUCKByko9nw3OAJ2yg0lwT5j+Jb7nVU8aLh3tMaGuRpxx3Ogqa9 kQhw== X-Gm-Message-State: ANhLgQ0uS7xkYWjtopZE6Coj7i5/1vHeMyARKm06FEOsMogZUTgIeT8O EHFchbnx3oiumFduLAB5w1o68L9Ag+s= X-Google-Smtp-Source: ADFU+vv3iLnhNolBrBcjQO8XIq71zVeXC+xGHZfKtv6ij3AFnORcPkH6C1HduiYU52RbaGJCGS0tYg== X-Received: by 2002:a63:d0b:: with SMTP id c11mr103192pgl.296.1583171916269; Mon, 02 Mar 2020 09:58:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 4/9] target/arm: Apply TBI to ESR_ELx in helper_exception_return Date: Mon, 2 Mar 2020 09:58:24 -0800 Message-Id: <20200302175829.2183-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200302175829.2183-1-richard.henderson@linaro.org> References: <20200302175829.2183-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We missed this case within AArch64.ExceptionReturn. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper-a64.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 509ae93069..123ce50e7a 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -1031,6 +1031,8 @@ void HELPER(exception_return)(CPUARMState *env, uint6= 4_t new_pc) "AArch32 EL%d PC 0x%" PRIx32 "\n", cur_el, new_el, env->regs[15]); } else { + int tbii; + env->aarch64 =3D 1; spsr &=3D aarch64_pstate_valid_mask(&env_archcpu(env)->isar); pstate_write(env, spsr); @@ -1038,8 +1040,27 @@ void HELPER(exception_return)(CPUARMState *env, uint= 64_t new_pc) env->pstate &=3D ~PSTATE_SS; } aarch64_restore_sp(env, new_el); - env->pc =3D new_pc; helper_rebuild_hflags_a64(env, new_el); + + /* + * Apply TBI to the exception return address. We had to delay this + * until after we selected the new EL, so that we could select the + * correct TBI+TBID bits. This is made easier by waiting until af= ter + * the hflags rebuild, since we can pull the composite TBII field + * from there. + */ + tbii =3D FIELD_EX32(env->hflags, TBFLAG_A64, TBII); + if ((tbii >> extract64(new_pc, 55, 1)) & 1) { + /* TBI is enabled. */ + int core_mmu_idx =3D cpu_mmu_index(env, false); + if (regime_has_2_ranges(core_to_aa64_mmu_idx(core_mmu_idx))) { + new_pc =3D sextract64(new_pc, 0, 56); + } else { + new_pc =3D extract64(new_pc, 0, 56); + } + } + env->pc =3D new_pc; + qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch64 EL%d PC 0x%" PRIx64 "\n", cur_el, new_el, env->pc); --=20 2.20.1