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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id r3sm4606313pfq.126.2020.02.28.17.28.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 17:28:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QpMHNZIbcT5PzqjajR8IDp8eTMJQTzdyuvxjhrMoYDc=; b=YY2Mz0sznUyzLkAu1ttdhi9ccja2VcdZ72zNGleYvo831HwzPkcs197oPmgr6em6O2 LZJH/O75OrxN2+rDi1nF+8SgvkWTYd5qQpCArvjePBcriTVbzyLidObarP1f4M1+jcn/ Y6PhNuae4pAmb56QmYcCVgpy7FzESM3dM7H5LCOStgueezcuczF2mTSszdceXTpUlYN1 LeupHVsARLhHvRKtTZ7P8LZBoszOakQUg1se3av9J4n95a3xHEMB3joKVLtdQuyH8A+G 3ED8dUat1+2kN1KLcCFtppx8Jf7p7OxzaZqbTqTQWkMOhCRtjuYNG4ZShvVPj+hlc5K0 EXxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QpMHNZIbcT5PzqjajR8IDp8eTMJQTzdyuvxjhrMoYDc=; b=ZNG2fZUWQUIwRKUd2HhY9gdr9ZJhfzd+4tEyl6TnK6jt0G1mosDHsi0xQmtIStzGTJ C7tdOtsDhy0W5sMvfIdxtUjP4gvqiTgrumNqSuqfP7720TSCuiqnu0Ya2WQpQRhR84KT D6TKcytVX1p+/WAaIhQmjbQZLHA9KXcYTR6pwSNEm/mPEJPZP51M1T+Uk9lTWz909JlX TInLYOlfaK3q/JRP45gU8VoXffNk9bmTDDiPjDNQPPRRQqcIr5WSa4SdRlPu2K912Ynx lVmukTpn8wSxqNSBBAe/ts6AiqMh3UpF10rCBqr80LCbRFkad9rUY/VpyVsAK++7oq7m +mCw== X-Gm-Message-State: APjAAAVrzDhwCKKwm9RT5mNM47xm0eCAZAJfsI3YOFeq7VUINDw+EyGn 9jZpPchHb1gVHSmR+a7ekBZWKlcy4kU= X-Google-Smtp-Source: APXvYqwkCjGMdstyhYyogHKj1DoGDKawMt7g65hy7zFiuS6OCr+vn78moluMw3RJ/Ct23OF2b8DJXw== X-Received: by 2002:a17:90b:243:: with SMTP id fz3mr7826522pjb.29.1582939698546; Fri, 28 Feb 2020 17:28:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 03/12] target/arm: Disable has_el2 and has_el3 for user-only Date: Fri, 28 Feb 2020 17:28:02 -0800 Message-Id: <20200229012811.24129-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200229012811.24129-1-richard.henderson@linaro.org> References: <20200229012811.24129-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In arm_cpu_reset, we configure many system registers so that user-only behaves as it should with a minimum of ifdefs. However, we do not set all of the system registers as required for a cpu with EL2 and EL3. Disabling EL2 and EL3 mean that we will not look at those registers, which means that we don't have to worry about configuring them. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e6016e33ce..33c28fe868 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1103,11 +1103,13 @@ static Property arm_cpu_reset_hivecs_property =3D static Property arm_cpu_rvbar_property =3D DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0); =20 +#ifndef CONFIG_USER_ONLY static Property arm_cpu_has_el2_property =3D DEFINE_PROP_BOOL("has_el2", ARMCPU, has_el2, true); =20 static Property arm_cpu_has_el3_property =3D DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true); +#endif =20 static Property arm_cpu_cfgend_property =3D DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false); @@ -1222,25 +1224,25 @@ void arm_cpu_post_init(Object *obj) qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property); } =20 +#ifndef CONFIG_USER_ONLY if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) { /* Add the has_el3 state CPU property only if EL3 is allowed. Thi= s will * prevent "has_el3" from existing on CPUs which cannot support EL= 3. */ qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property); =20 -#ifndef CONFIG_USER_ONLY object_property_add_link(obj, "secure-memory", TYPE_MEMORY_REGION, (Object **)&cpu->secure_memory, qdev_prop_allow_set_link_before_realize, OBJ_PROP_LINK_STRONG, &error_abort); -#endif } =20 if (arm_feature(&cpu->env, ARM_FEATURE_EL2)) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el2_property); } +#endif =20 if (arm_feature(&cpu->env, ARM_FEATURE_PMU)) { cpu->has_pmu =3D true; --=20 2.20.1