From nobody Thu Dec 18 22:22:57 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908112; cv=none; d=zohomail.com; s=zohoarc; b=lCuu+9X7oYao3Y5LEempd+Z8bDX7d80a5SRCdvbzy5pMOSwrawopW40BcMdaQ8J7RYpcyPDWLvScQK/iYXMhK2t7y3QydNEjwthOep0fEGE3QoEtkzpy1cf2igmn/z4ayKuTvkF4wpn+je64oai0VwjPYQpZtHp0W2n4PF/5gbc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908112; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XwFayHGAlgtbTjyBRhE/jLwf5sdkAmef4Kxh8ptCpD4=; b=S3lbVpfYQsYyoSFtFGRFuHCotnvkGU4x/J8e1sGNxH9hK6KNXs5gyRRWQWVxk/O7I4psoBQiWpqLpYhGG3xEfD7MBONhMmtsRHTOLVqJpZhfPy8jXCmRXnqJ75b0pXnfI+EKws+H48qgLa2JivGSAiwYcl8hYjmETypn+ZwFfAA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908112330226.2880478088465; Fri, 28 Feb 2020 08:41:52 -0800 (PST) Received: from localhost ([::1]:50206 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ihz-0004UZ-1W for importer@patchew.org; Fri, 28 Feb 2020 11:41:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56449) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7if8-0007J6-6c for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7if6-0001pV-AC for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:54 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:53371) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7if6-0001ow-2u for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:52 -0500 Received: by mail-wm1-x32d.google.com with SMTP id f15so3835251wml.3 for ; Fri, 28 Feb 2020 08:38:52 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.38.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:38:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XwFayHGAlgtbTjyBRhE/jLwf5sdkAmef4Kxh8ptCpD4=; b=CfU9YQtP8xBdClxjEp3azxpFYBaJW7FVffYGR2yLnHzgH2JFDSaTki10YoBSfy9wd3 z0aG2844lAarA2J5HOi0NIigYlOMvmkKx08FLHd2v0SLY8Y1eRQ6c2P2Ep0NdsowMmbl PhTBCSG+WZM2HHykTMpf43naxGqtT3nePbdxZ4fP3LS7PsqywvBnGATNkLMT2yoGMS9Z eZmQYQ5Eq80Mxj+fNQYCLayjMaL7BOIxNZ6ggCqFYagBG4Kj0O46DmTqN7fkG7ZuGGDb 84AJQHAgYlSCAhv5/V2PlAQw6yyMc1GBrkORj7W1ilteLZSrXzzG8fNvaO4VQA+LpXi/ +gIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XwFayHGAlgtbTjyBRhE/jLwf5sdkAmef4Kxh8ptCpD4=; b=i90K9lUTfKI+zwKQw8zE1nBdOYA7dVnIvdGHUYNa6hFvm4wfudDPfxK5wrvHiEz8Gr qSudxuK76AINCGVzDsKnfvpbm3tkd3n65Id71GYGQwggXk7CUM690U94Dv+uDFI/AkLG g/BR/3T0bR1T7fF6VZVwCJvJzl/ezyC/uD/mtMeuA3kETz2Y3fy9XQd3Wmlj0gmDT5wp 4wr+V4iqq008an6JBkqRMw05WESwyZIvwYVbAvxJviVvW/KMwoUArGi6CkNxBYfSakFQ LaI7X0oy/jwL8ccpr6Qf2FoRuXVnk48SvgJl5Mh6A0fPDp9p5nWoZqPyptrcApLJ8s8s u3wA== X-Gm-Message-State: APjAAAUrCJkhZxX+FuP1RE5HaHDcF/wDgGKaWicKRCYhW+E/W01mWnJs bSGmnjylutYJQW3xRebMkvq3/wQgCs0aSA== X-Google-Smtp-Source: APXvYqyOxe8+mDcSccIGhTxKMzzBCVpwg0Y9ev9lYOgQ1vZCeLsUxXSZzIAiMq7anBOilekePoUbJQ== X-Received: by 2002:a1c:e908:: with SMTP id q8mr1204180wmc.77.1582907930547; Fri, 28 Feb 2020 08:38:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/33] target/arm: Add isar_feature_aa32_vfp_simd Date: Fri, 28 Feb 2020 16:38:14 +0000 Message-Id: <20200228163840.23585-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use this in the places that were checking ARM_FEATURE_VFP, and are obviously testing for the existance of the register set as opposed to testing for some particular instruction extension. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20200224222232.13807-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 9 +++++++++ hw/intc/armv7m_nvic.c | 20 ++++++++++---------- linux-user/arm/signal.c | 4 ++-- target/arm/arch_dump.c | 11 ++++++----- target/arm/cpu.c | 4 ++-- target/arm/helper.c | 4 ++-- target/arm/m_helper.c | 11 ++++++----- 7 files changed, 37 insertions(+), 26 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 65171cb30ee..a128d48d405 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3450,6 +3450,15 @@ static inline bool isar_feature_aa32_fp16_arith(cons= t ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) =3D=3D 1; } =20 +static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) +{ + /* + * Return true if either VFP or SIMD is implemented. + * In this case, a minimum of VFP w/ D0-D15. + */ + return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; +} + static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) { /* Return true if D16-D31 are implemented */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 22a43e49847..a62587eb3f0 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1262,12 +1262,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) case 0xd84: /* CSSELR */ return cpu->env.v7m.csselr[attrs.secure]; case 0xd88: /* CPACR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } return cpu->env.v7m.cpacr[attrs.secure]; case 0xd8c: /* NSACR */ - if (!attrs.secure || !arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!attrs.secure || !cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } return cpu->env.v7m.nsacr; @@ -1417,7 +1417,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) } return cpu->env.v7m.sfar; case 0xf34: /* FPCCR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } if (attrs.secure) { @@ -1444,12 +1444,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) return value; } case 0xf38: /* FPCAR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } return cpu->env.v7m.fpcar[attrs.secure]; case 0xf3c: /* FPDSCR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } return cpu->env.v7m.fpdscr[attrs.secure]; @@ -1711,13 +1711,13 @@ static void nvic_writel(NVICState *s, uint32_t offs= et, uint32_t value, } break; case 0xd88: /* CPACR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { /* We implement only the Floating Point extension's CP10/CP11 = */ cpu->env.v7m.cpacr[attrs.secure] =3D value & (0xf << 20); } break; case 0xd8c: /* NSACR */ - if (attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (attrs.secure && cpu_isar_feature(aa32_vfp_simd, cpu)) { /* We implement only the Floating Point extension's CP10/CP11 = */ cpu->env.v7m.nsacr =3D value & (3 << 10); } @@ -1951,7 +1951,7 @@ static void nvic_writel(NVICState *s, uint32_t offset= , uint32_t value, break; } case 0xf34: /* FPCCR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { /* Not all bits here are banked. */ uint32_t fpccr_s; =20 @@ -2005,13 +2005,13 @@ static void nvic_writel(NVICState *s, uint32_t offs= et, uint32_t value, } break; case 0xf38: /* FPCAR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { value &=3D ~7; cpu->env.v7m.fpcar[attrs.secure] =3D value; } break; case 0xf3c: /* FPDSCR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { value &=3D 0x07c00000; cpu->env.v7m.fpdscr[attrs.secure] =3D value; } diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c index b0e753801b6..d96fc27ce11 100644 --- a/linux-user/arm/signal.c +++ b/linux-user/arm/signal.c @@ -346,7 +346,7 @@ static void setup_sigframe_v2(struct target_ucontext_v2= *uc, setup_sigcontext(&uc->tuc_mcontext, env, set->sig[0]); /* Save coprocessor signal frame. */ regspace =3D uc->tuc_regspace; - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { regspace =3D setup_sigframe_v2_vfp(regspace, env); } if (arm_feature(env, ARM_FEATURE_IWMMXT)) { @@ -671,7 +671,7 @@ static int do_sigframe_return_v2(CPUARMState *env, =20 /* Restore coprocessor signal frame */ regspace =3D uc->tuc_regspace; - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { regspace =3D restore_sigframe_v2_vfp(env, regspace); if (!regspace) { return 1; diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 2345dec3c2c..7693e17e964 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -363,9 +363,11 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, = CPUState *cs, int cpuid, void *opaque) { struct arm_note note; - CPUARMState *env =3D &ARM_CPU(cs)->env; + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; DumpState *s =3D opaque; - int ret, i, fpvalid =3D !!arm_feature(env, ARM_FEATURE_VFP); + int ret, i; + bool fpvalid =3D cpu_isar_feature(aa32_vfp_simd, cpu); =20 arm_note_init(¬e, s, "CORE", 5, NT_PRSTATUS, sizeof(note.prstatus)); =20 @@ -444,7 +446,6 @@ int cpu_get_dump_info(ArchDumpInfo *info, ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) { ARMCPU *cpu =3D ARM_CPU(first_cpu); - CPUARMState *env =3D &cpu->env; size_t note_size; =20 if (class =3D=3D ELFCLASS64) { @@ -452,12 +453,12 @@ ssize_t cpu_get_note_size(int class, int machine, int= nr_cpus) note_size +=3D AARCH64_PRFPREG_NOTE_SIZE; #ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_sve, cpu)) { - note_size +=3D AARCH64_SVE_NOTE_SIZE(env); + note_size +=3D AARCH64_SVE_NOTE_SIZE(&cpu->env); } #endif } else { note_size =3D ARM_PRSTATUS_NOTE_SIZE; - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { note_size +=3D ARM_VFP_NOTE_SIZE; } } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2eadf4dcb8b..be4c2a1253d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -293,7 +293,7 @@ static void arm_cpu_reset(CPUState *s) env->v7m.ccr[M_REG_S] |=3D R_V7M_CCR_UNALIGN_TRP_MASK; } =20 - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { env->v7m.fpccr[M_REG_NS] =3D R_V7M_FPCCR_ASPEN_MASK; env->v7m.fpccr[M_REG_S] =3D R_V7M_FPCCR_ASPEN_MASK | R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; @@ -1011,7 +1011,7 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f,= int flags) int numvfpregs =3D 0; if (cpu_isar_feature(aa32_simd_r32, cpu)) { numvfpregs =3D 32; - } else if (arm_feature(env, ARM_FEATURE_VFP)) { + } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { numvfpregs =3D 16; } for (i =3D 0; i < numvfpregs; i++) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 79db169e046..8841cc7fde8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -894,7 +894,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. * TRCDIS [28] is RAZ/WI since we do not implement a trace macroce= ll. */ - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { /* VFP coprocessor: cp10 & cp11 [23:20] */ mask |=3D (1 << 31) | (1 << 30) | (0xf << 20); =20 @@ -7814,7 +7814,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 35, "arm-vfp3.xml", 0); - } else if (arm_feature(env, ARM_FEATURE_VFP)) { + } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 19, "arm-vfp.xml", 0); } diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 33d414a684b..5e8a795d202 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -738,7 +738,8 @@ static uint32_t v7m_integrity_sig(CPUARMState *env, uin= t32_t lr) */ uint32_t sig =3D 0xfefa125a; =20 - if (!arm_feature(env, ARM_FEATURE_VFP) || (lr & R_V7M_EXCRET_FTYPE_MAS= K)) { + if (!cpu_isar_feature(aa32_vfp_simd, env_archcpu(env)) + || (lr & R_V7M_EXCRET_FTYPE_MASK)) { sig |=3D 1; } return sig; @@ -841,7 +842,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t l= r, bool dotailchain, =20 if (dotailchain) { /* Sanitize LR FType and PREFIX bits */ - if (!arm_feature(env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { lr |=3D R_V7M_EXCRET_FTYPE_MASK; } lr =3D deposit32(lr, 24, 8, 0xff); @@ -1373,7 +1374,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) =20 ftype =3D excret & R_V7M_EXCRET_FTYPE_MASK; =20 - if (!arm_feature(env, ARM_FEATURE_VFP) && !ftype) { + if (!ftype && !cpu_isar_feature(aa32_vfp_simd, cpu)) { qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception= " "exit PC value 0x%" PRIx32 " is UNPREDICTABLE " "if FPU not present\n", @@ -2450,7 +2451,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskr= eg, uint32_t val) * SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 =3D=3D 0, * RES0 if the FPU is not present, and is stored in the S bank */ - if (arm_feature(env, ARM_FEATURE_VFP) && + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env)) && extract32(env->v7m.nsacr, 10, 1)) { env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_FPCA_MASK; env->v7m.control[M_REG_S] |=3D val & R_V7M_CONTROL_FPCA_MA= SK; @@ -2565,7 +2566,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskr= eg, uint32_t val) env->v7m.control[env->v7m.secure] &=3D ~R_V7M_CONTROL_NPRIV_MA= SK; env->v7m.control[env->v7m.secure] |=3D val & R_V7M_CONTROL_NPR= IV_MASK; } - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { /* * SFPA is RAZ/WI from NS or if no FPU. * FPCA is RO if NSACR.CP10 =3D=3D 0, RES0 if the FPU is not p= resent. --=20 2.20.1