From nobody Fri Dec 19 04:32:24 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908477; cv=none; d=zohomail.com; s=zohoarc; b=Qlx2aJquv7viDJkZ7WfH803VkCDyz8KgTlk8wTdSYpbREGgJoTtJxut9M0jBD8S/bGSlgd4aZBjbxPV5O69mIw08vW3naiMAv1xHBxgJwC1k6SBvyfzIWglA1s8iTB2b36xhxUw9ufJCcFMGVcbumSOXrfFakTmoaeyg2TFuFmg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908477; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5oQ35QsMhetApJIHGz3Rua7oGdC5Wob+G0lA1+c8/Fw=; b=QtjlEVj9JEbZFfJ0czdMwA0raOOdaZ0/pVnpDpkoMkh0775xqmpcz+oKt+Z/mLRyPuotlAu4uLHY9dv7srtCMxSYoybSvt20tSBl6qucBYnmM5yhUpQ9IICLeu4/hJdYvDkh3TiA7BkiGPVY9693RVPl7QESJyJsDEACm4Y38b8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158290847720992.54239972113157; Fri, 28 Feb 2020 08:47:57 -0800 (PST) Received: from localhost ([::1]:50534 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7inr-0007pY-T3 for importer@patchew.org; Fri, 28 Feb 2020 11:47:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56791) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifZ-0008NU-O9 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifY-00028I-9A for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:21 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:40817) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifY-00027p-2c for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:20 -0500 Received: by mail-wm1-x342.google.com with SMTP id d138so2304968wmd.5 for ; Fri, 28 Feb 2020 08:39:20 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.39.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:39:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=5oQ35QsMhetApJIHGz3Rua7oGdC5Wob+G0lA1+c8/Fw=; b=SCghQKzZ0n5jys0ixaZ7beD5qPwkCXiQKVoGJ20dZ5/0G+sizZg5xvKWaLmkkll2DB OFyHBjEJN5jqdG6kY4xVjH4D+1qulKIG2c2ywWSlLw1v7iKRRHk0CYQZVOaJlEzU6Q7C XfaIOZQxTrVnqnl5w3Ul2X79GXh5PnbrTzVqkX1g58JuTTuM2YhXvjzgusSVCtmzr+4W VFaz8BirU53/Hm5OxGictG37WLGgy6aLycahac4zrkM67slOmV9pzh0x5dmujhbCQTQp w0xjAIXJeRTdKjTbxAo1qtPUr7AHjjpP7VyBnHGgnZhTJeKhofrOAAuw1lPsd3AZgc+Y XsBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5oQ35QsMhetApJIHGz3Rua7oGdC5Wob+G0lA1+c8/Fw=; b=hIWZkcYPHU13m+4CmSvH7MOcR2+oesCfqMuxl5aSZoJgdbQSzcmDXiEo9TnVEDMxXo BDEUN2baF+wyFLurA0sjkA1ttObXRc7SOlJTFfSe5zXUqlTgJwNC9hawr2IC2ujsgBLd JR6b4w0OHkNS64EAbYUTNoR2BmjAjJHdvW8UVFVj8Fhm+dv/UYpGf6/0D6fCeBxAKw9n sisoxa5NHkx5WkAa/bAUNEW0BAhuJW1IPnZY5ndmcmIvEG2UzvC7pN8XO7MNCFyOglHS +NqA7Yq4qojU0py0wCHM1rOpwsqxx2LVz9a+gRmjQ6CWvQAfMrh6a88zDTHjq1/wpjFl qxhw== X-Gm-Message-State: APjAAAXFfCQTbmPbTFFZCUMdTti9PbwU09m2wV8B9AKfUntP/a4LRJ/a jTOtA5Hp/Q8J3FokFD8VjhVTykArWuBRKQ== X-Google-Smtp-Source: APXvYqzLA2MHcxBIs1BgVBXpU97gJfV1kBa/rD3UY91e4uu4953h+6GsBVgDgujcT+rAgcOPbfuj+A== X-Received: by 2002:a1c:750f:: with SMTP id o15mr5708199wmc.111.1582907958750; Fri, 28 Feb 2020 08:39:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/33] target/arm: Implement ARMv8.3-CCIDX Date: Fri, 28 Feb 2020 16:38:39 +0000 Message-Id: <20200228163840.23585-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The ARMv8.3-CCIDX extension makes the CCSIDR_EL1 system ID registers have a format that uses the full 64 bit width of the register, and adds a new CCSIDR2 register so AArch32 can get at the high 32 bits. QEMU doesn't implement caches, so we just treat these ID registers as opaque values that are set to the correct constant values for each CPU. The only thing we need to do is allow 64-bit values in our cssidr[] array and provide the CCSIDR2 accessors. We don't set the CCIDX field in our 'max' CPU because the CCSIDR constant values we use are the same as the ones used by the Cortex-A57 and they are in the old 32-bit format. This means that the extra regdef added here is unused currently, but it means that whenever in the future we add a CPU that does need the new 64-bit format it will just work when we set the cssidr values and the ID registers for it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200224182626.29252-1-peter.maydell@linaro.org --- target/arm/cpu.h | 17 ++++++++++++++++- target/arm/helper.c | 19 +++++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ce1e2a090e5..0b84742b66a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -904,7 +904,7 @@ struct ARMCPU { /* The elements of this array are the CCSIDR values for each cache, * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. */ - uint32_t ccsidr[16]; + uint64_t ccsidr[16]; uint64_t reset_cbar; uint32_t reset_auxcr; bool reset_hivecs; @@ -3577,6 +3577,11 @@ static inline bool isar_feature_aa32_ac2(const ARMIS= ARegisters *id) return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) !=3D 0; } =20 +static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) !=3D 0; +} + /* * 64-bit feature tests via id registers. */ @@ -3784,6 +3789,11 @@ static inline bool isar_feature_aa64_rcpc_8_4(const = ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >=3D 2; } =20 +static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) !=3D 0; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ @@ -3807,6 +3817,11 @@ static inline bool isar_feature_any_pmu_8_4(const AR= MISARegisters *id) return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); } =20 +static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) +{ + return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 8841cc7fde8..6be9ffa09ef 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6726,6 +6726,21 @@ static const ARMCPRegInfo predinv_reginfo[] =3D { REGINFO_SENTINEL }; =20 +static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* Read the high 32 bits of the current CCSIDR */ + return extract64(ccsidr_read(env, ri), 32, 32); +} + +static const ARMCPRegInfo ccsidr2_reginfo[] =3D { + { .name =3D "CCSIDR2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 2, + .access =3D PL1_R, + .accessfn =3D access_aa64_tid2, + .readfn =3D ccsidr2_read, .type =3D ARM_CP_NO_RAW }, + REGINFO_SENTINEL +}; + static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInf= o *ri, bool isread) { @@ -7788,6 +7803,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, predinv_reginfo); } =20 + if (cpu_isar_feature(any_ccidx, cpu)) { + define_arm_cp_regs(cpu, ccsidr2_reginfo); + } + #ifndef CONFIG_USER_ONLY /* * Register redirections and aliases must be done last, --=20 2.20.1