From nobody Thu Dec 18 22:25:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908181; cv=none; d=zohomail.com; s=zohoarc; b=Q84MRsBLIDSmUrUXLQHhC060Zol+DLirviDy95rs6GS2AIASS0QuyCZ1yLo2ervnI3zhJeaAQpGIbTXdAa4f5+wSU2pLcXeJxZFce95K8dU2ugzNBP/mw4EEjL1770cB/dhDGoIcMlqOlln6C7bioVNxTgdK0KxewQGiV34VVL8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908181; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jvv1988l+MhveUC13kevwwKHJA6IhCtxQBKlOzO9REg=; b=ASUBg+ynVNCNAKTFtkT06BTbLtYtHIGd8tbu3Wl24lbI93AiAJ46YHCydW9TTUrzJ+foL3jNlq9SY7q0bIQj8tlY8X90wLFauXMPb011AjQ6WBAUUFgzQAnf+u8OqZVx9KRDx8g6dnztLM1zBK9EWTOTyM+BUrH+QsWjlrw2Jjc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908181187102.45803898622171; Fri, 28 Feb 2020 08:43:01 -0800 (PST) Received: from localhost ([::1]:50248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ij6-0007Ui-06 for importer@patchew.org; Fri, 28 Feb 2020 11:43:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56544) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifG-0007aB-72 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifE-0001v1-RY for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:02 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:39224) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifE-0001uT-Kw for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:00 -0500 Received: by mail-wr1-x42d.google.com with SMTP id y17so3670815wrn.6 for ; Fri, 28 Feb 2020 08:39:00 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.38.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:38:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=jvv1988l+MhveUC13kevwwKHJA6IhCtxQBKlOzO9REg=; b=iO7pGM6vHbpoUcRx2yCWAvXtxsR4l+11Fh4bm0GhEjJDB7fO0MV35ukOqDlIAEWN+C tRgD1IGgp9gSek+qahQulVpuSLrAEuuituWPdz7BEOVoYxR5d+hd80Jwv7XLhdpKdQ76 8nMLlKY5ieXl6m+16HZWL2Fu0ZYIr1JGHGpGD/mxPLsiEY3Ydhi2lBbqephqgCg9QW3j soVZsQp5WVO37vHmWQJupkYQ8laknHNyvUgftHK8TH+B0gk8WFEqu8EJYqypzF9xQpOd tQc/bgDGTeqOkwo7Sf/1TPH4v/CF7A2VWsgGxSHRK1/LLTVWCsJeI9mtFj8hoKPZJGbm ly8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jvv1988l+MhveUC13kevwwKHJA6IhCtxQBKlOzO9REg=; b=sxUKMUp+ZCD8G5+8svLoD8AWtzIH7iJBlR2b0vKC2qOS+zrj28nahHV9aqf83HEJ1u RatO4KMrsmrN2B0+oy8Y0JlrrV/P6T1YG/NiNxcFIVzCfrLREVVYqbLMkXDcxXSQqIwZ VTaJyMY1vDmJw6XVFB9zSqmQ0Cv2IHHW8ie+LkmlhpYNEneOi8C3c+k8N+AazP+MM4tQ HqCvyJanbfU5bYzMXDmOGtmJKXnPem2QwrSOOKFq28ZFfmVlhjZa4mh/rlQNcE4VyD0+ BeD3XxwCwsOcpdZMlifrBrlEngR2V1r6+EuXcTVPW5h2rNKDkrBw8H4Vp8YCAI4+9CbY ULEA== X-Gm-Message-State: APjAAAUn7fjpbYPICV/UbJHkIIIDcDz+aUDQl0xgKklpjRRt1QIaFiMI EFK+yj46hIH7p2kY+JCg93Bhb7iaXVqTiw== X-Google-Smtp-Source: APXvYqzM7uROXKdlxY8Pczv1StD86gWuHdFMz4bPNrX3XcmXSJxMlUz7W2kypPrOKGx3Zx7ZbIQR3g== X-Received: by 2002:adf:f012:: with SMTP id j18mr5550390wro.314.1582907939349; Fri, 28 Feb 2020 08:38:59 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/33] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac Date: Fri, 28 Feb 2020 16:38:21 +0000 Message-Id: <20200228163840.23585-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson All remaining tests for VFP4 are for fused multiply-add insns. Since the MVFR1 field is used for both VFP and NEON, move its adjustment from the !has_neon block to the (!has_vfp && !has_neon) block. Test for vfp of the appropraite width alongside the test for simdfmac within translate-vfp.inc.c. Within disas_neon_data_insn, we have already tested for ARM_FEATURE_NEON. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20200224222232.13807-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 12 ++++++++++++ target/arm/cpu.c | 6 +++++- target/arm/translate-vfp.inc.c | 22 ++++++++++++++++++---- target/arm/translate.c | 2 +- 4 files changed, 36 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b94d2a5ace4..b29b0eddfc3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3514,6 +3514,18 @@ static inline bool isar_feature_aa32_fp16_dpconv(con= st ARMISARegisters *id) return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; } =20 +/* + * Note that this ID register field covers both VFP and Neon FMAC, + * so should usually be tested in combination with some other + * check that confirms the presence of whichever of VFP or Neon is + * relevant, to avoid accidentally enabling a Neon feature on + * a VFP-no-Neon core or vice-versa. + */ +static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) +{ + return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) !=3D 0; +} + static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) { return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 1; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5be4c258096..dc45865c7a7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1512,7 +1512,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) u =3D FIELD_DP32(u, MVFR1, SIMDINT, 0); u =3D FIELD_DP32(u, MVFR1, SIMDSP, 0); u =3D FIELD_DP32(u, MVFR1, SIMDHP, 0); - u =3D FIELD_DP32(u, MVFR1, SIMDFMAC, 0); cpu->isar.mvfr1 =3D u; =20 u =3D cpu->isar.mvfr2; @@ -1535,6 +1534,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) u =3D cpu->isar.mvfr0; u =3D FIELD_DP32(u, MVFR0, SIMDREG, 0); cpu->isar.mvfr0 =3D u; + + /* Despite the name, this field covers both VFP and Neon */ + u =3D cpu->isar.mvfr1; + u =3D FIELD_DP32(u, MVFR1, SIMDFMAC, 0); + cpu->isar.mvfr1 =3D u; } =20 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index f88a95438fc..03ba8d7aac0 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1803,11 +1803,18 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_s= p *a) =20 /* * Present in VFPv4 only. + * Note that we can't rely on the SIMDFMAC check alone, because + * in a Neon-no-VFP core that ID register field will be non-zero. + */ + if (!dc_isar_feature(aa32_simdfmac, s) || + !dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + /* * In v7A, UNPREDICTABLE with non-zero vector length/stride; from * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A. */ - if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || - (s->vec_len !=3D 0 || s->vec_stride !=3D 0)) { + if (s->vec_len !=3D 0 || s->vec_stride !=3D 0) { return false; } =20 @@ -1861,11 +1868,18 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_d= p *a) =20 /* * Present in VFPv4 only. + * Note that we can't rely on the SIMDFMAC check alone, because + * in a Neon-no-VFP core that ID register field will be non-zero. + */ + if (!dc_isar_feature(aa32_simdfmac, s) || + !dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + /* * In v7A, UNPREDICTABLE with non-zero vector length/stride; from * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A. */ - if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || - (s->vec_len !=3D 0 || s->vec_stride !=3D 0)) { + if (s->vec_len !=3D 0 || s->vec_stride !=3D 0) { return false; } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 79880adaad2..0489e0cdaa6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5150,7 +5150,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) } break; case NEON_3R_VFM_VQRDMLSH: - if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) { + if (!dc_isar_feature(aa32_simdfmac, s)) { return 1; } break; --=20 2.20.1