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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.38.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:38:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YZu863NKaGXhWKWNne24xSYUgnIGai+DzFIAU+N7iSk=; b=VBZoeXyQnZ8iR8499S2q6Oi+uI2sCSK1nAscoRW22bD+7JG3wx6FySvg9nlSl8X1n6 x+GVnb7mCAfm9pSK3ZJ+/l93LIYM1d+J8bEB3EAWtklLSFB1YeILL4+hMUyzbtrT5XCM wKzYJsncC/lYlovXCy3cCJPbwFvPWGIMD4Ud6EtpsjJ12zGBofSsDsUywCQjxzhYTwBj nklN+chPOU74CTtnN/vhkx78tX6lDj39Ub+IrgdulgQMMtk7fCuvfxSYX98Nlca6BdJH Xs/uvfHiYeVsKT2SblSf9jkOOmiqQ/MCGUlkllT90ebecVL4qnrxeStZ8I87Xxv/PxQW WgCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YZu863NKaGXhWKWNne24xSYUgnIGai+DzFIAU+N7iSk=; b=UK0WSmVas/dYa1yyoXkQkpSuA5pYKPOABHES0y091S5gRoM0sw1paIfg6SgyhaPO36 BdJKoXlv2TcqKzii4DL7Ck28ss99/TP77+BL4QAP6g6rMj2kkN6EbH7YCN5BE6Y3HWp1 cHwb8CUFRPPKs93wyU7jjPsseRuCmEEj9JHeNI9GpWQq21JBhbuDAB32NoaZ+MZtBAEX +Am4JXM+dEd9ylE96d/oN4hDNfQnok3VOz8txjWBuvF0ORNq3eUmJ9qBv6inAD1MfJEd 6uiS9AS5hZLJLWJ9NN0kiZxFrK+Ud1abA0yApgai+EIByzK+ftt/iTUGfagP8gNRHY5x 5H6Q== X-Gm-Message-State: APjAAAV2viAAsXBVYgoGF5ZCheT8UQlZJ9lZpmyf//6C5NK2TAzI5OMD IJIYQti8jlYtk746+BJH5f59iG4c4S5slg== X-Google-Smtp-Source: APXvYqyj/hjjEMXoHlKZwIADjKDOXPrP6HWnDHGOADUFV+hWLUPosbVmm1w+bwSJPDFGp86WuLlNnw== X-Received: by 2002:a1c:984a:: with SMTP id a71mr5799398wme.185.1582907938374; Fri, 28 Feb 2020 08:38:58 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/33] target/arm: Add missing checks for fpsp_v2 Date: Fri, 28 Feb 2020 16:38:20 +0000 Message-Id: <20200228163840.23585-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200224222232.13807-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-vfp.inc.c | 78 ++++++++++++++++++++++++++++++---- 1 file changed, 69 insertions(+), 9 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 51d46f43027..f88a95438fc 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -555,6 +555,13 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV= _to_gp *a) int pass; uint32_t offset; =20 + /* SIZE =3D=3D 2 is a VFP instruction; otherwise NEON. */ + if (a->size =3D=3D 2 + ? !dc_isar_feature(aa32_fpsp_v2, s) + : !arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { return false; @@ -564,10 +571,6 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV= _to_gp *a) pass =3D extract32(offset, 2, 1); offset =3D extract32(offset, 0, 2) * 8; =20 - if (a->size !=3D 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -614,6 +617,13 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VM= OV_from_gp *a) int pass; uint32_t offset; =20 + /* SIZE =3D=3D 2 is a VFP instruction; otherwise NEON. */ + if (a->size =3D=3D 2 + ? !dc_isar_feature(aa32_fpsp_v2, s) + : !arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { return false; @@ -623,10 +633,6 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VM= OV_from_gp *a) pass =3D extract32(offset, 2, 1); offset =3D extract32(offset, 0, 2) * 8; =20 - if (a->size !=3D 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -700,6 +706,10 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_= VMRS *a) TCGv_i32 tmp; bool ignore_vfp_enabled =3D false; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (arm_dc_feature(s, ARM_FEATURE_M)) { /* * The only M-profile VFP vmrs/vmsr sysreg is FPSCR. @@ -844,6 +854,10 @@ static bool trans_VMOV_single(DisasContext *s, arg_VMO= V_single *a) { TCGv_i32 tmp; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -873,6 +887,10 @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV= _64_sp *a) { TCGv_i32 tmp; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + /* * VMOV between two general-purpose registers and two single precision * floating point registers @@ -908,8 +926,12 @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV= _64_dp *a) =20 /* * VMOV between two general-purpose registers and one double precision - * floating point register + * floating point register. Note that this does not require support + * for double precision arithmetic. */ + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } =20 /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { @@ -946,6 +968,10 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VL= DR_VSTR_sp *a) uint32_t offset; TCGv_i32 addr, tmp; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -977,6 +1003,11 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_V= LDR_VSTR_dp *a) TCGv_i32 addr; TCGv_i64 tmp; =20 + /* Note that this does not require support for double arithmetic. */ + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; @@ -1013,6 +1044,10 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_= VLDM_VSTM_sp *a) TCGv_i32 addr, tmp; int i, n; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + n =3D a->imm; =20 if (n =3D=3D 0 || (a->vd + n) > 32) { @@ -1086,6 +1121,11 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_= VLDM_VSTM_dp *a) TCGv_i64 tmp; int i, n; =20 + /* Note that this does not require support for double arithmetic. */ + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + n =3D a->imm >> 1; =20 if (n =3D=3D 0 || (a->vd + n) > 32 || n > 16) { @@ -1234,6 +1274,10 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3Op= SPFn *fn, TCGv_i32 f0, f1, fd; TCGv_ptr fpst; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_fpshvec, s) && (veclen !=3D 0 || s->vec_stride !=3D 0)) { return false; @@ -1388,6 +1432,10 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2Op= SPFn *fn, int vd, int vm) int veclen =3D s->vec_len; TCGv_i32 f0, fd; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_fpshvec, s) && (veclen !=3D 0 || s->vec_stride !=3D 0)) { return false; @@ -2023,6 +2071,10 @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_= sp *a) { TCGv_i32 vd, vm; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + /* Vm/M bits must be zero for the Z variant */ if (a->z && a->vm !=3D 0) { return false; @@ -2466,6 +2518,10 @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_V= CVT_int_sp *a) TCGv_i32 vm; TCGv_ptr fpst; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2684,6 +2740,10 @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_V= CVT_sp_int *a) TCGv_i32 vm; TCGv_ptr fpst; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } --=20 2.20.1