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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.38.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:38:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=FqRxxLEQXMGLzTCr1Km31hEFtk/Wttk51AWGftp156w=; b=D0qzKoRkWufzFqZ/ywCCwKPngc2k/lUTSsrXhS9O4hFyTLwkUTKTKsUDB6AW7P8R5r f3NTZBf+r7zkV9F9PkL5YsPKTiKCJidii9WI/Y+JtOAfrBKXLbvfMDHHf+tjLRP0QF8U Vs43t5/n7zgET3K30QndNKQJdOnkybjcvCYntaZ1T4z+SsV/mZu8g3J7Bc/+I6n3ZDRW CGdrRpM9nRk1MszNeca1xLKEsoo9OC6pz8rwV0mPCIkB8jJqXZFs6jUw22ojwmxwY84G yawyU+CX06gtAgQWBdiqDc7YZJb6+6dQ2p3PqWVgtz+ZhjpEpSeP85ux02V992kEmaNW VnAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FqRxxLEQXMGLzTCr1Km31hEFtk/Wttk51AWGftp156w=; b=qXVno9tqjPgUMf0w+QHP5rL+0vAXaQ8EpVC5jPio9kHXzZcx7NbJkPHNYSdW31B7GY GYgb7t5n1o9gtcRpkdaYtBU1zcjeFTwPNCHVzC/UmJUAWr5SipvbRJkNB8lYsUGb2iWx tBHVcXvffblOA3HazzFDDPjD34UDdLJPRbOsJ1axrEmoxl1DrAyoV4EkRBifGst1VAgA dI9wdZhZrKluursQCYV7MczEnSUOKFTNUdW15f3kCumV09r0PIXQYzi8XxzEeZLPY6ik jXr8a+nLoGQluislx3TnzI7MyrdhI9NMf+RPyQ0SL7gIN/GPTQp0v1i0WTgcOK7rEZ3V 14ZA== X-Gm-Message-State: APjAAAX+aN1Fusr2SVR0HmzRQNVjdivnsbElfDxNUJnZXhwfl4QhRCnI 8U4noLo7dMF0TcyRPcbzI3Ea6tXECBucAw== X-Google-Smtp-Source: APXvYqy/f7K0zEXQRYsVebUz6YYXk2qHTbuhvFP/g5kI5Xlroj3SE5ofoZBr7aPdXG8Jv5OHL7FV+A== X-Received: by 2002:a7b:ce0b:: with SMTP id m11mr5725644wmc.4.1582907933842; Fri, 28 Feb 2020 08:38:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/33] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp Date: Fri, 28 Feb 2020 16:38:17 +0000 Message-Id: <20200228163840.23585-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We cannot easily create "any" functions for these, because the ID_AA64PFR0 fields for FP and SIMD signal "enabled" with zero. Which means that an aarch32-only cpu will return incorrect results when testing the aarch64 registers. To use these, we must either have context or additionally test vs ARM_FEATURE_AARCH64. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20200224222232.13807-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 11 +++++++++++ target/arm/cpu.c | 9 ++++++--- target/arm/machine.c | 5 +++-- 3 files changed, 20 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f7a90f512e3..b94d2a5ace4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3494,6 +3494,11 @@ static inline bool isar_feature_aa32_fpdp_v3(const A= RMISARegisters *id) return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >=3D 2; } =20 +static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) +{ + return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); +} + /* * We always set the FP and SIMD FP16 fields to indicate identical * levels of support (assuming SIMD is implemented at all), so @@ -3696,6 +3701,12 @@ static inline bool isar_feature_aa64_dcpodp(const AR= MISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >=3D 2; } =20 +static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) +{ + /* We always set the AdvSIMD and FP fields identically. */ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) !=3D 0xf; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index be4c2a1253d..5be4c258096 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1260,7 +1260,9 @@ void arm_cpu_post_init(Object *obj) * KVM does not currently allow us to lie to the guest about its * ID/feature registers, so the guest always sees what the host has. */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) + ? cpu_isar_feature(aa64_fp_simd, cpu) + : cpu_isar_feature(aa32_vfp, cpu)) { cpu->has_vfp =3D true; if (!kvm_enabled()) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_propert= y); @@ -1636,8 +1638,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * We rely on no XScale CPU having VFP so we can use the same bits in = the * TB flags field for VECSTRIDE and XSCALE_CPAR. */ - assert(!(arm_feature(env, ARM_FEATURE_VFP) && - arm_feature(env, ARM_FEATURE_XSCALE))); + assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || + !cpu_isar_feature(aa32_vfp_simd, cpu) || + !arm_feature(env, ARM_FEATURE_XSCALE)); =20 if (arm_feature(env, ARM_FEATURE_V7) && !arm_feature(env, ARM_FEATURE_M) && diff --git a/target/arm/machine.c b/target/arm/machine.c index 241890ac8cf..c5a2114f51c 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -9,9 +9,10 @@ static bool vfp_needed(void *opaque) { ARMCPU *cpu =3D opaque; - CPUARMState *env =3D &cpu->env; =20 - return arm_feature(env, ARM_FEATURE_VFP); + return (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) + ? cpu_isar_feature(aa64_fp_simd, cpu) + : cpu_isar_feature(aa32_vfp_simd, cpu)); } =20 static int get_fpscr(QEMUFile *f, void *opaque, size_t size, --=20 2.20.1