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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.38.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:38:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qGZ+hkeDo4DLkuBIrqEdZXUncCd+tIHU06Z8m9ZQiI8=; b=EVBok5plp2swBkBlt3cKGXscx9khXWHu7NM5IMfEpOTL0EmFeRCyJ1FbmTAyGMxDTc dA9fQYIbHa/s9kc4W9Jz7jbYPolRmwPxZuVAT0k/v5AGtOfdoks4rWD0c9jIqNOmOBFD wwdvPksgGMIKro2NBPwFh6UCuvv2nBW2rs9CcZ4KItAza7EHI9Laj0FaGjEv9OHj+A3z O0TUhkvBam6/RawsvLZu2O940oWNfibfSXIPFRoSUlXtJRDh12ykyfPJ6AM87S4QrMTH TVEt+T6o35Uk9D0HTFyWNbxSihIt2WRZxCkf6B8RrUHozV3eyAuco/OV1iUpqMoDTW+P m+Nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qGZ+hkeDo4DLkuBIrqEdZXUncCd+tIHU06Z8m9ZQiI8=; b=cs+h13HvB1YP7MlWa0fEX7b4zcIjPy0M4DSOgS4SKBUFDe01uaVZpv0Sk2F2dph9Fr jiC4yrln9r3iz3U2thasvoAgpX/4VNlZd0KtL7CnzMJR6RVfHYYqaiKJFPKNw9ldPc00 ao2X4fSVI0YqqktryvDHF21Ho0t+hL1wGav70Wg0PlFpFb2T7yPEzktvVIWA/NAm6/5a YaWCjhX8r81vh93B8zCj8zYQTRjZQE2w7PLQbl70ZN/R2si+4FQ1lkmu7dBclrIDrUCA DGhe7mdiTUI0geq8VKAyzRgrAvkOd1GZLgdqntkAa6L2zGsKr68fzvc2Xf10znQXoPwW 854g== X-Gm-Message-State: APjAAAVPDrJHUHC1NYUpkgVpvNNFrSoVcCpFxCaxpRmuQZorxzIwqKHI n8JYXjaHHFZ/XJEYGv8hTo8xxzpr+o4vcQ== X-Google-Smtp-Source: APXvYqySh1vMh7hJzIrc+Pbqo6HGOSx+T+4ogT2M+kzaYoZibKdJ93b1L6xATqyY2S/hWhgjvGte3Q== X-Received: by 2002:a5d:4450:: with SMTP id x16mr5491088wrr.242.1582907932781; Fri, 28 Feb 2020 08:38:52 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/33] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} Date: Fri, 28 Feb 2020 16:38:16 +0000 Message-Id: <20200228163840.23585-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42b X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We will shortly use these to test for VFPv2 and VFPv3 in different situations. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200224222232.13807-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1e6eac0cd2a..f7a90f512e3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3470,12 +3470,30 @@ static inline bool isar_feature_aa32_fpshvec(const = ARMISARegisters *id) return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; } =20 +static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) +{ + /* Return true if CPU supports single precision floating point, VFPv2 = */ + return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; +} + +static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) +{ + /* Return true if CPU supports single precision floating point, VFPv3 = */ + return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >=3D 2; +} + static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) { /* Return true if CPU supports double precision floating point, VFPv2 = */ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; } =20 +static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) +{ + /* Return true if CPU supports double precision floating point, VFPv3 = */ + return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >=3D 2; +} + /* * We always set the FP and SIMD FP16 fields to indicate identical * levels of support (assuming SIMD is implemented at all), so --=20 2.20.1