From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582907995; cv=none; d=zohomail.com; s=zohoarc; b=RN1W0xRJPs3fewa5wyaB8yJw/bcgvPWhyEbXnkNP2v1xpLkQT4Sb1aTwZ2TQDInxnTF4CUwnrgRpDnLkkmNFV87ie5s3GtRLAZcBK5pWZIWhm+9VtSK1xn1A/rh4JKNA2Lg/E25g5C+96AYkGj8lW6t0ZZdHrGAealVMDn2LiTw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582907995; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ImwM0adJI+zaYU2PeeesY4R3AUrKvYPOwthqhAld2eU=; b=EW3LJjel18I+Ni2WKQHABEEh/xxiEfcD7sxfvzkxmHjvbsx+7sWl3q3QDRe+Ldi6LDqwgPwz/+EaluNopRXcEUjNh2U1GODbyX6AuCJ6gpBX4xaVVcVJwC/7FyiYtDThOeBgUWfdLQNXiBZsD/7mEjST5pBdjBcePUt+I59uu/Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582907995077586.8491691351073; Fri, 28 Feb 2020 08:39:55 -0800 (PST) Received: from localhost ([::1]:50130 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ig4-0000BP-JB for importer@patchew.org; Fri, 28 Feb 2020 11:39:52 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56357) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7if0-0007EH-Lx for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7iez-0001kr-H6 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:46 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:40073) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7iez-0001jS-BS for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:45 -0500 Received: by mail-wm1-x32a.google.com with SMTP id d138so2302681wmd.5 for ; Fri, 28 Feb 2020 08:38:45 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.38.43 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:38:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ImwM0adJI+zaYU2PeeesY4R3AUrKvYPOwthqhAld2eU=; b=H8DF+2NVEkZCjeVj3Vs1x0iHvSTeXkAaauvyJUTuUYTZ6JmH6ZHNc+3TtibiVxV2wq w3qh4zeIOneWJS6P8t9nlLzSYO01Zm6Z8H3fa7xy/RHeH4Bc/bqHf6JcCeDf1RxIL1jC PWx3JFmfNdESJ+8CeHwnWYZeYYsS04MsiIvRbhFv8AYj3TGSQh7e82L8odH6a2wWPs9K wjsEE50ZV8/zhaVdPo0G053btWPs0eshipl9jmSLfd0I2YsisYwvgHgYoZu8xHHKOm0L lGbciB7WWjfDw6BLEfP8MUji2iDj8yCKId7WqUlO6ipec9QD9Ea8wsLmHJaiWzsNR9yI z09A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ImwM0adJI+zaYU2PeeesY4R3AUrKvYPOwthqhAld2eU=; b=c/xtrA7Vd03lPUr0eoP3lAo73/ZJMB+4SVXsyKGP33YtudpwWA8i8NtW1BjvJp+LrO y5xojhoYK/nGthtoF32oT1zBPpGZaP9m5Du6wl6RE4IG9uJtpjZEDSlV0l1ztZFyJgRc Tb5qpB18z2HI6rEbvyVVocGC7irTrQes2FBy8Gn3b5KOxhWKSbN6UD0lFFe2seacKrhm x12FhCJ5gVY7WP5PE0X1ZaJGkBtWb5hMYzszRCZPZ+07DZP9dkJC62JPTnsKORztc5Nt Tiw1rikcOWWLpwfQ/x87LyOox2mW7/SP+XTBIjd8jHWVelzz0UnRMfe/YXOgI2XAPnbi 3DWA== X-Gm-Message-State: APjAAAVm7AxCOgseLSioehhXzdb0YDK7nSZJfPWE3/Cx/0WA70TDbY6k XIz+bLTC2LWGkX9iEnyAXstP4XWCflMCjw== X-Google-Smtp-Source: APXvYqw9rSepdizjwcMCjzGhcNoA8G2utvd2kBWWMjH2b6II5k5XUmL/Ap6hEWhmTgWK82+5VTwcAw== X-Received: by 2002:a1c:2504:: with SMTP id l4mr5768854wml.72.1582907923987; Fri, 28 Feb 2020 08:38:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/33] hw/arm: Use TYPE_PL011 to create serial port Date: Fri, 28 Feb 2020 16:38:08 +0000 Message-Id: <20200228163840.23585-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32a X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Gavin Shan This uses TYPE_PL011 when creating the serial port so that the code looks cleaner. Signed-off-by: Gavin Shan Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Message-id: 20200224222223.4128-1-gshan@redhat.com Signed-off-by: Peter Maydell --- hw/arm/sbsa-ref.c | 3 ++- hw/arm/virt.c | 3 ++- hw/arm/xlnx-versal.c | 3 ++- 3 files changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 1cba9fc3021..8409ba853de 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -39,6 +39,7 @@ #include "hw/pci-host/gpex.h" #include "hw/qdev-properties.h" #include "hw/usb.h" +#include "hw/char/pl011.h" #include "net/net.h" =20 #define RAMLIMIT_GB 8192 @@ -409,7 +410,7 @@ static void create_uart(const SBSAMachineState *sms, in= t uart, { hwaddr base =3D sbsa_ref_memmap[uart].base; int irq =3D sbsa_ref_irqmap[uart]; - DeviceState *dev =3D qdev_create(NULL, "pl011"); + DeviceState *dev =3D qdev_create(NULL, TYPE_PL011); SysBusDevice *s =3D SYS_BUS_DEVICE(dev); =20 qdev_prop_set_chr(dev, "chardev", chr); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a8191a3e75e..856808599d2 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -74,6 +74,7 @@ #include "hw/mem/nvdimm.h" #include "hw/acpi/generic_event_device.h" #include "hw/virtio/virtio-iommu.h" +#include "hw/char/pl011.h" =20 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ @@ -727,7 +728,7 @@ static void create_uart(const VirtMachineState *vms, in= t uart, int irq =3D vms->irqmap[uart]; const char compat[] =3D "arm,pl011\0arm,primecell"; const char clocknames[] =3D "uartclk\0apb_pclk"; - DeviceState *dev =3D qdev_create(NULL, "pl011"); + DeviceState *dev =3D qdev_create(NULL, TYPE_PL011); SysBusDevice *s =3D SYS_BUS_DEVICE(dev); =20 qdev_prop_set_chr(dev, "chardev", chr); diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 1cf3daaf4f4..403fc7b8814 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -22,6 +22,7 @@ #include "hw/misc/unimp.h" #include "hw/intc/arm_gicv3_common.h" #include "hw/arm/xlnx-versal.h" +#include "hw/char/pl011.h" =20 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") #define GEM_REVISION 0x40070106 @@ -144,7 +145,7 @@ static void versal_create_uarts(Versal *s, qemu_irq *pi= c) DeviceState *dev; MemoryRegion *mr; =20 - dev =3D qdev_create(NULL, "pl011"); + dev =3D qdev_create(NULL, TYPE_PL011); s->lpd.iou.uart[i] =3D SYS_BUS_DEVICE(dev); qdev_prop_set_chr(dev, "chardev", serial_hd(i)); object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fat= al); --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908096; cv=none; d=zohomail.com; s=zohoarc; b=eKS1XMT7OconZAm95a0cChun9JhfkR5HHbFQ9yNcOWBtbB2qzh1LzslrIgdP1mOWuV4HKMm4RtP8Chx403Ff5S2m87eny96RRonnEhExcTwxh7rooyfbWTh1LKrf/YF+9JcPFtJwohOr7//2VnTZFDJQKia9Mi8lSVnNKK5JWAE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908096; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UjASb9Z8QnXhRYOsvt2c7nwH5VonxCR4/zGig7D/A+U=; b=O8zAnac9RDelZ5u9TYmupYj1P7wdOVMXLOwWC2FZCo/DsC9XGBfGXqY2EbFIrI0ui/KFtXRNq+MWRHvQxyE5BGSQ1GA31BOE17l/6jh1z9kMmxiK0oqoPxVgxxYlXspVwghUXMkGpXXuNZkyHa4eqao1UnBY2tPXgCP8XS4Y+x8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908096146310.8239873624094; Fri, 28 Feb 2020 08:41:36 -0800 (PST) Received: from localhost ([::1]:50195 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ihi-0003qg-WF for importer@patchew.org; Fri, 28 Feb 2020 11:41:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56366) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7if1-0007EJ-Ay for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7if0-0001ls-GC for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:47 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:51403) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7if0-0001l0-AU for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:46 -0500 Received: by mail-wm1-x342.google.com with SMTP id t23so3862154wmi.1 for ; Fri, 28 Feb 2020 08:38:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.38.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:38:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=UjASb9Z8QnXhRYOsvt2c7nwH5VonxCR4/zGig7D/A+U=; b=QqPbb73deHrp8+uZ70A8sET7xXtKptzfjYLjBJiPQTbDTOQPegr5IYo7ly4iHlsL8h m0Bc0HeJsa/G+exx0TzRs+k5/3Uje7hX/sAxPSKZy8ETWowi4bhk3vhhu2/lsBBch3PE r1YnBdWEtvoSHGPKmXNU50BCyZEhIBCLIhWxe1v6CkmP5vxOv38TKLOWKyi+iU5UJMnJ 88NeIrLMeTb0W44YQq2nqov9v+0/Zu2B3bAApH/1GWuWMHt5/1/3FLvoJaEKFZ2W6NT1 0XQFA8ImhdbDDgJem+PJczspD72/AXjgGVPYIdcdrnW838ObOOXIDUy9yNKzeW0JYT5i J+sA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UjASb9Z8QnXhRYOsvt2c7nwH5VonxCR4/zGig7D/A+U=; b=bSH21yjA06WB1CNj/JxsxEQWBaBhcKx0O+C4yr8GdwuFlczwVxfN+owmVPX6C8ZKH+ Z0y/Y7HNtrI86Dvzo/2SUHVcPtzt0PbTuuKavyW1SAK8ABS/i2l6QvKMNk2aVPAcGJMK MlZBu8AzE77Mve5ME5p27nsv6O0O2Wry1TcHuoMqIeyDwK5jnNBV1AnpEgGQhUODhIEv 6k5/Cabu3J+Pgqp9PYzLlC5jKqpXxMKpafXFV/9qXy7H1inpFU0uk+KwcsDioenPInMj yxzZJ/c8fdsBmaLKB8+hLXxRphZpiv8IRdPbBboS/gR5AP8ZZCg+FruOKKg43detktBh LI0A== X-Gm-Message-State: APjAAAXuhA9FD+c8JWml5LQQhIxUumObQwQvlHc26rwA0kuRo+DLrl4p /Hb0LIw7oQRTUKpNXTY1hAzmsvDMRVcrJg== X-Google-Smtp-Source: APXvYqw5hFlzEibrbvHPPmZ2nV6xg+4fKbOsWZQ5OnK743vNbuOnFqVMqHZ/e25cDrwkZGumrpu/kA== X-Received: by 2002:a7b:cae9:: with SMTP id t9mr5509710wml.186.1582907925066; Fri, 28 Feb 2020 08:38:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/33] target/arm: Set ID_MMFR4.HPDS for aarch64_max_initfn Date: Fri, 28 Feb 2020 16:38:09 +0000 Message-Id: <20200228163840.23585-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We had set this for aarch32-only in arm_max_initfn, but failed to set the same bit for aarch64. Signed-off-by: Richard Henderson Message-id: 20200218190958.745-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0929401a4dd..db695384ebc 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -704,6 +704,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_mmfr3 =3D u; =20 u =3D cpu->isar.id_mmfr4; + u =3D FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ u =3D FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ cpu->isar.id_mmfr4 =3D u; =20 --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908100; cv=none; d=zohomail.com; s=zohoarc; b=l63Wut7rEMKVB0ewkJAkTkVAjObhbeT3TG1dOmCYONveo5hH4UhxagErGJNg5iVz2E1wyfbcjMaEjjQw6ub/IsnTry7Mej+AqEcRlS0ALOOhBYIKyELGrhZgGQBQb9EUzhW02pAnp+xRNsHh2CfFXX4UGFk9H6AEkzlQvolneGo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908100; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=p1vL82UhROt8QXhCUT1feYYkEotDCosoZbN7/fg2s9o=; b=K0A6xrrbYlxivDBDAQBbdVLDjvA4+NpZxDHxJhYKJcTuWG3YjbdkTtSUKkwhROSUImmOGFoTF0xD4VN7SRv8Q6cQqR3JOWQ7F0MoIjBVTwAJz/Fgu6bj9IPsKR+V3MdXOaytNtUeF2Ma8HyjcVZi01bOWnno8Lmf3ltpRNvh93E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908100531259.1242000210211; Fri, 28 Feb 2020 08:41:40 -0800 (PST) Received: from localhost ([::1]:50198 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ihn-000426-9S for importer@patchew.org; Fri, 28 Feb 2020 11:41:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56384) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7if2-0007Ea-R7 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7if1-0001mi-Nc for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:48 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:36847) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7if1-0001mC-HL for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:47 -0500 Received: by mail-wm1-x329.google.com with SMTP id g83so1708038wme.1 for ; Fri, 28 Feb 2020 08:38:47 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.38.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:38:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=p1vL82UhROt8QXhCUT1feYYkEotDCosoZbN7/fg2s9o=; b=bLtRVeHlZKlL18VRGYJDD8RjmhQMmybKM5kBfU8MORmkXVP0RJHB3iXYUByqB3bTbD Lmcq0P9KVVF95qjovTBAiEaGnc8LO1t/lXj4KAljghn+Pi+bIl3l9edFzMVpj8qGTx5B dDQQ06PMRxGrdp9bcZ1XKcRDy/vtTdhsgZx2YIu8sCamVlSDjdZAnFqVgVyPzUJfkWy0 aUfylGXjhlzsS3z5YnzjK4aGqizQZW0yihBWdsEhyCKn2oL/rXJM6HVILiNuL0p+xtne n5SoUssf+D1ze0SEuw4NAvu313vUlRht6rfw3TMP08XuNfBOOH2ZCCMpuvrLpaSplmm/ U6gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=p1vL82UhROt8QXhCUT1feYYkEotDCosoZbN7/fg2s9o=; b=ROWWdY/Pph5KxbJ68pFGr14KSOEpZDdLBjzxxsr4mcdaKb3uPT+VhJ+JZP8J8JWNNS P6XfLjI752XrWpJ+7EfwdeggjxCqXPWslxxOMg0dWAVsGjokXfebPn1gprvq8JjgaWNO 5DKCxe0IlOgRL+/4hJNPi8wxty7UaSVgJ+goWFsnx1jXJFCV+i4JvS3GwGzGoSwMG02q 60o3H/3fopZCCa4VgvjeTSp2rPQ/FEgq1mJT0J9MRz6mVeroy11rVZPVxGhLQY2t6BXh kmn9A71f/xk9LXqwoaa3j7b2nFhtLlh8a3P/ObPvZPELjNWjVW1dpSLzW4XyVUwhpneQ T4Yg== X-Gm-Message-State: APjAAAW0lSjJ39fOBzvtyAS4RFzadvT+rdsPv4Y+B4VUKByhZj0E7sFC 2qBZIf20Ce8Lf57BJvt+P3kbMOHCFhXFZQ== X-Google-Smtp-Source: APXvYqxqaJ/auXTizGmmWTmVRcRwplohICnqvz0h1fnm5v5AaRUdJvgx18RYH69YA6KXWl0AbzbhTw== X-Received: by 2002:a1c:1b41:: with SMTP id b62mr5353257wmb.97.1582907926188; Fri, 28 Feb 2020 08:38:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/33] hw/arm/integratorcp: Map the audio codec controller Date: Fri, 28 Feb 2020 16:38:10 +0000 Message-Id: <20200228163840.23585-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::329 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 The Linux kernel displays errors why trying to detect the PL041 audio interface: Linux version 4.16.0 (linus@genomnajs) (gcc version 7.2.1 20171011 (Linar= o GCC 7.2-2017.11)) #142 PREEMPT Wed May 9 13:24:55 CEST 2018 CPU: ARM926EJ-S [41069265] revision 5 (ARMv5TEJ), cr=3D00093177 CPU: VIVT data cache, VIVT instruction cache OF: fdt: Machine model: ARM Integrator/CP ... OF: amba_device_add() failed (-19) for /fpga/aaci@1d000000 Since we have it already modelled, simply plug it. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200223233033.15371-2-f4bug@amsat.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/integratorcp.c | 1 + hw/arm/Kconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index cc845b85340..6d69010d06b 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -642,6 +642,7 @@ static void integratorcp_init(MachineState *machine) qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_WPROT, = 0)); qdev_connect_gpio_out(dev, 1, qdev_get_gpio_in_named(icp, ICP_GPIO_MMC_CARDIN,= 0)); + sysbus_create_varargs("pl041", 0x1d000000, pic[25], NULL); =20 if (nd_table[0].used) smc91c111_init(&nd_table[0], 0xc8000000, pic[27]); diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 3d86691ae0c..61635f52c42 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -69,6 +69,7 @@ config INTEGRATOR select INTEGRATOR_DEBUG select PL011 # UART select PL031 # RTC + select PL041 # audio select PL050 # keyboard/mouse select PL110 # pl111 LCD controller select PL181 # display --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908009; cv=none; d=zohomail.com; s=zohoarc; b=nN62iveiS9LYdq45Suue3qlkHgWoCo+33Ie6MZVm3pKD4lQD1OA7+T6MofayCDP9Y3jidOU2gm5p/JHzvtGw/pPEG2lVT0iXmGA1V1YBDDNzF851hCcBclwprHTZIZ4tSK5iv/QSyqq8MyNwcYEfkg8sGY8nRSF0lizLLGWzuec= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908009; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=A5mwcI/ZKfr3Tx2KU66kVPbnF23MRJiSSiyB+hKM2CQ=; b=Hju5UCyMRtaE9WEQ4gTFlkC0YTtv8iuIqJXtALgvFt9Ly6LJMYtQCWGSi5+IzWZagcrho2CHlLkpX1aFDN98JxVYPSCaZrGrr5z4ip87DbSI9erH3jcdRfmvLhxatqjvKx8U+xxsMtTlCgNmSEUC2vLnSKr/dI/F/ATps/ajpb4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908009557938.8496982950206; Fri, 28 Feb 2020 08:40:09 -0800 (PST) Received: from localhost ([::1]:50138 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7igK-0000hm-AM for importer@patchew.org; Fri, 28 Feb 2020 11:40:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56399) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7if4-0007Ei-8B for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7if3-0001nR-0M for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:50 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:40083) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7if2-0001my-QH for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:48 -0500 Received: by mail-wm1-x334.google.com with SMTP id d138so2302924wmd.5 for ; Fri, 28 Feb 2020 08:38:48 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.38.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:38:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=A5mwcI/ZKfr3Tx2KU66kVPbnF23MRJiSSiyB+hKM2CQ=; b=nM4d+fcknakBsqL9wyxhzJT2RzyVjLOGS2qg/4JqBsOAh82YqanlOr51BWUbEBceEz eq5T5m7uuryLQOaPUFORQIccCk2yG/1jQuMnenT8HKyBl+f6CaCx980uxkkq6fF3mKTO dH/W7qejJdrRLq5phLA6zVgOuVT4TI0nRsuHV5E7uhXbkINPEzifQRw45vBWrH1bYvfJ HVb/k3oyzSwkSxtLH8QxUZPN3YYsbyG241SvuXq09Mv3+xyAki0nyL99z32jlIx1hoPj rckezZavDsA7OQYalPesDckOZS2fbRtb7Y4nS1AMh/XZhcUegr9iNsd0ME9S8GiG4Rej yyqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A5mwcI/ZKfr3Tx2KU66kVPbnF23MRJiSSiyB+hKM2CQ=; b=XhD9rF2bV6fP+wmhbGNUNpzIQTmtJgQoTPtpVglOubf1eMoD6FLTWzkRfWZTTf2PSS N1Qfx1gvEJOwkzZc6Vs1lacLmkibX84RVb3dcjnzu2gmQnKdJ4YCZu4fDANA/yICpWMQ RGhZj+OZaUO+aYWaT9EnvOuxy7tqX7tiO3aS/Hy4g6KvXwAn7rljNEvXpuNDSdqtYsrV a/m7St2qQ2FKDyCO0n+VKovuH6E852XuFh6i+vdE37Qzx+tOScss2BLe1EzJ42fSLKeD 3MJBMqEtd7GXMjwrmaUan7ivqQzssY3+jgiokXgmVQ8oCPaRpL1MNTGE60dP5bHHSJEg Az5w== X-Gm-Message-State: APjAAAUZzGATT2v10HVi9ZMHHbRRQZAI9OCqUe7NwaHLu3l07m0xhWYf UArB6XFNBgmlH1N0ZuP7apsZMYrMXMZ6uA== X-Google-Smtp-Source: APXvYqzu/nX+vUqm+o7lq7cOBxBXzkS6R7+0elAYGTOeBvXadvnOwFlnWqwYmIO0ps65jlZ6wwTUWQ== X-Received: by 2002:a7b:cbcf:: with SMTP id n15mr5572752wmi.21.1582907927354; Fri, 28 Feb 2020 08:38:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/33] arm_gic: Mask the un-supported priority bits Date: Fri, 28 Feb 2020 16:38:11 +0000 Message-Id: <20200228163840.23585-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::334 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Sai Pavan Boddu The GICv2 allows the implementation to implement a variable number of priority bits; unimplemented bits in the priority registers are read as zeros, writes ignored. We were previously always implementing a full 8 bits of priority, which is allowed but not what the real hardware typically does (which is usually to have 4 or 5 bits of priority). Add a new device property to allow the number of implemented property bits to be specified. Signed-off-by: Sai Pavan Boddu Message-id: 1582537164-764-2-git-send-email-sai.pavan.boddu@xilinx.com Suggested-by: Peter Maydell Reviewed-by: Peter Maydell [PMM: improved commit message] Signed-off-by: Peter Maydell --- include/hw/intc/arm_gic.h | 2 ++ include/hw/intc/arm_gic_common.h | 1 + hw/intc/arm_gic.c | 33 ++++++++++++++++++++++++++++++-- hw/intc/arm_gic_common.c | 1 + 4 files changed, 35 insertions(+), 2 deletions(-) diff --git a/include/hw/intc/arm_gic.h b/include/hw/intc/arm_gic.h index ed703a17203..303b9748cbb 100644 --- a/include/hw/intc/arm_gic.h +++ b/include/hw/intc/arm_gic.h @@ -68,6 +68,8 @@ =20 /* Number of SGI target-list bits */ #define GIC_TARGETLIST_BITS 8 +#define GIC_MAX_PRIORITY_BITS 8 +#define GIC_MIN_PRIORITY_BITS 4 =20 #define TYPE_ARM_GIC "arm_gic" #define ARM_GIC(obj) \ diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_com= mon.h index b5585fec451..6e0d6b8a889 100644 --- a/include/hw/intc/arm_gic_common.h +++ b/include/hw/intc/arm_gic_common.h @@ -96,6 +96,7 @@ typedef struct GICState { uint16_t priority_mask[GIC_NCPU_VCPU]; uint16_t running_priority[GIC_NCPU_VCPU]; uint16_t current_pending[GIC_NCPU_VCPU]; + uint32_t n_prio_bits; =20 /* If we present the GICv2 without security extensions to a guest, * the guest can configure the GICC_CTLR to configure group 1 binary p= oint diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 1d7da7baa20..c60dc6b5e6e 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -641,6 +641,23 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, Mem= TxAttrs attrs) return ret; } =20 +static uint32_t gic_fullprio_mask(GICState *s, int cpu) +{ + /* + * Return a mask word which clears the unimplemented priority + * bits from a priority value for an interrupt. (Not to be + * confused with the group priority, whose mask depends on BPR.) + */ + int priBits; + + if (gic_is_vcpu(cpu)) { + priBits =3D GIC_VIRT_MAX_GROUP_PRIO_BITS; + } else { + priBits =3D s->n_prio_bits; + } + return ~0U << (8 - priBits); +} + void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, MemTxAttrs attrs) { @@ -651,6 +668,8 @@ void gic_dist_set_priority(GICState *s, int cpu, int ir= q, uint8_t val, val =3D 0x80 | (val >> 1); /* Non-secure view */ } =20 + val &=3D gic_fullprio_mask(s, cpu); + if (irq < GIC_INTERNAL) { s->priority1[irq][cpu] =3D val; } else { @@ -669,7 +688,7 @@ static uint32_t gic_dist_get_priority(GICState *s, int = cpu, int irq, } prio =3D (prio << 1) & 0xff; /* Non-secure view */ } - return prio; + return prio & gic_fullprio_mask(s, cpu); } =20 static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, @@ -684,7 +703,7 @@ static void gic_set_priority_mask(GICState *s, int cpu,= uint8_t pmask, return; } } - s->priority_mask[cpu] =3D pmask; + s->priority_mask[cpu] =3D pmask & gic_fullprio_mask(s, cpu); } =20 static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs att= rs) @@ -2055,6 +2074,16 @@ static void arm_gic_realize(DeviceState *dev, Error = **errp) return; } =20 + if (s->n_prio_bits > GIC_MAX_PRIORITY_BITS || + (s->virt_extn ? s->n_prio_bits < GIC_VIRT_MAX_GROUP_PRIO_BITS : + s->n_prio_bits < GIC_MIN_PRIORITY_BITS)) { + error_setg(errp, "num-priority-bits cannot be greater than %d" + " or less than %d", GIC_MAX_PRIORITY_BITS, + s->virt_extn ? GIC_VIRT_MAX_GROUP_PRIO_BITS : + GIC_MIN_PRIORITY_BITS); + return; + } + /* This creates distributor, main CPU interface (s->cpuiomem[0]) and if * enabled, virtualization extensions related interfaces (main virtual * interface (s->vifaceiomem[0]) and virtual CPU interface). diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index e6c4fe7a5a4..7b44d5625b6 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -357,6 +357,7 @@ static Property arm_gic_common_properties[] =3D { DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0= ), /* True if the GIC should implement the virtualization extensions */ DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn,= 0), + DEFINE_PROP_UINT32("num-priority-bits", GICState, n_prio_bits, 8), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908175; cv=none; d=zohomail.com; s=zohoarc; b=OyBfwB6t25LhFsmIWeT+kCl/rhbu0DT1w1vLafPwGzaA6HEdW4syiG2JfKJyCnb/FD3Y9+uia6zcMccjHh1IC003Xlt4UqS6bz0zGhnYcoUjKHsVM4sYLVhVgyQSIP9sunrqCKYCHs4WHhZx+XgWaVdqLmbRLLador9k1kwTxsA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908175; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DrxWiG6jWEHbV7tbIEKAcwRWenD5JqrAAvIabuixUV4=; b=DQDQijBlqECs165EF2I1/uF8sLhAesOPcS+n3h9PYJKGzGkl4JJWHjoMqyT3QooBI97xWYp/jFQQ0Bj4iAkEqlDELJh7PJ3YEBaeXP/iyZ3sMA+5mn+aU8B71pkhdEANH+IxR1P7YkTGEkQVeEmFHE8CFjPCV+fyrAPtabrHnTo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908175553216.9162422069693; Fri, 28 Feb 2020 08:42:55 -0800 (PST) Received: from localhost ([::1]:50244 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ij0-0007AC-CF for importer@patchew.org; Fri, 28 Feb 2020 11:42:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56404) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7if4-0007F8-Ry for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7if3-0001nu-TU for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:50 -0500 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:39579) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7if3-0001nW-JE for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:49 -0500 Received: by mail-wm1-x329.google.com with SMTP id c84so3870038wme.4 for ; Fri, 28 Feb 2020 08:38:49 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.38.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:38:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DrxWiG6jWEHbV7tbIEKAcwRWenD5JqrAAvIabuixUV4=; b=FLhh6Nc1M8OwUxXdRxn7WVIr76Wq+ZLJdnHwRId/lhEzFeSu8oYgmwH67ytHAsCuEj lzBRc2DQHdG5AuAIjHXXLWIEWe27cMfY592s9NRmMWicnwh1cl+9TJ3tSiF2ep9rzugc Jxmh8OYuV+up/esxLgoDRZhWSrNin5b4rebLlpi21a41cDsHfObwQCu2oVowzVQ/NHBW Xn36E4Xb6hz9QGY9C3Q4k5AcFyA3+4j9lSpXVCOsfhJs1SMjZ8dqNxJegCyvE2yzGiaj CP1sw50h58mRt0+vnbnw0vcksvoppOzBcOfAscnmhrtixfdQw5cLTITdb55dYclvA1Tv ePdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DrxWiG6jWEHbV7tbIEKAcwRWenD5JqrAAvIabuixUV4=; b=bEXH1ej5+jY6joIhFD6ys0ff9FNx8RTR5bpsPjmB+vvPW2TuBm23hlXbyAeyRyd5mp IQn3mKOkB2OSZ25exm7WgXY/FJ+3DVpXbNk8KUQibLB/5dhUcXxBi+CBTusUIGNd7uHC OXvLlgqG+ePDJjuudVkH2KCS5aB1avD7qqeTvk1Q35Jl5aATFSyZsYXvtXJuuyTNpa6R tOL8EVb9zcqTsKK4HExGOU65JYUDawOmd4zWoh+VD+tRJfetuUD1RZDB3v4ubcb/dAsb OY4UKS32nphNUNjc2e5wfGsQA3odKUcQ+UhG9J6ACgmqvqwwWHWhBwWVIzxTfWQv4AxN DZcg== X-Gm-Message-State: APjAAAWUadUdKwq3OhcHIpJDmio+O0FdmdsVOYSEdkPfvZBVpWUDvqIQ O1U3kkj2R/TlevmUYWFsk2NqBZyWjX7kqQ== X-Google-Smtp-Source: APXvYqySDumxWxAKkOcEUnjrG8pJ5z03AVFrXsqnooDRJNvnScd2VPV3TBtFPnvWJA0HWxA3vizPkg== X-Received: by 2002:a05:600c:4151:: with SMTP id h17mr5955408wmm.189.1582907928407; Fri, 28 Feb 2020 08:38:48 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/33] cpu/a9mpcore: Set number of GIC priority bits to 5 Date: Fri, 28 Feb 2020 16:38:12 +0000 Message-Id: <20200228163840.23585-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::329 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Sai Pavan Boddu All A9 CPUs have a GIC with 5 bits of priority. Signed-off-by: Sai Pavan Boddu Reviewed-by: Peter Maydell Message-id: 1582537164-764-3-git-send-email-sai.pavan.boddu@xilinx.com Suggested-by: Peter Maydell Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/cpu/a9mpcore.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index 1f8bc8a196f..b4f6a7e8a54 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -16,6 +16,8 @@ #include "hw/qdev-properties.h" #include "hw/core/cpu.h" =20 +#define A9_GIC_NUM_PRIORITY_BITS 5 + static void a9mp_priv_set_irq(void *opaque, int irq, int level) { A9MPPrivState *s =3D (A9MPPrivState *)opaque; @@ -68,6 +70,8 @@ static void a9mp_priv_realize(DeviceState *dev, Error **e= rrp) gicdev =3D DEVICE(&s->gic); qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + qdev_prop_set_uint32(gicdev, "num-priority-bits", + A9_GIC_NUM_PRIORITY_BITS); =20 /* Make the GIC's TZ support match the CPUs. We assume that * either all the CPUs have TZ, or none do. --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908289; cv=none; d=zohomail.com; s=zohoarc; b=DqKTHHi3VCgP+6NsX6U0hCBm4RQFTg8GHQXuG4N7wa+kTazbP1jmccMibBbbXdRv0FA1+xYSwufPjdzy5ue3MYxawB5PyGlT3a86UKUzJlCnIoSw4pT8INgUyQMA7sCbSDnaIpCr/MftaLLOzjQCJBeNarJPhns0Bgy0GqnZ3FU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908289; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nSlxCsltQjy6FqvEdHt6MRzvJ+bEsn0aUcxipAHAa08=; b=LsQM+2TClCKz7TBqhejGr0HfUk5dQiafLNCzOY9J95K3AYjUfTHUGP24ipnEg0i3s/lts4EiCMjpdUDVx9NSalSXKCwJnk9oyhKefeRKPy6Nms4rFnMX+lzCXBjb+7velwd/or32h6QbnId7LjiVnmqNvxmDSL1MJ8CEE8WfaCw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908289617418.25029232802706; Fri, 28 Feb 2020 08:44:49 -0800 (PST) Received: from localhost ([::1]:50318 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ikq-0002Ms-DS for importer@patchew.org; Fri, 28 Feb 2020 11:44:48 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56421) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7if5-0007GQ-VQ for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7if5-0001oh-11 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:51 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:36809) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7if4-0001oB-RH for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:50 -0500 Received: by mail-wr1-x436.google.com with SMTP id j16so3687467wrt.3 for ; Fri, 28 Feb 2020 08:38:50 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.38.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:38:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=nSlxCsltQjy6FqvEdHt6MRzvJ+bEsn0aUcxipAHAa08=; b=duU6eQxr59a/ZLa/KtZsCIruH2vUmm0JznT0rQC45r+d28EzzUbe/eOYLunn5U9Azc 4cAQ4p7gpiVr5NJA4T/5lCEy7B1lkyOwdz0uOaoudnqCHmO1TrXe9P+PEbJHEdmi2lYa KsA0dtZtap3siyHcnG1qckb5ZjErQgNl3obC6PbxFYVUud5K3c+cWAvGcFN8SvbRlJ59 94jzN65EWkjZ5PyylZJ9KIfEPbacfa8iSvCt7FFoPLTqA+Z+vmVjpGrmT49R24R1rxfN jnxFQGfVWHMLU4tBjUQ3PKLEpoJyJsj9Tm0kZcE7HjZ1GCuuEZ2PzM0KmfPN3BrC/Ik0 tRdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nSlxCsltQjy6FqvEdHt6MRzvJ+bEsn0aUcxipAHAa08=; b=iVH8mF5KAiyNzF0lKRhMDvogZIQZrF0TD8wRDSat042Edm0uQC+xRBwUNm7tuOe46L 215JFkuYezNpSgzmo340onM3RTBuxynsGNeYukprCD+jIT4Mree4ersxqXbWVewyRGoU v7n/r9oacVVrsSvOMDHaBwgrtqIk0svOkK9fTQcJXKwiamymBl1KizEWzxz/JKDtbAW7 v7FhEZ+K3jgKmWoQaaJKrfnLcpjswBhfc+L0kYDK7/8VHGEZ+FDXYRvHrEnyRWNh8/cG lnoDoPvqC6zdrg0fja/X+b9UFOxEwWITJqxnoEB2K02DaDKi9yqWZjKZ13ZrQpuqTfOt PXXg== X-Gm-Message-State: APjAAAWG38/eUpVeU7BTPxK1RQUYLx6/e9YBysihUvBa3MJjyw3gxThH WwgCtdY9CBNt7H7q6QnEuPAobb3BrKoLCg== X-Google-Smtp-Source: APXvYqzrrHqr8PrgwnmeNH5ZOwq/ND8bgckwSZ29hgVOCgwQ0qpngRjQ3u8eNI8n3Ux4ZHic3BRRyw== X-Received: by 2002:a5d:518b:: with SMTP id k11mr5816187wrv.114.1582907929532; Fri, 28 Feb 2020 08:38:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/33] cpu/arm11mpcore: Set number of GIC priority bits to 4 Date: Fri, 28 Feb 2020 16:38:13 +0000 Message-Id: <20200228163840.23585-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::436 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Sai Pavan Boddu The GIC built into the ARM11MPCore is always implemented with 4 priority bits; set the GIC property accordingly. Signed-off-by: Sai Pavan Boddu Reviewed-by: Peter Maydell Message-id: 1582537164-764-4-git-send-email-sai.pavan.boddu@xilinx.com Suggested-by: Peter Maydell Reviewed-by: Peter Maydell [PMM: tweaked commit message] Signed-off-by: Peter Maydell --- hw/cpu/arm11mpcore.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c index 2e3e87cc1b3..ab9fadb67cb 100644 --- a/hw/cpu/arm11mpcore.c +++ b/hw/cpu/arm11mpcore.c @@ -15,6 +15,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" =20 +#define ARM11MPCORE_NUM_GIC_PRIORITY_BITS 4 =20 static void mpcore_priv_set_irq(void *opaque, int irq, int level) { @@ -86,6 +87,10 @@ static void mpcore_priv_realize(DeviceState *dev, Error = **errp) =20 qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + qdev_prop_set_uint32(gicdev, "num-priority-bits", + ARM11MPCORE_NUM_GIC_PRIORITY_BITS); + + object_property_set_bool(OBJECT(&s->gic), true, "realized", &err); if (err !=3D NULL) { error_propagate(errp, err); --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908112; cv=none; d=zohomail.com; s=zohoarc; b=lCuu+9X7oYao3Y5LEempd+Z8bDX7d80a5SRCdvbzy5pMOSwrawopW40BcMdaQ8J7RYpcyPDWLvScQK/iYXMhK2t7y3QydNEjwthOep0fEGE3QoEtkzpy1cf2igmn/z4ayKuTvkF4wpn+je64oai0VwjPYQpZtHp0W2n4PF/5gbc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908112; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XwFayHGAlgtbTjyBRhE/jLwf5sdkAmef4Kxh8ptCpD4=; b=S3lbVpfYQsYyoSFtFGRFuHCotnvkGU4x/J8e1sGNxH9hK6KNXs5gyRRWQWVxk/O7I4psoBQiWpqLpYhGG3xEfD7MBONhMmtsRHTOLVqJpZhfPy8jXCmRXnqJ75b0pXnfI+EKws+H48qgLa2JivGSAiwYcl8hYjmETypn+ZwFfAA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908112330226.2880478088465; Fri, 28 Feb 2020 08:41:52 -0800 (PST) Received: from localhost ([::1]:50206 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ihz-0004UZ-1W for importer@patchew.org; Fri, 28 Feb 2020 11:41:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56449) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7if8-0007J6-6c for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7if6-0001pV-AC for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:54 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:53371) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7if6-0001ow-2u for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:52 -0500 Received: by mail-wm1-x32d.google.com with SMTP id f15so3835251wml.3 for ; Fri, 28 Feb 2020 08:38:52 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.38.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:38:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XwFayHGAlgtbTjyBRhE/jLwf5sdkAmef4Kxh8ptCpD4=; b=CfU9YQtP8xBdClxjEp3azxpFYBaJW7FVffYGR2yLnHzgH2JFDSaTki10YoBSfy9wd3 z0aG2844lAarA2J5HOi0NIigYlOMvmkKx08FLHd2v0SLY8Y1eRQ6c2P2Ep0NdsowMmbl PhTBCSG+WZM2HHykTMpf43naxGqtT3nePbdxZ4fP3LS7PsqywvBnGATNkLMT2yoGMS9Z eZmQYQ5Eq80Mxj+fNQYCLayjMaL7BOIxNZ6ggCqFYagBG4Kj0O46DmTqN7fkG7ZuGGDb 84AJQHAgYlSCAhv5/V2PlAQw6yyMc1GBrkORj7W1ilteLZSrXzzG8fNvaO4VQA+LpXi/ +gIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XwFayHGAlgtbTjyBRhE/jLwf5sdkAmef4Kxh8ptCpD4=; b=i90K9lUTfKI+zwKQw8zE1nBdOYA7dVnIvdGHUYNa6hFvm4wfudDPfxK5wrvHiEz8Gr qSudxuK76AINCGVzDsKnfvpbm3tkd3n65Id71GYGQwggXk7CUM690U94Dv+uDFI/AkLG g/BR/3T0bR1T7fF6VZVwCJvJzl/ezyC/uD/mtMeuA3kETz2Y3fy9XQd3Wmlj0gmDT5wp 4wr+V4iqq008an6JBkqRMw05WESwyZIvwYVbAvxJviVvW/KMwoUArGi6CkNxBYfSakFQ LaI7X0oy/jwL8ccpr6Qf2FoRuXVnk48SvgJl5Mh6A0fPDp9p5nWoZqPyptrcApLJ8s8s u3wA== X-Gm-Message-State: APjAAAUrCJkhZxX+FuP1RE5HaHDcF/wDgGKaWicKRCYhW+E/W01mWnJs bSGmnjylutYJQW3xRebMkvq3/wQgCs0aSA== X-Google-Smtp-Source: APXvYqyOxe8+mDcSccIGhTxKMzzBCVpwg0Y9ev9lYOgQ1vZCeLsUxXSZzIAiMq7anBOilekePoUbJQ== X-Received: by 2002:a1c:e908:: with SMTP id q8mr1204180wmc.77.1582907930547; Fri, 28 Feb 2020 08:38:50 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/33] target/arm: Add isar_feature_aa32_vfp_simd Date: Fri, 28 Feb 2020 16:38:14 +0000 Message-Id: <20200228163840.23585-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use this in the places that were checking ARM_FEATURE_VFP, and are obviously testing for the existance of the register set as opposed to testing for some particular instruction extension. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20200224222232.13807-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 9 +++++++++ hw/intc/armv7m_nvic.c | 20 ++++++++++---------- linux-user/arm/signal.c | 4 ++-- target/arm/arch_dump.c | 11 ++++++----- target/arm/cpu.c | 4 ++-- target/arm/helper.c | 4 ++-- target/arm/m_helper.c | 11 ++++++----- 7 files changed, 37 insertions(+), 26 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 65171cb30ee..a128d48d405 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3450,6 +3450,15 @@ static inline bool isar_feature_aa32_fp16_arith(cons= t ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) =3D=3D 1; } =20 +static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) +{ + /* + * Return true if either VFP or SIMD is implemented. + * In this case, a minimum of VFP w/ D0-D15. + */ + return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; +} + static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) { /* Return true if D16-D31 are implemented */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 22a43e49847..a62587eb3f0 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1262,12 +1262,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) case 0xd84: /* CSSELR */ return cpu->env.v7m.csselr[attrs.secure]; case 0xd88: /* CPACR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } return cpu->env.v7m.cpacr[attrs.secure]; case 0xd8c: /* NSACR */ - if (!attrs.secure || !arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!attrs.secure || !cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } return cpu->env.v7m.nsacr; @@ -1417,7 +1417,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) } return cpu->env.v7m.sfar; case 0xf34: /* FPCCR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } if (attrs.secure) { @@ -1444,12 +1444,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) return value; } case 0xf38: /* FPCAR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } return cpu->env.v7m.fpcar[attrs.secure]; case 0xf3c: /* FPDSCR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } return cpu->env.v7m.fpdscr[attrs.secure]; @@ -1711,13 +1711,13 @@ static void nvic_writel(NVICState *s, uint32_t offs= et, uint32_t value, } break; case 0xd88: /* CPACR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { /* We implement only the Floating Point extension's CP10/CP11 = */ cpu->env.v7m.cpacr[attrs.secure] =3D value & (0xf << 20); } break; case 0xd8c: /* NSACR */ - if (attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (attrs.secure && cpu_isar_feature(aa32_vfp_simd, cpu)) { /* We implement only the Floating Point extension's CP10/CP11 = */ cpu->env.v7m.nsacr =3D value & (3 << 10); } @@ -1951,7 +1951,7 @@ static void nvic_writel(NVICState *s, uint32_t offset= , uint32_t value, break; } case 0xf34: /* FPCCR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { /* Not all bits here are banked. */ uint32_t fpccr_s; =20 @@ -2005,13 +2005,13 @@ static void nvic_writel(NVICState *s, uint32_t offs= et, uint32_t value, } break; case 0xf38: /* FPCAR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { value &=3D ~7; cpu->env.v7m.fpcar[attrs.secure] =3D value; } break; case 0xf3c: /* FPDSCR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { value &=3D 0x07c00000; cpu->env.v7m.fpdscr[attrs.secure] =3D value; } diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c index b0e753801b6..d96fc27ce11 100644 --- a/linux-user/arm/signal.c +++ b/linux-user/arm/signal.c @@ -346,7 +346,7 @@ static void setup_sigframe_v2(struct target_ucontext_v2= *uc, setup_sigcontext(&uc->tuc_mcontext, env, set->sig[0]); /* Save coprocessor signal frame. */ regspace =3D uc->tuc_regspace; - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { regspace =3D setup_sigframe_v2_vfp(regspace, env); } if (arm_feature(env, ARM_FEATURE_IWMMXT)) { @@ -671,7 +671,7 @@ static int do_sigframe_return_v2(CPUARMState *env, =20 /* Restore coprocessor signal frame */ regspace =3D uc->tuc_regspace; - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { regspace =3D restore_sigframe_v2_vfp(env, regspace); if (!regspace) { return 1; diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 2345dec3c2c..7693e17e964 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -363,9 +363,11 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, = CPUState *cs, int cpuid, void *opaque) { struct arm_note note; - CPUARMState *env =3D &ARM_CPU(cs)->env; + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; DumpState *s =3D opaque; - int ret, i, fpvalid =3D !!arm_feature(env, ARM_FEATURE_VFP); + int ret, i; + bool fpvalid =3D cpu_isar_feature(aa32_vfp_simd, cpu); =20 arm_note_init(¬e, s, "CORE", 5, NT_PRSTATUS, sizeof(note.prstatus)); =20 @@ -444,7 +446,6 @@ int cpu_get_dump_info(ArchDumpInfo *info, ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) { ARMCPU *cpu =3D ARM_CPU(first_cpu); - CPUARMState *env =3D &cpu->env; size_t note_size; =20 if (class =3D=3D ELFCLASS64) { @@ -452,12 +453,12 @@ ssize_t cpu_get_note_size(int class, int machine, int= nr_cpus) note_size +=3D AARCH64_PRFPREG_NOTE_SIZE; #ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_sve, cpu)) { - note_size +=3D AARCH64_SVE_NOTE_SIZE(env); + note_size +=3D AARCH64_SVE_NOTE_SIZE(&cpu->env); } #endif } else { note_size =3D ARM_PRSTATUS_NOTE_SIZE; - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { note_size +=3D ARM_VFP_NOTE_SIZE; } } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2eadf4dcb8b..be4c2a1253d 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -293,7 +293,7 @@ static void arm_cpu_reset(CPUState *s) env->v7m.ccr[M_REG_S] |=3D R_V7M_CCR_UNALIGN_TRP_MASK; } =20 - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { env->v7m.fpccr[M_REG_NS] =3D R_V7M_FPCCR_ASPEN_MASK; env->v7m.fpccr[M_REG_S] =3D R_V7M_FPCCR_ASPEN_MASK | R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; @@ -1011,7 +1011,7 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f,= int flags) int numvfpregs =3D 0; if (cpu_isar_feature(aa32_simd_r32, cpu)) { numvfpregs =3D 32; - } else if (arm_feature(env, ARM_FEATURE_VFP)) { + } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { numvfpregs =3D 16; } for (i =3D 0; i < numvfpregs; i++) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 79db169e046..8841cc7fde8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -894,7 +894,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. * TRCDIS [28] is RAZ/WI since we do not implement a trace macroce= ll. */ - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { /* VFP coprocessor: cp10 & cp11 [23:20] */ mask |=3D (1 << 31) | (1 << 30) | (0xf << 20); =20 @@ -7814,7 +7814,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 35, "arm-vfp3.xml", 0); - } else if (arm_feature(env, ARM_FEATURE_VFP)) { + } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 19, "arm-vfp.xml", 0); } diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 33d414a684b..5e8a795d202 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -738,7 +738,8 @@ static uint32_t v7m_integrity_sig(CPUARMState *env, uin= t32_t lr) */ uint32_t sig =3D 0xfefa125a; =20 - if (!arm_feature(env, ARM_FEATURE_VFP) || (lr & R_V7M_EXCRET_FTYPE_MAS= K)) { + if (!cpu_isar_feature(aa32_vfp_simd, env_archcpu(env)) + || (lr & R_V7M_EXCRET_FTYPE_MASK)) { sig |=3D 1; } return sig; @@ -841,7 +842,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t l= r, bool dotailchain, =20 if (dotailchain) { /* Sanitize LR FType and PREFIX bits */ - if (!arm_feature(env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { lr |=3D R_V7M_EXCRET_FTYPE_MASK; } lr =3D deposit32(lr, 24, 8, 0xff); @@ -1373,7 +1374,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) =20 ftype =3D excret & R_V7M_EXCRET_FTYPE_MASK; =20 - if (!arm_feature(env, ARM_FEATURE_VFP) && !ftype) { + if (!ftype && !cpu_isar_feature(aa32_vfp_simd, cpu)) { qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception= " "exit PC value 0x%" PRIx32 " is UNPREDICTABLE " "if FPU not present\n", @@ -2450,7 +2451,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskr= eg, uint32_t val) * SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 =3D=3D 0, * RES0 if the FPU is not present, and is stored in the S bank */ - if (arm_feature(env, ARM_FEATURE_VFP) && + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env)) && extract32(env->v7m.nsacr, 10, 1)) { env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_FPCA_MASK; env->v7m.control[M_REG_S] |=3D val & R_V7M_CONTROL_FPCA_MA= SK; @@ -2565,7 +2566,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskr= eg, uint32_t val) env->v7m.control[env->v7m.secure] &=3D ~R_V7M_CONTROL_NPRIV_MA= SK; env->v7m.control[env->v7m.secure] |=3D val & R_V7M_CONTROL_NPR= IV_MASK; } - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { /* * SFPA is RAZ/WI from NS or if no FPU. * FPCA is RO if NSACR.CP10 =3D=3D 0, RES0 if the FPU is not p= resent. --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908428; cv=none; d=zohomail.com; s=zohoarc; b=P4gPFGdNIdzlY7pd1Q3aV4IN0m/ATK0sS4/y/jUK+Hc3TXbLAr8t/o3PkR2pYfRYj67oW4SpETk//lIrP5HRqytFsCPAZealLEpjX2tgJG8pAUApDI8BNpPjsGdXSgOr4KmEXDcMoO8FR3xYbLm3j8SzHAYxYvJbdGnVlxg6nHI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908428; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sePkBd54w+3287LZ8LJspmr9uwrTqj5oJOIrdf/A0uM=; b=EYIm/EPNO6PIYZA6vn0ZEBJRHkVUEnlL8Ha2yPnQxqiHh6QjcI+jS2c2XKK6jKnadrBukhxSuqlbNv18bTrh+grY/TNYWCvOY6rgEErW4NfsHxyov6zj/5GFyTt22Yk0of+W7tIfn+VP8tRj5eLjp6sCCFhdUo294tI5nMiM2BU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158290842832214.059429664849517; Fri, 28 Feb 2020 08:47:08 -0800 (PST) Received: from localhost ([::1]:50514 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7in4-0006Pf-SR for importer@patchew.org; Fri, 28 Feb 2020 11:47:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56455) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7if8-0007Jp-Iz for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7if7-0001qI-8s for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:54 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:42256) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7if7-0001pn-2D for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:53 -0500 Received: by mail-wr1-x433.google.com with SMTP id p18so3636781wre.9 for ; Fri, 28 Feb 2020 08:38:53 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.38.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:38:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sePkBd54w+3287LZ8LJspmr9uwrTqj5oJOIrdf/A0uM=; b=z07IPW5IErtmdNtGsafxx25bHg7fqigpofL7hXnZ+NCU0ASILniY2ujLxFrjOxhXC3 y+Oagn5NSACPency6dciLTgPXn+ph1HHr50HWHbdgCU/0nC3IBY6PpXnqiqs/VAM+4IX SI5G5njSSmK5cE+L1pLFUK3+kN3OuLruktcuBGkKM82wswIO/jKcMo1FhdBhzGeBQZyb 02KrqdC7jjZHXQUGXKbPBF26MvVR8c3HAf7A31sflqTdC09WR5sKFY7q6tzmTnVyMsE7 gFs/Re4raGpDD4AZ4nvjp/p+uH/Bpj+5HWUbc/SOSfcIGIFWnYs9SefHoLjLhOu0HEAZ tN1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sePkBd54w+3287LZ8LJspmr9uwrTqj5oJOIrdf/A0uM=; b=YuxDJPcqGbVQBKFpeXzjTmGF0PAfu/wLjamvoufayXqzjNLbCx0YD2/gEViR9bY1yY cK19LgLNQKpIn7eautG64MQa/407Q+tUf50eu4cJ9Zn3N+dLq1vsE2kdPG3tCFQoSHcB aWuLo1K2mwGv7jkiZbKLyzEJojWMASdmCxjM43fJTlhBtzD/X214jzfBnnZ7jfcNd3BZ zlIjIHYZAVXuP//G3BbrWFqeUIFi0NrVVWXc9YHXcQN9McZaDNA4n/P7OCKUrdi6JVE9 xlhxoYcGgX3pWeIUzYYukXjVj4zXMut4YmcGN4A2p8HqOSGzTFLC5Kc7/Ei6aP6/0fGw 5YLQ== X-Gm-Message-State: APjAAAVAUuKG/zZI+jAzXccV+vJ0ui3iDqc1Y7eslt6G/2xtZCvUS+pG yGGb0725qY774poBnV2hnf3KHfprLMHxng== X-Google-Smtp-Source: APXvYqylST1/yH46ggQ8hjDRLDzT29KDXHPvcfMppKsj5y9uzxNw90pWyVMFdI/8Iv8Epl9ZJ2gRPw== X-Received: by 2002:a5d:5007:: with SMTP id e7mr5660291wrt.228.1582907931694; Fri, 28 Feb 2020 08:38:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/33] target/arm: Rename isar_feature_aa32_fpdp_v2 Date: Fri, 28 Feb 2020 16:38:15 +0000 Message-Id: <20200228163840.23585-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::433 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson The old name, isar_feature_aa32_fpdp, does not reflect that the test includes VFPv2. We will introduce another feature tests for VFPv3. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-id: 20200224222232.13807-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 4 ++-- target/arm/translate-vfp.inc.c | 40 +++++++++++++++++----------------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a128d48d405..1e6eac0cd2a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3470,9 +3470,9 @@ static inline bool isar_feature_aa32_fpshvec(const AR= MISARegisters *id) return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; } =20 -static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id) +static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) { - /* Return true if CPU supports double precision floating point */ + /* Return true if CPU supports double precision floating point, VFPv2 = */ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; } =20 diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index ba46e2557a1..e94876c30ca 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -206,7 +206,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -339,7 +339,7 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMA= XNM *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -425,7 +425,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -488,7 +488,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1313,7 +1313,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpD= PFn *fn, return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1462,7 +1462,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpD= PFn *fn, int vd, int vm) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1827,7 +1827,7 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp = *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1926,7 +1926,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VM= OV_imm_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2070,7 +2070,7 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_d= p *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2143,7 +2143,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_V= CVT_f64_f16 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2209,7 +2209,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_V= CVT_f16_f64 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2269,7 +2269,7 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRIN= TR_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2330,7 +2330,7 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRIN= TZ_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2389,7 +2389,7 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRIN= TX_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2417,7 +2417,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_s= p *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2445,7 +2445,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_d= p *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2499,7 +2499,7 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VC= VT_int_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2539,7 +2539,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2632,7 +2632,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VC= VT_fix_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2728,7 +2728,7 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VC= VT_dp_int *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908013; cv=none; d=zohomail.com; s=zohoarc; b=FZ4IIPBrvCkcqZnqb2MvDiAn29YLOygIRr9bCtomTZ7eqJkXgCKJ/M88zftJWfQwEAlVKpuZ2k+61/esLZInUcRr36CcCHVgwxk415v1Ooiku5aKFsS+0MX9P6Wgjw0yFs0kXo37uRrKvEoX2VPvKa6BcXMO0gMkN4POWmTXqK8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908013; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qGZ+hkeDo4DLkuBIrqEdZXUncCd+tIHU06Z8m9ZQiI8=; b=TEGhoz77KFnZkKx42wzaKMmwSMs9iPF75J4VYoZt4NGqIdmysqOLV/lEvpkzkpqqXvinYCPNW0GP9updPJJZqUPnvTlXK7OrZE8Lcnw3Pp25nWuzoe8AqO3IF/eGCePCjnsY20xfFMZ9a1xefQkYw9daXxw18tqwi8HuLDapFok= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908013626225.02520979467397; Fri, 28 Feb 2020 08:40:13 -0800 (PST) Received: from localhost ([::1]:50142 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7igO-0000sM-DA for importer@patchew.org; Fri, 28 Feb 2020 11:40:12 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56461) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7if9-0007Kx-97 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7if8-0001qz-A3 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:55 -0500 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:34219) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7if8-0001qW-3p for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:54 -0500 Received: by mail-wr1-x42b.google.com with SMTP id z15so3707575wrl.1 for ; Fri, 28 Feb 2020 08:38:54 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.38.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:38:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qGZ+hkeDo4DLkuBIrqEdZXUncCd+tIHU06Z8m9ZQiI8=; b=EVBok5plp2swBkBlt3cKGXscx9khXWHu7NM5IMfEpOTL0EmFeRCyJ1FbmTAyGMxDTc dA9fQYIbHa/s9kc4W9Jz7jbYPolRmwPxZuVAT0k/v5AGtOfdoks4rWD0c9jIqNOmOBFD wwdvPksgGMIKro2NBPwFh6UCuvv2nBW2rs9CcZ4KItAza7EHI9Laj0FaGjEv9OHj+A3z O0TUhkvBam6/RawsvLZu2O940oWNfibfSXIPFRoSUlXtJRDh12ykyfPJ6AM87S4QrMTH TVEt+T6o35Uk9D0HTFyWNbxSihIt2WRZxCkf6B8RrUHozV3eyAuco/OV1iUpqMoDTW+P m+Nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qGZ+hkeDo4DLkuBIrqEdZXUncCd+tIHU06Z8m9ZQiI8=; b=cs+h13HvB1YP7MlWa0fEX7b4zcIjPy0M4DSOgS4SKBUFDe01uaVZpv0Sk2F2dph9Fr jiC4yrln9r3iz3U2thasvoAgpX/4VNlZd0KtL7CnzMJR6RVfHYYqaiKJFPKNw9ldPc00 ao2X4fSVI0YqqktryvDHF21Ho0t+hL1wGav70Wg0PlFpFb2T7yPEzktvVIWA/NAm6/5a YaWCjhX8r81vh93B8zCj8zYQTRjZQE2w7PLQbl70ZN/R2si+4FQ1lkmu7dBclrIDrUCA DGhe7mdiTUI0geq8VKAyzRgrAvkOd1GZLgdqntkAa6L2zGsKr68fzvc2Xf10znQXoPwW 854g== X-Gm-Message-State: APjAAAVPDrJHUHC1NYUpkgVpvNNFrSoVcCpFxCaxpRmuQZorxzIwqKHI n8JYXjaHHFZ/XJEYGv8hTo8xxzpr+o4vcQ== X-Google-Smtp-Source: APXvYqySh1vMh7hJzIrc+Pbqo6HGOSx+T+4ogT2M+kzaYoZibKdJ93b1L6xATqyY2S/hWhgjvGte3Q== X-Received: by 2002:a5d:4450:: with SMTP id x16mr5491088wrr.242.1582907932781; Fri, 28 Feb 2020 08:38:52 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/33] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} Date: Fri, 28 Feb 2020 16:38:16 +0000 Message-Id: <20200228163840.23585-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42b X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We will shortly use these to test for VFPv2 and VFPv3 in different situations. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200224222232.13807-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1e6eac0cd2a..f7a90f512e3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3470,12 +3470,30 @@ static inline bool isar_feature_aa32_fpshvec(const = ARMISARegisters *id) return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; } =20 +static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) +{ + /* Return true if CPU supports single precision floating point, VFPv2 = */ + return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; +} + +static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) +{ + /* Return true if CPU supports single precision floating point, VFPv3 = */ + return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >=3D 2; +} + static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) { /* Return true if CPU supports double precision floating point, VFPv2 = */ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; } =20 +static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) +{ + /* Return true if CPU supports double precision floating point, VFPv3 = */ + return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >=3D 2; +} + /* * We always set the FP and SIMD FP16 fields to indicate identical * levels of support (assuming SIMD is implemented at all), so --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908568; cv=none; d=zohomail.com; s=zohoarc; b=UJV5VqD/uYIJQUBi45O7MfUOJWgRvvIYaq5YgHZvDTjSkdDskCO7rSO5SBDFnNIV6a3bMoiuiP09U/YLLJbdOYQqlnmf3fAHVvkTVCJg+qTAkV5d52CcHdYFjW6I2uYB/KU67+4SZ4S7L+PZJv84vc0B+Anbhl9X3H/EyamqUpM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908568; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FqRxxLEQXMGLzTCr1Km31hEFtk/Wttk51AWGftp156w=; b=d97aT7gHJErYD13BaIVt9R4BTWJUv4juj1X9ITpQxNkW4YupQnri7AMZQJPJnRG5Q7iGsyZuPwwv/S9EXajbE8UrvJNIzyFzkkYvHSeu6w1F9JMLRVABx9pwnmBG8uv+arLDciTyiYoqhsDA/vsabuZ/tcvalmGsAy9tkbCJeR4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158290856888466.15310048643562; Fri, 28 Feb 2020 08:49:28 -0800 (PST) Received: from localhost ([::1]:50572 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ipL-0001Wx-OE for importer@patchew.org; Fri, 28 Feb 2020 11:49:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56485) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifA-0007Ni-PX for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7if9-0001rk-Hf for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:56 -0500 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:33204) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7if9-0001rJ-B7 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:55 -0500 Received: by mail-wm1-x344.google.com with SMTP id m10so9731111wmc.0 for ; Fri, 28 Feb 2020 08:38:55 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.38.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:38:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=FqRxxLEQXMGLzTCr1Km31hEFtk/Wttk51AWGftp156w=; b=D0qzKoRkWufzFqZ/ywCCwKPngc2k/lUTSsrXhS9O4hFyTLwkUTKTKsUDB6AW7P8R5r f3NTZBf+r7zkV9F9PkL5YsPKTiKCJidii9WI/Y+JtOAfrBKXLbvfMDHHf+tjLRP0QF8U Vs43t5/n7zgET3K30QndNKQJdOnkybjcvCYntaZ1T4z+SsV/mZu8g3J7Bc/+I6n3ZDRW CGdrRpM9nRk1MszNeca1xLKEsoo9OC6pz8rwV0mPCIkB8jJqXZFs6jUw22ojwmxwY84G yawyU+CX06gtAgQWBdiqDc7YZJb6+6dQ2p3PqWVgtz+ZhjpEpSeP85ux02V992kEmaNW VnAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FqRxxLEQXMGLzTCr1Km31hEFtk/Wttk51AWGftp156w=; b=qXVno9tqjPgUMf0w+QHP5rL+0vAXaQ8EpVC5jPio9kHXzZcx7NbJkPHNYSdW31B7GY GYgb7t5n1o9gtcRpkdaYtBU1zcjeFTwPNCHVzC/UmJUAWr5SipvbRJkNB8lYsUGb2iWx tBHVcXvffblOA3HazzFDDPjD34UDdLJPRbOsJ1axrEmoxl1DrAyoV4EkRBifGst1VAgA dI9wdZhZrKluursQCYV7MczEnSUOKFTNUdW15f3kCumV09r0PIXQYzi8XxzEeZLPY6ik jXr8a+nLoGQluislx3TnzI7MyrdhI9NMf+RPyQ0SL7gIN/GPTQp0v1i0WTgcOK7rEZ3V 14ZA== X-Gm-Message-State: APjAAAX+aN1Fusr2SVR0HmzRQNVjdivnsbElfDxNUJnZXhwfl4QhRCnI 8U4noLo7dMF0TcyRPcbzI3Ea6tXECBucAw== X-Google-Smtp-Source: APXvYqy/f7K0zEXQRYsVebUz6YYXk2qHTbuhvFP/g5kI5Xlroj3SE5ofoZBr7aPdXG8Jv5OHL7FV+A== X-Received: by 2002:a7b:ce0b:: with SMTP id m11mr5725644wmc.4.1582907933842; Fri, 28 Feb 2020 08:38:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/33] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp Date: Fri, 28 Feb 2020 16:38:17 +0000 Message-Id: <20200228163840.23585-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We cannot easily create "any" functions for these, because the ID_AA64PFR0 fields for FP and SIMD signal "enabled" with zero. Which means that an aarch32-only cpu will return incorrect results when testing the aarch64 registers. To use these, we must either have context or additionally test vs ARM_FEATURE_AARCH64. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20200224222232.13807-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 11 +++++++++++ target/arm/cpu.c | 9 ++++++--- target/arm/machine.c | 5 +++-- 3 files changed, 20 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f7a90f512e3..b94d2a5ace4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3494,6 +3494,11 @@ static inline bool isar_feature_aa32_fpdp_v3(const A= RMISARegisters *id) return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >=3D 2; } =20 +static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) +{ + return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); +} + /* * We always set the FP and SIMD FP16 fields to indicate identical * levels of support (assuming SIMD is implemented at all), so @@ -3696,6 +3701,12 @@ static inline bool isar_feature_aa64_dcpodp(const AR= MISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >=3D 2; } =20 +static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) +{ + /* We always set the AdvSIMD and FP fields identically. */ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) !=3D 0xf; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index be4c2a1253d..5be4c258096 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1260,7 +1260,9 @@ void arm_cpu_post_init(Object *obj) * KVM does not currently allow us to lie to the guest about its * ID/feature registers, so the guest always sees what the host has. */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) + ? cpu_isar_feature(aa64_fp_simd, cpu) + : cpu_isar_feature(aa32_vfp, cpu)) { cpu->has_vfp =3D true; if (!kvm_enabled()) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_propert= y); @@ -1636,8 +1638,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * We rely on no XScale CPU having VFP so we can use the same bits in = the * TB flags field for VECSTRIDE and XSCALE_CPAR. */ - assert(!(arm_feature(env, ARM_FEATURE_VFP) && - arm_feature(env, ARM_FEATURE_XSCALE))); + assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || + !cpu_isar_feature(aa32_vfp_simd, cpu) || + !arm_feature(env, ARM_FEATURE_XSCALE)); =20 if (arm_feature(env, ARM_FEATURE_V7) && !arm_feature(env, ARM_FEATURE_M) && diff --git a/target/arm/machine.c b/target/arm/machine.c index 241890ac8cf..c5a2114f51c 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -9,9 +9,10 @@ static bool vfp_needed(void *opaque) { ARMCPU *cpu =3D opaque; - CPUARMState *env =3D &cpu->env; =20 - return arm_feature(env, ARM_FEATURE_VFP); + return (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) + ? cpu_isar_feature(aa64_fp_simd, cpu) + : cpu_isar_feature(aa32_vfp_simd, cpu)); } =20 static int get_fpscr(QEMUFile *f, void *opaque, size_t size, --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908110; cv=none; d=zohomail.com; s=zohoarc; b=gzBLhMmq//K6fWVZNLncIpRXMmN9CbtPyhGTkg1oCgbLHyhv3l35L15npCnFMxlO3PE6dOO95LdJnBBQRcadL0kazn6SB4XM1MoB0QcRB8X3+v5N1M32UTTQtbj/z13jRJ+APVxysCRCDf06yAal0KK0AZSc//+VhFoqbO8krSs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908110; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=shlVhcZnOZKNj4cL6nMd6uYbiv5CWaO9bwOYlKOsNRM=; b=WGSfunLxjWs5STndUzwL2vHQl66j6pvOAaXteYj/34HGU+BIiAdSNHK0kdReQeL+B+ki5ghgVCPhG/w/dIaBvq4X0v7wZc5PZeZmmuUmr3KSRTl1tdS4O9ZNAa0H9lkgUUPti8tHYNxZE2IJbjdlTseGzoG0WpItsKcmUp+bscg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908110343898.6644602961115; Fri, 28 Feb 2020 08:41:50 -0800 (PST) Received: from localhost ([::1]:50202 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ihv-0004Mj-TL for importer@patchew.org; Fri, 28 Feb 2020 11:41:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56510) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifC-0007SV-Vs for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifB-0001sq-8D for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:58 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:38819) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifB-0001sC-0W for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:57 -0500 Received: by mail-wm1-x341.google.com with SMTP id n64so2576823wme.3 for ; Fri, 28 Feb 2020 08:38:56 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.38.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:38:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=shlVhcZnOZKNj4cL6nMd6uYbiv5CWaO9bwOYlKOsNRM=; b=vhrXQwrwhGOYuQefwV/eM8yTI0kUKey+5Ymuo1qp/XeKTQUBqyooUW+feOvDVTz9kd aONa6zNw8EP2mOt0XHPpVyVxo5PFIBaQgYDWo55cC1LpjHElkjSSyb+8KoQ2BhB4uNhk KTOsTC5Rzy5vUNxY+yhmGp52tPfiFHJdGZr0dZlJ54x+5RjA9/4l466McRLqDrNJZFaa SZ1eYK1T/bMwtRBYmpCYmPO12BqMogFImm8gRCPXgeYxYGCOcJtOoY53s+IT5rKSDqvo yCV8UN9HXEAKFtcEpQKklzlPxE/81ni7LHMvUltwu9p/nJ+iLM/ZjQ3Gq8yW+mSxm/1+ i3pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=shlVhcZnOZKNj4cL6nMd6uYbiv5CWaO9bwOYlKOsNRM=; b=gie3vtEaa+Z/CqFrScA3oVzQLuvvin2u1lqo68QN9WGsnqVn6zCB7HvrNTkinN7nje VtMWEPR9DCfcqd1KELIoLc6yfWMssfDTHJz5LP4oYK8b0kLSMfDWJo75K4qCGglO9Ru8 FiojXRZmgiXRnD1ik6AA/37AnxqWwCUw/Cj16gpE9wJtDcCc4yMnhJ1RhvVFz4JYheY8 7BY7wHvcWABZlnTC645TbahDvaLlgTxofnaBuWRh4UYnXtKLepxyWDjscHjz7KR7DN64 wbyhu8MBeZ06xWqQzUdCy/k+j8MWloMhD/EcVVfyPdDTzgkD4LgEhMRuMlFLFkOp9mKl NbmQ== X-Gm-Message-State: APjAAAUehowdKRQGZqCNZ/f5i+gPqnL6kP+70LaJQrtWLwIp672Ehwnj 7allKxTuxuiveQnk2Jjiyc0zhI8ReFf46A== X-Google-Smtp-Source: APXvYqzkgNwkXtmTc7rg6tl0fUs8WNNuTOe+8DkdMb47CK5p9xy5+/i/mJT2vshSDSFVvjnb6yE+TA== X-Received: by 2002:a05:600c:20e:: with SMTP id 14mr5463185wmi.108.1582907935199; Fri, 28 Feb 2020 08:38:55 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/33] target/arm: Perform fpdp_v2 check first Date: Fri, 28 Feb 2020 16:38:18 +0000 Message-Id: <20200228163840.23585-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200224222232.13807-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-vfp.inc.c | 140 +++++++++++++++++---------------- 1 file changed, 71 insertions(+), 69 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index e94876c30ca..ff301650455 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -200,13 +200,13 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vn | a->vd) & 0x10)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && + ((a->vm | a->vn | a->vd) & 0x10)) { return false; } =20 @@ -333,13 +333,13 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMIN= MAXNM *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vn | a->vd) & 0x10)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && + ((a->vm | a->vn | a->vd) & 0x10)) { return false; } =20 @@ -419,13 +419,13 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vd) & 0x10)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && + ((a->vm | a->vd) & 0x10)) { return false; } =20 @@ -483,12 +483,12 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 @@ -1308,12 +1308,12 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3O= pDPFn *fn, TCGv_i64 f0, f1, fd; TCGv_ptr fpst; =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) { return false; } =20 @@ -1457,12 +1457,12 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2O= pDPFn *fn, int vd, int vm) int veclen =3D s->vec_len; TCGv_i64 f0, fd; =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) { return false; } =20 @@ -1827,7 +1827,9 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp = *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { return false; } =20 @@ -1921,12 +1923,12 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_= VMOV_imm_dp *a) =20 vd =3D a->vd; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) { return false; } =20 @@ -2060,6 +2062,10 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_= dp *a) { TCGv_i64 vd, vm; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + /* Vm/M bits must be zero for the Z variant */ if (a->z && a->vm !=3D 0) { return false; @@ -2070,10 +2076,6 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_= dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2134,6 +2136,10 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_= VCVT_f64_f16 *a) TCGv_i32 tmp; TCGv_i64 vd; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_fp16_dpconv, s)) { return false; } @@ -2143,10 +2149,6 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_= VCVT_f64_f16 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2200,6 +2202,10 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_= VCVT_f16_f64 *a) TCGv_i32 tmp; TCGv_i64 vm; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_fp16_dpconv, s)) { return false; } @@ -2209,10 +2215,6 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_= VCVT_f16_f64 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2260,6 +2262,10 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRI= NTR_dp *a) TCGv_ptr fpst; TCGv_i64 tmp; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_vrint, s)) { return false; } @@ -2269,10 +2275,6 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRI= NTR_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2321,6 +2323,10 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRI= NTZ_dp *a) TCGv_i64 tmp; TCGv_i32 tcg_rmode; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_vrint, s)) { return false; } @@ -2330,10 +2336,6 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRI= NTZ_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2380,6 +2382,10 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRI= NTX_dp *a) TCGv_ptr fpst; TCGv_i64 tmp; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_vrint, s)) { return false; } @@ -2389,10 +2395,6 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRI= NTX_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2412,12 +2414,12 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT= _sp *a) TCGv_i64 vd; TCGv_i32 vm; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; } =20 @@ -2440,12 +2442,12 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT= _dp *a) TCGv_i64 vm; TCGv_i32 vd; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 @@ -2494,12 +2496,12 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_= VCVT_int_dp *a) TCGv_i64 vd; TCGv_ptr fpst; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; } =20 @@ -2530,6 +2532,10 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *= a) TCGv_i32 vd; TCGv_i64 vm; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_jscvt, s)) { return false; } @@ -2539,10 +2545,6 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *= a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2623,6 +2625,10 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_V= CVT_fix_dp *a) TCGv_ptr fpst; int frac_bits; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { return false; } @@ -2632,10 +2638,6 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_V= CVT_fix_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2723,12 +2725,12 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_= VCVT_dp_int *a) TCGv_i64 vm; TCGv_ptr fpst; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908191; cv=none; d=zohomail.com; s=zohoarc; b=iaAWtj0iiGbK2xOp6K/YC49tPsk021PuSp6NwoN0gO57J72ROpHCYKFLVlg7bWgu2Ksdc1zhwBw+SkC8O15sYbOnQdhgNPeQYhs1S6XkWun+CuSG8+aK2GYa54JyhcYrwF5LIUZN7iPudE+gq/1eYFyWfqTL1YPUIj2v0LMizVw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908191; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LRuxsvUE6MoetAym138Cb7YXTKAQg191Q+D+Hx23Pq4=; b=MmjeJqTwlnQSakmdEflBKXT/4NSeQrWrzGF6wyichp7QRgBuDbAlQelOlGnVTKytWRs4NQRuRBlcsD+d/xLI8qPUaAChyNFUPRX6fX4R3k5okwGIl/vV6C0b9t0/GmG+x0pDwFoCs6I5lHpZxEcIUhOj9vKkIupx0sO+wnfyWe8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908191557272.465901621376; Fri, 28 Feb 2020 08:43:11 -0800 (PST) Received: from localhost ([::1]:50252 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ijG-0007vN-Dn for importer@patchew.org; Fri, 28 Feb 2020 11:43:10 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56515) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifD-0007Ti-GX for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifC-0001tX-Dn for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:59 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:37421) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifC-0001t8-7b for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:58 -0500 Received: by mail-wm1-x342.google.com with SMTP id a141so3904551wme.2 for ; Fri, 28 Feb 2020 08:38:58 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.38.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:38:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LRuxsvUE6MoetAym138Cb7YXTKAQg191Q+D+Hx23Pq4=; b=PXzMT4BRRMw5gRXIMcOn92ZIHPyFhgclRxEAre7Yx34nFp3emrjojJsTPCuHrjykQY t6Tatg4Tz15eXBsyx7yk++kCZFf6EIWqSUpZuw787sKluQhPZGEYyDcPByNzTNi7dS/N pUBQUU9MwHn5dAPqRpY9J7rwqicLFzfq8w94kXPsy/MrnpSRtvkZlmWX/bYA9xLrqS8s mePB8bIJSdDbKWjpKOrn9hywe6ui4SBWzfvBhfJ86b/j2uE9XEvyzvijheQt8zSL9wu6 pwJZnTXwPTr8lRroSv6ekAue9wCmjhEWHB6pBP6AHFby2hi8hW25WNWAyMTF5qKhBjL/ vtfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LRuxsvUE6MoetAym138Cb7YXTKAQg191Q+D+Hx23Pq4=; b=GTIDttXDpmTDrfePxyKejSoPra/uCkmjMDvCLAxgUjH+w5PK2BdyQqBaaG9h77iJCn Opo1G0sVGy+F20Wg21fkx6HXS0hZ6uGAXVb5xPvNSRJVDQlwxTy1nUlKAi83hxbTx+Mx q+s2X7NQJk9LFh318wx143+4KxXjVB+gxHTdlWTC3+Qou+e45qVQg8q9znqqn3My0izf Wv0mjfrpRn9835mLkpBwZqXCm5O2OLWeTpSxLjkDHFzaZ96jSSuSc856rL9kgxX/BKph QrPPIhNOn1NJN4qe6KBu1JBKuGwX/I5yYsWBJFl0J7g1xSBCnd9mZUlnRmJeBSf0QKsC 8GMQ== X-Gm-Message-State: APjAAAVm9srT8QbvVJYfCS2AnM/9yPRmCe10Z8skDbvWRPsPyj6OcEvR ZFFxzuAS8aK3IrxIQ4VNBBsA76GAab0j9A== X-Google-Smtp-Source: APXvYqyA4R0mRr3xtGFFnc76L/eakytyw4jUjPxSce7AvheD1XivyRvTNpOVja694eQUDVqztoz+Mw== X-Received: by 2002:a7b:ce09:: with SMTP id m9mr5028278wmc.49.1582907937046; Fri, 28 Feb 2020 08:38:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/33] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Date: Fri, 28 Feb 2020 16:38:19 +0000 Message-Id: <20200228163840.23585-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Sort this check to the start of a trans_* function. Merge this with any existing test for fpdp_v2. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200224222232.13807-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-vfp.inc.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index ff301650455..51d46f43027 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -717,7 +717,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_V= MRS *a) * VFPv2 allows access to FPSID from userspace; VFPv3 restricts * all ID registers to privileged access only. */ - if (IS_USER(s) && arm_dc_feature(s, ARM_FEATURE_VFP3)) { + if (IS_USER(s) && dc_isar_feature(aa32_fpsp_v3, s)) { return false; } ignore_vfp_enabled =3D true; @@ -746,7 +746,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_V= MRS *a) case ARM_VFP_FPINST: case ARM_VFP_FPINST2: /* Not present in VFPv3 */ - if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_VFP3)) { + if (IS_USER(s) || dc_isar_feature(aa32_fpsp_v3, s)) { return false; } break; @@ -1873,12 +1873,12 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_= VMOV_imm_sp *a) =20 vd =3D a->vd; =20 - if (!dc_isar_feature(aa32_fpshvec, s) && - (veclen !=3D 0 || s->vec_stride !=3D 0)) { + if (!dc_isar_feature(aa32_fpsp_v3, s)) { return false; } =20 - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { + if (!dc_isar_feature(aa32_fpshvec, s) && + (veclen !=3D 0 || s->vec_stride !=3D 0)) { return false; } =20 @@ -1923,7 +1923,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VM= OV_imm_dp *a) =20 vd =3D a->vd; =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + if (!dc_isar_feature(aa32_fpdp_v3, s)) { return false; } =20 @@ -1937,10 +1937,6 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_V= MOV_imm_dp *a) return false; } =20 - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2565,7 +2561,7 @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VC= VT_fix_sp *a) TCGv_ptr fpst; int frac_bits; =20 - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { + if (!dc_isar_feature(aa32_fpsp_v3, s)) { return false; } =20 @@ -2625,11 +2621,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_V= CVT_fix_dp *a) TCGv_ptr fpst; int frac_bits; =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { + if (!dc_isar_feature(aa32_fpdp_v3, s)) { return false; } =20 --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908309; cv=none; d=zohomail.com; s=zohoarc; b=FA3IBBFXypvAxTRIhzr0gHhszgoquL7sdJx1A/UAUvB6mQ/VUPe7OukPnKjgQ2qNhiefrIFhuCF8hsg6KBhqL/FC56+O16AyRZh7Nal6tSJDE/D9rxaquN8hZwjLEi9pRAP9Q2q7Q2QcG/Cpel2h9Mm+Q66FtujnLT+zN+N1cE4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908309; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YZu863NKaGXhWKWNne24xSYUgnIGai+DzFIAU+N7iSk=; b=NO/eiCj5yuZ9f6vqlE+YZc02FUymcNRSw/j4zcwncA+kFilt9MfNRj7X4wkxQ1Z2Pw45gsU+t27EA2yHnTH891f6q4qBwjyYDIAryI4eX+fmMWQ7RxD3QbdnCMsvDLUoMqF5GJvgAcCdZkUBnPqZMwxl73EXFKTCDoIrWIc2k2Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908309860160.04059074857946; Fri, 28 Feb 2020 08:45:09 -0800 (PST) Received: from localhost ([::1]:50380 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ilA-0003ET-B8 for importer@patchew.org; Fri, 28 Feb 2020 11:45:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56533) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifF-0007YQ-DR for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:02 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifD-0001uM-SI for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:01 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:34504) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifD-0001tw-Lg for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:38:59 -0500 Received: by mail-wm1-x342.google.com with SMTP id i10so8616502wmd.1 for ; Fri, 28 Feb 2020 08:38:59 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.38.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:38:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YZu863NKaGXhWKWNne24xSYUgnIGai+DzFIAU+N7iSk=; b=VBZoeXyQnZ8iR8499S2q6Oi+uI2sCSK1nAscoRW22bD+7JG3wx6FySvg9nlSl8X1n6 x+GVnb7mCAfm9pSK3ZJ+/l93LIYM1d+J8bEB3EAWtklLSFB1YeILL4+hMUyzbtrT5XCM wKzYJsncC/lYlovXCy3cCJPbwFvPWGIMD4Ud6EtpsjJ12zGBofSsDsUywCQjxzhYTwBj nklN+chPOU74CTtnN/vhkx78tX6lDj39Ub+IrgdulgQMMtk7fCuvfxSYX98Nlca6BdJH Xs/uvfHiYeVsKT2SblSf9jkOOmiqQ/MCGUlkllT90ebecVL4qnrxeStZ8I87Xxv/PxQW WgCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YZu863NKaGXhWKWNne24xSYUgnIGai+DzFIAU+N7iSk=; b=UK0WSmVas/dYa1yyoXkQkpSuA5pYKPOABHES0y091S5gRoM0sw1paIfg6SgyhaPO36 BdJKoXlv2TcqKzii4DL7Ck28ss99/TP77+BL4QAP6g6rMj2kkN6EbH7YCN5BE6Y3HWp1 cHwb8CUFRPPKs93wyU7jjPsseRuCmEEj9JHeNI9GpWQq21JBhbuDAB32NoaZ+MZtBAEX +Am4JXM+dEd9ylE96d/oN4hDNfQnok3VOz8txjWBuvF0ORNq3eUmJ9qBv6inAD1MfJEd 6uiS9AS5hZLJLWJ9NN0kiZxFrK+Ud1abA0yApgai+EIByzK+ftt/iTUGfagP8gNRHY5x 5H6Q== X-Gm-Message-State: APjAAAV2viAAsXBVYgoGF5ZCheT8UQlZJ9lZpmyf//6C5NK2TAzI5OMD IJIYQti8jlYtk746+BJH5f59iG4c4S5slg== X-Google-Smtp-Source: APXvYqyj/hjjEMXoHlKZwIADjKDOXPrP6HWnDHGOADUFV+hWLUPosbVmm1w+bwSJPDFGp86WuLlNnw== X-Received: by 2002:a1c:984a:: with SMTP id a71mr5799398wme.185.1582907938374; Fri, 28 Feb 2020 08:38:58 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/33] target/arm: Add missing checks for fpsp_v2 Date: Fri, 28 Feb 2020 16:38:20 +0000 Message-Id: <20200228163840.23585-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200224222232.13807-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-vfp.inc.c | 78 ++++++++++++++++++++++++++++++---- 1 file changed, 69 insertions(+), 9 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 51d46f43027..f88a95438fc 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -555,6 +555,13 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV= _to_gp *a) int pass; uint32_t offset; =20 + /* SIZE =3D=3D 2 is a VFP instruction; otherwise NEON. */ + if (a->size =3D=3D 2 + ? !dc_isar_feature(aa32_fpsp_v2, s) + : !arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { return false; @@ -564,10 +571,6 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV= _to_gp *a) pass =3D extract32(offset, 2, 1); offset =3D extract32(offset, 0, 2) * 8; =20 - if (a->size !=3D 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -614,6 +617,13 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VM= OV_from_gp *a) int pass; uint32_t offset; =20 + /* SIZE =3D=3D 2 is a VFP instruction; otherwise NEON. */ + if (a->size =3D=3D 2 + ? !dc_isar_feature(aa32_fpsp_v2, s) + : !arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { return false; @@ -623,10 +633,6 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VM= OV_from_gp *a) pass =3D extract32(offset, 2, 1); offset =3D extract32(offset, 0, 2) * 8; =20 - if (a->size !=3D 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -700,6 +706,10 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_= VMRS *a) TCGv_i32 tmp; bool ignore_vfp_enabled =3D false; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (arm_dc_feature(s, ARM_FEATURE_M)) { /* * The only M-profile VFP vmrs/vmsr sysreg is FPSCR. @@ -844,6 +854,10 @@ static bool trans_VMOV_single(DisasContext *s, arg_VMO= V_single *a) { TCGv_i32 tmp; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -873,6 +887,10 @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV= _64_sp *a) { TCGv_i32 tmp; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + /* * VMOV between two general-purpose registers and two single precision * floating point registers @@ -908,8 +926,12 @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV= _64_dp *a) =20 /* * VMOV between two general-purpose registers and one double precision - * floating point register + * floating point register. Note that this does not require support + * for double precision arithmetic. */ + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } =20 /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { @@ -946,6 +968,10 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VL= DR_VSTR_sp *a) uint32_t offset; TCGv_i32 addr, tmp; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -977,6 +1003,11 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_V= LDR_VSTR_dp *a) TCGv_i32 addr; TCGv_i64 tmp; =20 + /* Note that this does not require support for double arithmetic. */ + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; @@ -1013,6 +1044,10 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_= VLDM_VSTM_sp *a) TCGv_i32 addr, tmp; int i, n; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + n =3D a->imm; =20 if (n =3D=3D 0 || (a->vd + n) > 32) { @@ -1086,6 +1121,11 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_= VLDM_VSTM_dp *a) TCGv_i64 tmp; int i, n; =20 + /* Note that this does not require support for double arithmetic. */ + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + n =3D a->imm >> 1; =20 if (n =3D=3D 0 || (a->vd + n) > 32 || n > 16) { @@ -1234,6 +1274,10 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3Op= SPFn *fn, TCGv_i32 f0, f1, fd; TCGv_ptr fpst; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_fpshvec, s) && (veclen !=3D 0 || s->vec_stride !=3D 0)) { return false; @@ -1388,6 +1432,10 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2Op= SPFn *fn, int vd, int vm) int veclen =3D s->vec_len; TCGv_i32 f0, fd; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_fpshvec, s) && (veclen !=3D 0 || s->vec_stride !=3D 0)) { return false; @@ -2023,6 +2071,10 @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_= sp *a) { TCGv_i32 vd, vm; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + /* Vm/M bits must be zero for the Z variant */ if (a->z && a->vm !=3D 0) { return false; @@ -2466,6 +2518,10 @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_V= CVT_int_sp *a) TCGv_i32 vm; TCGv_ptr fpst; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2684,6 +2740,10 @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_V= CVT_sp_int *a) TCGv_i32 vm; TCGv_ptr fpst; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908181; cv=none; d=zohomail.com; s=zohoarc; b=Q84MRsBLIDSmUrUXLQHhC060Zol+DLirviDy95rs6GS2AIASS0QuyCZ1yLo2ervnI3zhJeaAQpGIbTXdAa4f5+wSU2pLcXeJxZFce95K8dU2ugzNBP/mw4EEjL1770cB/dhDGoIcMlqOlln6C7bioVNxTgdK0KxewQGiV34VVL8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908181; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jvv1988l+MhveUC13kevwwKHJA6IhCtxQBKlOzO9REg=; b=ASUBg+ynVNCNAKTFtkT06BTbLtYtHIGd8tbu3Wl24lbI93AiAJ46YHCydW9TTUrzJ+foL3jNlq9SY7q0bIQj8tlY8X90wLFauXMPb011AjQ6WBAUUFgzQAnf+u8OqZVx9KRDx8g6dnztLM1zBK9EWTOTyM+BUrH+QsWjlrw2Jjc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908181187102.45803898622171; Fri, 28 Feb 2020 08:43:01 -0800 (PST) Received: from localhost ([::1]:50248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ij6-0007Ui-06 for importer@patchew.org; Fri, 28 Feb 2020 11:43:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56544) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifG-0007aB-72 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifE-0001v1-RY for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:02 -0500 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:39224) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifE-0001uT-Kw for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:00 -0500 Received: by mail-wr1-x42d.google.com with SMTP id y17so3670815wrn.6 for ; Fri, 28 Feb 2020 08:39:00 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.38.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:38:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=jvv1988l+MhveUC13kevwwKHJA6IhCtxQBKlOzO9REg=; b=iO7pGM6vHbpoUcRx2yCWAvXtxsR4l+11Fh4bm0GhEjJDB7fO0MV35ukOqDlIAEWN+C tRgD1IGgp9gSek+qahQulVpuSLrAEuuituWPdz7BEOVoYxR5d+hd80Jwv7XLhdpKdQ76 8nMLlKY5ieXl6m+16HZWL2Fu0ZYIr1JGHGpGD/mxPLsiEY3Ydhi2lBbqephqgCg9QW3j soVZsQp5WVO37vHmWQJupkYQ8laknHNyvUgftHK8TH+B0gk8WFEqu8EJYqypzF9xQpOd tQc/bgDGTeqOkwo7Sf/1TPH4v/CF7A2VWsgGxSHRK1/LLTVWCsJeI9mtFj8hoKPZJGbm ly8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jvv1988l+MhveUC13kevwwKHJA6IhCtxQBKlOzO9REg=; b=sxUKMUp+ZCD8G5+8svLoD8AWtzIH7iJBlR2b0vKC2qOS+zrj28nahHV9aqf83HEJ1u RatO4KMrsmrN2B0+oy8Y0JlrrV/P6T1YG/NiNxcFIVzCfrLREVVYqbLMkXDcxXSQqIwZ VTaJyMY1vDmJw6XVFB9zSqmQ0Cv2IHHW8ie+LkmlhpYNEneOi8C3c+k8N+AazP+MM4tQ HqCvyJanbfU5bYzMXDmOGtmJKXnPem2QwrSOOKFq28ZFfmVlhjZa4mh/rlQNcE4VyD0+ BeD3XxwCwsOcpdZMlifrBrlEngR2V1r6+EuXcTVPW5h2rNKDkrBw8H4Vp8YCAI4+9CbY ULEA== X-Gm-Message-State: APjAAAUn7fjpbYPICV/UbJHkIIIDcDz+aUDQl0xgKklpjRRt1QIaFiMI EFK+yj46hIH7p2kY+JCg93Bhb7iaXVqTiw== X-Google-Smtp-Source: APXvYqzM7uROXKdlxY8Pczv1StD86gWuHdFMz4bPNrX3XcmXSJxMlUz7W2kypPrOKGx3Zx7ZbIQR3g== X-Received: by 2002:adf:f012:: with SMTP id j18mr5550390wro.314.1582907939349; Fri, 28 Feb 2020 08:38:59 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/33] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac Date: Fri, 28 Feb 2020 16:38:21 +0000 Message-Id: <20200228163840.23585-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson All remaining tests for VFP4 are for fused multiply-add insns. Since the MVFR1 field is used for both VFP and NEON, move its adjustment from the !has_neon block to the (!has_vfp && !has_neon) block. Test for vfp of the appropraite width alongside the test for simdfmac within translate-vfp.inc.c. Within disas_neon_data_insn, we have already tested for ARM_FEATURE_NEON. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20200224222232.13807-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 12 ++++++++++++ target/arm/cpu.c | 6 +++++- target/arm/translate-vfp.inc.c | 22 ++++++++++++++++++---- target/arm/translate.c | 2 +- 4 files changed, 36 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b94d2a5ace4..b29b0eddfc3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3514,6 +3514,18 @@ static inline bool isar_feature_aa32_fp16_dpconv(con= st ARMISARegisters *id) return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; } =20 +/* + * Note that this ID register field covers both VFP and Neon FMAC, + * so should usually be tested in combination with some other + * check that confirms the presence of whichever of VFP or Neon is + * relevant, to avoid accidentally enabling a Neon feature on + * a VFP-no-Neon core or vice-versa. + */ +static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) +{ + return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) !=3D 0; +} + static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) { return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 1; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5be4c258096..dc45865c7a7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1512,7 +1512,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) u =3D FIELD_DP32(u, MVFR1, SIMDINT, 0); u =3D FIELD_DP32(u, MVFR1, SIMDSP, 0); u =3D FIELD_DP32(u, MVFR1, SIMDHP, 0); - u =3D FIELD_DP32(u, MVFR1, SIMDFMAC, 0); cpu->isar.mvfr1 =3D u; =20 u =3D cpu->isar.mvfr2; @@ -1535,6 +1534,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) u =3D cpu->isar.mvfr0; u =3D FIELD_DP32(u, MVFR0, SIMDREG, 0); cpu->isar.mvfr0 =3D u; + + /* Despite the name, this field covers both VFP and Neon */ + u =3D cpu->isar.mvfr1; + u =3D FIELD_DP32(u, MVFR1, SIMDFMAC, 0); + cpu->isar.mvfr1 =3D u; } =20 if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index f88a95438fc..03ba8d7aac0 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1803,11 +1803,18 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_s= p *a) =20 /* * Present in VFPv4 only. + * Note that we can't rely on the SIMDFMAC check alone, because + * in a Neon-no-VFP core that ID register field will be non-zero. + */ + if (!dc_isar_feature(aa32_simdfmac, s) || + !dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + /* * In v7A, UNPREDICTABLE with non-zero vector length/stride; from * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A. */ - if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || - (s->vec_len !=3D 0 || s->vec_stride !=3D 0)) { + if (s->vec_len !=3D 0 || s->vec_stride !=3D 0) { return false; } =20 @@ -1861,11 +1868,18 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_d= p *a) =20 /* * Present in VFPv4 only. + * Note that we can't rely on the SIMDFMAC check alone, because + * in a Neon-no-VFP core that ID register field will be non-zero. + */ + if (!dc_isar_feature(aa32_simdfmac, s) || + !dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + /* * In v7A, UNPREDICTABLE with non-zero vector length/stride; from * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A. */ - if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || - (s->vec_len !=3D 0 || s->vec_stride !=3D 0)) { + if (s->vec_len !=3D 0 || s->vec_stride !=3D 0) { return false; } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 79880adaad2..0489e0cdaa6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5150,7 +5150,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) } break; case NEON_3R_VFM_VQRDMLSH: - if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) { + if (!dc_isar_feature(aa32_simdfmac, s)) { return 1; } break; --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908699; cv=none; d=zohomail.com; s=zohoarc; b=Cr0XCVmGhx/M3fcRnmqzkNjwWwidmXvJbfHa5QXMq9gZn4GS+CMJz6m2pMQvFA0rTMk9QA2BYaN9hjEYCB5ps8zjNt6Mf/xJaTJJv7M/3JJOH+QfCrwcUrNwraFHxJjM0rJDUGP+TP4Yf7QCE1/qHLbv56rTDCpKUYy+6aDkyXQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908699; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TTuud3NM/HeI5fDHZvld7c2Fw5CE+eUly98+A8SwQ5c=; b=Ie34GvtSozNK8qbjEwRAopJ0d74EjSQAgIH6cZ9TGLtogjFgduksn9FtcdS7+8FeiQed8Q/S9ktRpJl5FOomc68el9/DgemQ1lskQEutOhZeCaGbL40f7QvDVk1IVbQx6oSb8sRFErnN9GU/mtxLDquBbz7RWdITJCtUz8moiI0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908699540433.6424331627004; Fri, 28 Feb 2020 08:51:39 -0800 (PST) Received: from localhost ([::1]:50632 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7irS-000574-0F for importer@patchew.org; Fri, 28 Feb 2020 11:51:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56555) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifG-0007bY-QS for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:03 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifF-0001vX-R7 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:02 -0500 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:46716) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifF-0001v6-Ku for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:01 -0500 Received: by mail-wr1-x42a.google.com with SMTP id j7so3594841wrp.13 for ; Fri, 28 Feb 2020 08:39:01 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.38.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:38:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=TTuud3NM/HeI5fDHZvld7c2Fw5CE+eUly98+A8SwQ5c=; b=Y6jTuK4S1tCNjjFkQ6g8ohlK3ruxxYhkpDTcnknw2KWYXDDbB0zCtAcrStuF6Q/mQ7 wg3PqpGOnA1yY2s+KvJCu4hbgG7Nfi9R9E61Mn/leGj6QLnSW+Iog2LmtYPDYymZnaT3 D6Hu4B6NmFYl0NE5RCCfDafmGgJYdaz474hV+wpATNu2Aahg5IfzvAMO8M/jsaVQVK16 qMLAffEH72tQoCeaK5aCPTu2szuAUt1ukbfyIvPXfOTN6bug/LmrvLV23baKc9ME9h4N fGfLqFOR+5cO6Q8AkPS/qBj4K5xaTRSPxwzKdXAgy2utmVnUXHbk0Zg0Mz7vlCHrwzSD DdKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TTuud3NM/HeI5fDHZvld7c2Fw5CE+eUly98+A8SwQ5c=; b=OamJRqJO9AGc5zw/i22lN9rtXtkckypJme3bU3jXOqRloVVU8k1aTLHnXP5KdgK05p Tad62HAs6flOO5N7k4keOnPCgpBjv9za8vYhZy7WuiF9sD2YgKuyNWUCWDjRTeLro4gE 1mVzTg5X32WFePXKAq+nB0W9fIEILhqcM3LoupNceyIKy9sctbTzsasVgEA/2mZcm99g LJW6QAIJEVWz1PCh1B/MZ8Xk3PYwPDd2Uv/cPbJittL30U2IwWKwqsyym9+SJrahdq0y PXLfO/O0x2sg7IE0LXuo5ghUs60/2Ztq8Ok6cTDa+jsC4VmY1EQpNq0obhtESq48qR0G BewA== X-Gm-Message-State: APjAAAW+8GLHpRv1m7sd82blVPKI+X5dXxeH9/QkpxDN504JXRKwdMHu SqTwZyXciA8gIbpRZoLwPyZ88FoKCEmGYQ== X-Google-Smtp-Source: APXvYqyxcd00KVMLSg4G0ioAfwoHA/BAd7SNd6I6bW4aYkCVeQxCyhnF62L2QymNnf/Ef/nHeQuSMw== X-Received: by 2002:adf:afc9:: with SMTP id y9mr5579811wrd.346.1582907940439; Fri, 28 Feb 2020 08:39:00 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/33] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn Date: Fri, 28 Feb 2020 16:38:22 +0000 Message-Id: <20200228163840.23585-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42a X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We now have proper ISA checks within each trans_* function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200224222232.13807-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 0489e0cdaa6..893911fca70 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2652,10 +2652,6 @@ static void gen_neon_dup_high16(TCGv_i32 var) */ static int disas_vfp_insn(DisasContext *s, uint32_t insn) { - if (!arm_dc_feature(s, ARM_FEATURE_VFP)) { - return 1; - } - /* * If the decodetree decoder handles this insn it will always * emit code to either execute the insn or generate an appropriate --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908818; cv=none; d=zohomail.com; s=zohoarc; b=IA/uxFRHM0qbQfNmJn+NvGp/ZQ/K9A9Ju4IPpJRds+7V+sICDTSn+lB2BBN/afpndU+VJ/3iSGr9ed5QPj1rjtxr0K7aE431BzCsTUmBBfLf4YtJJg7ytaoHImCaUJ3umajd/2gw+xqPZnwLw4VdqFxYkXyxX8lMRUI02QsCmVw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908818; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eSnuWh5zos/20PohnmnqFwoVE6VjZG74my10MbXx4a8=; b=TaJQqzOljchi5JAbhTb8Scr1h1hdM5jq7z8Ms4/Bk8EJ56bJZwsLY8cNCqg3KaBD7xisU3ZwDkhtYfP1CZApRdKFEF8K88f0pKFjX4feNv/M9LMXAimXyMuMCThEDCqBIjcU1u6G+fcJAUxdoh3Wzd6sP8g7RZcmMyn9fxza9fA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908818435406.72271073969875; Fri, 28 Feb 2020 08:53:38 -0800 (PST) Received: from localhost ([::1]:50672 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7itN-00007m-5q for importer@patchew.org; Fri, 28 Feb 2020 11:53:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56581) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifI-0007gW-Ai for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifG-0001wN-S3 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:04 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:37790) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifG-0001vj-Lp for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:02 -0500 Received: by mail-wr1-x436.google.com with SMTP id l5so3681536wrx.4 for ; Fri, 28 Feb 2020 08:39:02 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.39.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:39:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=eSnuWh5zos/20PohnmnqFwoVE6VjZG74my10MbXx4a8=; b=eC90pNS4MpNXEqzseUx4VTjCvGMYt0OXlFCG+IACn9Wwix+E2YKxbNTIudTw8O91QJ emZ9oxbuWEimFDteHAhd5YOXUmLMugkDGjsiC/OQvaWeh6xYmBh7FNRTT3v2TjKsqXwx wX2SXfM/D+x4FlSBTba1ydhkS9valfgiTrL+Cxh83A7wag5LvTomdVLtl5KtLVM3FzFx JQQ2DnYYRkQvqJ1yWawt39toCDj3Ht5zxfEJ8TUlkVC9FSOgWrNNPzwitIkUkoHAvIIK RbhaDzWsMzCturzgXFrX8dY3jwRGsslxYtO0JSr77XEE66yYZRX5iZ3Te/fjFTVhdZ5l 5ppQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eSnuWh5zos/20PohnmnqFwoVE6VjZG74my10MbXx4a8=; b=NdF3NuJTDLIZJfEni5KED7skksvrU6xWzrY/I7aiI4pcWZtzCdoQD3nM3bIKFgZsoy TcQLcFcYcoKxnRZob00G4yaHzqzssad5s1yHIhP+11YttRFV7nH9+/TNnVbdBBulRKGL DPmW4OelI+Yv2QhdA7ivI2OO/s/cS+wKiqSQhLctlsB16rbBz3EC1H5Du5m7hJ69AZcI QTh4+spj3zgNE2C8dTygR8zFqyemULgRXhxP2a981waRsQ2PG6lVOsrqpElO/Qn+Pv+P 4hIviBlkUWQvbd6YglcS/FxqESS3A9QvgELYwmz+3T8YfJjIAsLOBo0xQU6FfgTX41b1 k38w== X-Gm-Message-State: APjAAAV8rGca/WIqEx44OWy+8ztSn2WFRhcdaTwdGXE9SpQ5DRMUiFU1 K9Z40ZANG94R/iAE1x8cA/zj3SIzjuc32Q== X-Google-Smtp-Source: APXvYqzMasEKTjb7UmRnJZpUnoOS8R+TyRR2juQOnCBGbL1pAsTF1MzgGaBgEhFkbh/i1KOMQo8kMQ== X-Received: by 2002:a05:6000:1083:: with SMTP id y3mr5256674wrw.146.1582907941458; Fri, 28 Feb 2020 08:39:01 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/33] target/arm: Move VLLDM and VLSTM to vfp.decode Date: Fri, 28 Feb 2020 16:38:23 +0000 Message-Id: <20200228163840.23585-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::436 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Now that we no longer have an early check for ARM_FEATURE_VFP, we can use the proper ISA check in trans_VLLDM_VLSTM. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20200224222232.13807-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-vfp.inc.c | 39 +++++++++++++++++++++++++ target/arm/translate.c | 53 ++++++---------------------------- target/arm/vfp.decode | 2 ++ 3 files changed, 50 insertions(+), 44 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 03ba8d7aac0..1964af3ea5e 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -2828,3 +2828,42 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_V= CVT_dp_int *a) tcg_temp_free_ptr(fpst); return true; } + +/* + * Decode VLLDM and VLSTM are nonstandard because: + * * if there is no FPU then these insns must NOP in + * Secure state and UNDEF in Nonsecure state + * * if there is an FPU then these insns do not have + * the usual behaviour that vfp_access_check() provides of + * being controlled by CPACR/NSACR enable bits or the + * lazy-stacking logic. + */ +static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) +{ + TCGv_i32 fptr; + + if (!arm_dc_feature(s, ARM_FEATURE_M) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + /* If not secure, UNDEF. */ + if (!s->v8m_secure) { + return false; + } + /* If no fpu, NOP. */ + if (!dc_isar_feature(aa32_vfp, s)) { + return true; + } + + fptr =3D load_reg(s, a->rn); + if (a->l) { + gen_helper_v7m_vlldm(cpu_env, fptr); + } else { + gen_helper_v7m_vlstm(cpu_env, fptr); + } + tcg_temp_free_i32(fptr); + + /* End the TB, because we have updated FP control bits */ + s->base.is_jmp =3D DISAS_UPDATE; + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 893911fca70..5b7cad1ea2d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10962,53 +10962,18 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) goto illegal_op; /* op0 =3D 0b11 : unallocated */ } =20 - /* - * Decode VLLDM and VLSTM first: these are nonstandard because: - * * if there is no FPU then these insns must NOP in - * Secure state and UNDEF in Nonsecure state - * * if there is an FPU then these insns do not have - * the usual behaviour that disas_vfp_insn() provides of - * being controlled by CPACR/NSACR enable bits or the - * lazy-stacking logic. - */ - if (arm_dc_feature(s, ARM_FEATURE_V8) && - (insn & 0xffa00f00) =3D=3D 0xec200a00) { - /* 0b1110_1100_0x1x_xxxx_xxxx_1010_xxxx_xxxx - * - VLLDM, VLSTM - * We choose to UNDEF if the RAZ bits are non-zero. - */ - if (!s->v8m_secure || (insn & 0x0040f0ff)) { + if (disas_vfp_insn(s, insn)) { + if (((insn >> 8) & 0xe) =3D=3D 10 && + dc_isar_feature(aa32_fpsp_v2, s)) { + /* FP, and the CPU supports it */ goto illegal_op; + } else { + /* All other insns: NOCP */ + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), + default_exception_el(s)); } - - if (arm_dc_feature(s, ARM_FEATURE_VFP)) { - uint32_t rn =3D (insn >> 16) & 0xf; - TCGv_i32 fptr =3D load_reg(s, rn); - - if (extract32(insn, 20, 1)) { - gen_helper_v7m_vlldm(cpu_env, fptr); - } else { - gen_helper_v7m_vlstm(cpu_env, fptr); - } - tcg_temp_free_i32(fptr); - - /* End the TB, because we have updated FP control bits= */ - s->base.is_jmp =3D DISAS_UPDATE; - } - break; } - if (arm_dc_feature(s, ARM_FEATURE_VFP) && - ((insn >> 8) & 0xe) =3D=3D 10) { - /* FP, and the CPU supports it */ - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } - break; - } - - /* All other insns: NOCP */ - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized= (), - default_exception_el(s)); break; } if ((insn & 0xfe000a00) =3D=3D 0xfc000800 diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index a67b3f29ee5..592fe9e1e42 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -242,3 +242,5 @@ VCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 = .... \ vd=3D%vd_sp vm=3D%vm_sp VCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \ vd=3D%vd_sp vm=3D%vm_dp + +VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000 --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908982; cv=none; d=zohomail.com; s=zohoarc; b=ZpvBMmeHoSHtlcdmBfpdbbIu5XKL/Pjqp1qz2+oj/aPz8fraD7wyCmEEf9awYl6lmA1sUDeJDm8ZV6XhLABcUqtNnZB/SBlfpUtkWPu7580TOM5DWYHT7a59CYYbLlzJi4j0KA4aT4Y/YiluhIdv2055AkVXi4xg9rEUDB8SEe0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908982; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/fspnfbWHr/iEc26cj3LysOXZAm0hum7R0BOuileGqY=; b=bU+e3W/nh73db3OdAyr+ItoVGt2es7OPk/1I/0bqwXYcyRAmMA63mu0iafGhXts+ZDqbOs/CkruQp9BNQcyTgaSZYZVuclorCfpZ0Cs7hnF5BPv43PLAYYu9DfKnTAKqeZc24Sk5GRhDYjXY2PAGH1UW5cKF73ypvJf4ZgCiNSU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908982110329.65968138457515; Fri, 28 Feb 2020 08:56:22 -0800 (PST) Received: from localhost ([::1]:50754 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7iw0-0003y9-Kf for importer@patchew.org; Fri, 28 Feb 2020 11:56:20 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56596) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifJ-0007ju-Gl for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifH-0001x6-U4 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:05 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:40079) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifH-0001wY-No for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:03 -0500 Received: by mail-wm1-x32d.google.com with SMTP id d138so2303904wmd.5 for ; Fri, 28 Feb 2020 08:39:03 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.39.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:39:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/fspnfbWHr/iEc26cj3LysOXZAm0hum7R0BOuileGqY=; b=Z3TDQLEnn2KAhrI5sZeL3qfZxJrRZhngXm27pLNarxuobTbmtUXL07LrnPuhATd2NB veibm57iaNXkRDrrmgneS+5t8DX15408H6sEQL36gzuR6cy93fc+rF9C33XGwtj3CB7X cOo4dH4XoT8iyMvL8ztOGh4QIT93CboIPICNxvJYP80i3PxRdYq4Gyaz4ObaXQOhRh2I 1UL/Lo7jU7kuuWapEaVdWvLKkGrL2YFT2gzUXRBgC9HQmFZZLPeI9+FortsYDWgdplui GWyZU2FKPYZ+JVRYTAQW4oPsWbQrogksSN6Yyl6pIaOxKrZHAYZM2jbSv/9O7hnigPy7 rlPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/fspnfbWHr/iEc26cj3LysOXZAm0hum7R0BOuileGqY=; b=XXFbWrOXQu8KiAjE+72jFX/acYTEw+3p+8oXlw1mlOn3IrfviKyuEL53tZeiq/mewI bjMGigx4XKdI1ZWorP1L0ZBtvhcSyPXgKYErUpi1GffgfXlvqqqCi6hKEtxtXc1HrhmE tc1mI3n7MSu+sPvzNA94aB2N6P29RGOdsa7lqLit1heirKT6hrO3y1jck1ZyXnzOXZDB QWT20uFAz0xcV4AnEbsxHB4LNVyiD3DmlUSXxDIysmj2Bf7pkGagLxCIJ+buQ7Iy1l4n Vz19kJFfb2PZ6Si37Oer7YuOwmgKkhX6qjI4hebftj5v48olfUVLH03lE7gidv3aYan4 CAQQ== X-Gm-Message-State: APjAAAWR9nbjJAhdqzYdbrlt0v5qCNXU4KL9L8kv2URwI2WKedpkaeLt tziGNLAFttY+Z65nqr0nKyZsNdzFUaj1+g== X-Google-Smtp-Source: APXvYqyIV/o92HQoNA1SwD3Fbi4Bmmp7bKwD0yiU6Q6KoSW/RJpweLxWxxdfI+xIE2FJ3F9qtPelAA== X-Received: by 2002:a1c:48c1:: with SMTP id v184mr5517173wma.5.1582907942412; Fri, 28 Feb 2020 08:39:02 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/33] target/arm: Move the vfp decodetree calls next to the base isa Date: Fri, 28 Feb 2020 16:38:24 +0000 Message-Id: <20200228163840.23585-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Have the calls adjacent as an intermediate step toward actually merging the decodes. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20200224222232.13807-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate.c | 83 +++++++++++++++--------------------------- 1 file changed, 29 insertions(+), 54 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 5b7cad1ea2d..6259064ea7c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2646,31 +2646,6 @@ static void gen_neon_dup_high16(TCGv_i32 var) tcg_temp_free_i32(tmp); } =20 -/* - * Disassemble a VFP instruction. Returns nonzero if an error occurred - * (ie. an undefined instruction). - */ -static int disas_vfp_insn(DisasContext *s, uint32_t insn) -{ - /* - * If the decodetree decoder handles this insn it will always - * emit code to either execute the insn or generate an appropriate - * exception; so we don't need to ever return non-zero to tell - * the calling code to emit an UNDEF exception. - */ - if (extract32(insn, 28, 4) =3D=3D 0xf) { - if (disas_vfp_uncond(s, insn)) { - return 0; - } - } else { - if (disas_vfp(s, insn)) { - return 0; - } - } - /* If the decodetree decoder didn't handle this insn, it must be UNDEF= */ - return 1; -} - static inline bool use_goto_tb(DisasContext *s, target_ulong dest) { #ifndef CONFIG_USER_ONLY @@ -10778,7 +10753,9 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) ARCH(5); =20 /* Unconditional instructions. */ - if (disas_a32_uncond(s, insn)) { + /* TODO: Perhaps merge these into one decodetree output file. */ + if (disas_a32_uncond(s, insn) || + disas_vfp_uncond(s, insn)) { return; } /* fall back to legacy decoder */ @@ -10805,13 +10782,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) } return; } - if ((insn & 0x0f000e10) =3D=3D 0x0e000a00) { - /* VFP. */ - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } - return; - } if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10842,7 +10812,9 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) arm_skip_unless(s, cond); } =20 - if (disas_a32(s, insn)) { + /* TODO: Perhaps merge these into one decodetree output file. */ + if (disas_a32(s, insn) || + disas_vfp(s, insn)) { return; } /* fall back to legacy decoder */ @@ -10852,11 +10824,10 @@ static void disas_arm_insn(DisasContext *s, unsig= ned int insn) case 0xd: case 0xe: if (((insn >> 8) & 0xe) =3D=3D 10) { - /* VFP. */ - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } - } else if (disas_coproc_insn(s, insn)) { + /* VFP, but failed disas_vfp. */ + goto illegal_op; + } + if (disas_coproc_insn(s, insn)) { /* Coprocessor. */ goto illegal_op; } @@ -10945,7 +10916,14 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) ARCH(6T2); } =20 - if (disas_t32(s, insn)) { + /* + * TODO: Perhaps merge these into one decodetree output file. + * Note disas_vfp is written for a32 with cond field in the + * top nibble. The t32 encoding requires 0xe in the top nibble. + */ + if (disas_t32(s, insn) || + disas_vfp_uncond(s, insn) || + ((insn >> 28) =3D=3D 0xe && disas_vfp(s, insn))) { return; } /* fall back to legacy decoder */ @@ -10962,17 +10940,15 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) goto illegal_op; /* op0 =3D 0b11 : unallocated */ } =20 - if (disas_vfp_insn(s, insn)) { - if (((insn >> 8) & 0xe) =3D=3D 10 && - dc_isar_feature(aa32_fpsp_v2, s)) { - /* FP, and the CPU supports it */ - goto illegal_op; - } else { - /* All other insns: NOCP */ - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), - default_exception_el(s)); - } + if (((insn >> 8) & 0xe) =3D=3D 10 && + dc_isar_feature(aa32_fpsp_v2, s)) { + /* FP, and the CPU supports it */ + goto illegal_op; + } else { + /* All other insns: NOCP */ + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), + default_exception_el(s)); } break; } @@ -10995,9 +10971,8 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) goto illegal_op; } } else if (((insn >> 8) & 0xe) =3D=3D 10) { - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } + /* VFP, but failed disas_vfp. */ + goto illegal_op; } else { if (insn & (1 << 28)) goto illegal_op; --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908298; cv=none; d=zohomail.com; s=zohoarc; b=IWRH9ufZiPIlUwKELGW/C5Tk5CUozG85CZfFf3EEm8LMq+I9QNUB35gyKn/nsVJNNJhR6wptEKfHhJz6uv8NA5VF5tO0/HUNRecBMjb5c2IYspoJtA8kXSQcLPqwD2yFgdHWa08Oyvnbn5XT7Vw6PftOygo1jI5BB58m4Y5lXw4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908298; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/szCr71Fa7E6rI1eZ/F7YIIPt2UZ+jHQ1gjDewWxJ5c=; b=KxmcUsapLcbO9QAFTKy2I6McwUY6FaPaxvGNEMNyynqX8eZ6nk2KFIKkbqKoHyjDKsh0SXZuYzaDXbWLVG8Fn5k53XT8lIEwGOnyzlHhfI5MS3WuEDdSqx6DfpDEv62cWJgxPgBlY8wwr8k5Do12muKnN36As0YvnBp4g4Ekwy4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908298378943.4042503357213; Fri, 28 Feb 2020 08:44:58 -0800 (PST) Received: from localhost ([::1]:50324 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ikz-0002jq-4U for importer@patchew.org; Fri, 28 Feb 2020 11:44:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56600) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifK-0007lJ-1M for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifI-0001xe-TV for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:05 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:35689) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifI-0001xE-Mq for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:04 -0500 Received: by mail-wr1-x443.google.com with SMTP id r7so3699343wro.2 for ; Fri, 28 Feb 2020 08:39:04 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.39.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:39:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/szCr71Fa7E6rI1eZ/F7YIIPt2UZ+jHQ1gjDewWxJ5c=; b=qRTNhp6psz1En8zws8pb8ZlK5HXWzKliohebiQ7UbEAoUvLi1fsTcfUz2208sBZGxa Ojk0p2TaV26D5L7MDnPqcpM1IxPnx3AFBWzYOtivzcDIqzEXeB/B9iwBpSjlZ36ehTwA BucaYFDcSAzZdLH3WvG/F0gGi2t6Yr44GN7wwpaXXIJC8rf7KPDtea+L83pU3eSKWOlv hdSB51C1LB5UnIScYo/ShPMgDBm4BiKu/xSEyhfdNyXS58pV8dwmcgpeGzw795mz9x9j W9gk88dbhQ7PbekKotM7PLuho6P3ipDewzMHfz5Yr+fC2bKEBsv/th2/nL+4fNnWfJCa 1mbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/szCr71Fa7E6rI1eZ/F7YIIPt2UZ+jHQ1gjDewWxJ5c=; b=T0yliuYTZqK6unM/aejvlGDzrTrPVcU02Idm6oxyVDaNDKgxeVE3UziRxoPzWDwPhG k5wwrCNQiqloHmJk8YJ+l/KMNjdXgWMb06XJ6QNMhH6wVGG2V3HruJl5utFDzxY7NhPG 6YzolKp+xMCImJUXC5DsDiylqR4vhz0FAOjG/zxYYmwypgDmbKUbbd6qqYz78mh/HCve w1Hu8c6vdlAK14uQ+560G+X8Q8JPKrKuA0yZazr1huu/SG64NtI10YzxcbfKGT1tBcxl pFJW3VESSQBP393V2gCyymohT4anUJRn7Y5itu+Hbp1lLwcQGa+eRLbsWOyQlrjjQ4u4 DdTQ== X-Gm-Message-State: APjAAAX4JHZ8e5lFaEjhoAfkEfIUYg3aUlFF6G10FnUMZ5YqfCKuAFZZ Y7w1l0c3XvXHE0pYE4HIUiO2O4kPZ0Y4Ug== X-Google-Smtp-Source: APXvYqxpcvE+fFUvwvyH0hTV/yu2pwT9k9wq6bUoskSAjptK6REq6k1oOgjBFDicdsMjytt90HFyVQ== X-Received: by 2002:a5d:518b:: with SMTP id k11mr5816991wrv.114.1582907943447; Fri, 28 Feb 2020 08:39:03 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/33] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP Date: Fri, 28 Feb 2020 16:38:25 +0000 Message-Id: <20200228163840.23585-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use isar feature tests instead of feature bit tests. Although none of QEMUs current cpus have VFPv3 without D32, replace the large comment explaining why with one line that sets ARM_HWCAP_ARM_VFPv3D16 under the correct conditions. Mirror the test sequence used in the linux kernel. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20200224222232.13807-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- linux-user/elfload.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index b1a895f24ce..86cda127b78 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -468,22 +468,25 @@ static uint32_t get_elf_hwcap(void) =20 /* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */ GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); - GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP); GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); - GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); - GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4); + GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE); GET_FEATURE_ID(aa32_arm_div, ARM_HWCAP_ARM_IDIVA); GET_FEATURE_ID(aa32_thumb_div, ARM_HWCAP_ARM_IDIVT); - /* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.= c. - * Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of - * ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated - * to our VFP_FP16 feature bit. - */ - GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPD32); - GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE); + GET_FEATURE_ID(aa32_vfp, ARM_HWCAP_ARM_VFP); + + if (cpu_isar_feature(aa32_fpsp_v3, cpu) || + cpu_isar_feature(aa32_fpdp_v3, cpu)) { + hwcaps |=3D ARM_HWCAP_ARM_VFPv3; + if (cpu_isar_feature(aa32_simd_r32, cpu)) { + hwcaps |=3D ARM_HWCAP_ARM_VFPD32; + } else { + hwcaps |=3D ARM_HWCAP_ARM_VFPv3D16; + } + } + GET_FEATURE_ID(aa32_simdfmac, ARM_HWCAP_ARM_VFPv4); =20 return hwcaps; } --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582909103; cv=none; d=zohomail.com; s=zohoarc; b=LK/wIDwKVe/2q30IdA2L/lFmIwuRniigetCP98C6LH0V+ns41hOL18tLir/wv1rvjpcg6ES9P/AxNtgkyOL0pRu+OhBHTW2gRWdBPmkLPuZDCTC2bRkbKPgHhkuygftcmxbBImRNdvy7rTjwU+GONoX9PdN+eYRHhyXwipT+b5Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582909103; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Li0UuQunOn+1b7qXuee2MpCV0HZHZNa8ULuV4VqSjn8=; b=CiLxg0fPXFncExkcZAcZqhT80xqb/om/ejxICpQKeraYjcdgOxBvYPULyryCdobbtMcJsc4DywTiETxtvBSNRCeVRpFthI6NpvrvcSkmg8YekGr/KhYYn7vBgibLD6+nLLHHbt2hOYiZONliYsP66g9BqVvOGJLae+l8tSBIQNU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582909103396176.22829279716314; Fri, 28 Feb 2020 08:58:23 -0800 (PST) Received: from localhost ([::1]:50796 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ixy-0007iM-66 for importer@patchew.org; Fri, 28 Feb 2020 11:58:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56620) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifN-0007tD-0b for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifK-0001yj-QS for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:08 -0500 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:52828) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifK-0001yH-J0 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:06 -0500 Received: by mail-wm1-x336.google.com with SMTP id p9so3856107wmc.2 for ; Fri, 28 Feb 2020 08:39:06 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.39.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:39:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Li0UuQunOn+1b7qXuee2MpCV0HZHZNa8ULuV4VqSjn8=; b=UKqo9iVSitRHWZURRI1pFbDNnKB18/hrLd1Kf/tZm9OEiaj6UrvkFkhfZnHThFDf0d RlT5TESIKzdHdwzDUTp2UXubH2D4F+QdF/edesskaGRo9pCnhTmcKLnEdHBWh0byHAra t4B40GkEmN3Zc7c16zQIGwPtpzk6hwHS9eBYiNN8VCZi8rzp1tL6GHLvJKn9Vy0jY62p zqcCdWNdjsX5QO6wNqSijZnWXJ/rxnAQdt430HjAYgPe7o5ISqF5fBKM6CHBo6WOocZr EWNEg8y6ooNJeBSOZRFbXRqkO24qkPC0cxNuMDVF6Z2GHxS+RQ/cvHC+ikOp0Xmn9NS3 T9CQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Li0UuQunOn+1b7qXuee2MpCV0HZHZNa8ULuV4VqSjn8=; b=PzOkciJizfon9KAAQ/ZR8j8wrfiYpdG85ONaqCN6SZ/OUMJiPqtlODUG4Wt8KOFZDL zhDSEIn/P6GaGs+gUCD2N1W+jTCmAVrXK2pQagoQKjGTBOwt2H/hAPXxpDOXbaVhCkfP u5m56YcgIhNl7Y3Sza1T0BBw7mvjJ9jqPhuG8AP+R2BQVktWrEbhVzXj0VB3Wt2EDqsV MXFAKLWWY/0o44Bc5JqGVLibyR3K4A/bQz7T/Rpo4Wnrht8Czj/bOYeYVwfUK48yeMAJ UhR/f/tccJOU0TPCHDyxddKgMXMINVbK05Z2JsqGchAamTLe90ZH3CoNO8Kdj2ZOweuD WBzg== X-Gm-Message-State: APjAAAVhyn5s51doIREG1wpzpplVY+D3g4FEpOKpG3L2tTPqN8uE9jdc tBiiLKFJ4Ubg4GWIqKYeaVwMonPmNJWvUQ== X-Google-Smtp-Source: APXvYqzIyksyoUB7B0sxJ1dIxa4WNU9mQp6mrY/NuJeeSzaA3Ol+gEiVQW5weqFwGNq0ME0PBwFsfA== X-Received: by 2002:a7b:c08d:: with SMTP id r13mr5639318wmh.84.1582907945050; Fri, 28 Feb 2020 08:39:05 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/33] target/arm: Remove ARM_FEATURE_VFP* Date: Fri, 28 Feb 2020 16:38:26 +0000 Message-Id: <20200228163840.23585-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::336 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We have converted all tests against these features to ISAR tests. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200224222232.13807-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 3 --- target/arm/cpu.c | 25 ------------------------- target/arm/cpu64.c | 3 --- target/arm/kvm32.c | 5 ----- target/arm/kvm64.c | 1 - 5 files changed, 37 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b29b0eddfc3..05aa9711cd8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1880,7 +1880,6 @@ QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= =3D R_V7M_CSSELR_INDEX_MASK); * mapping in linux-user/elfload.c:get_elf_hwcap(). */ enum arm_features { - ARM_FEATURE_VFP, ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ @@ -1889,7 +1888,6 @@ enum arm_features { ARM_FEATURE_V7, ARM_FEATURE_THUMB2, ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ - ARM_FEATURE_VFP3, ARM_FEATURE_NEON, ARM_FEATURE_M, /* Microcontroller profile. */ ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ @@ -1900,7 +1898,6 @@ enum arm_features { ARM_FEATURE_V5, ARM_FEATURE_STRONGARM, ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ - ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ ARM_FEATURE_GENERIC_TIMER, ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=3D15 */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index dc45865c7a7..e6016e33cec 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1208,13 +1208,6 @@ void arm_cpu_post_init(Object *obj) if (arm_feature(&cpu->env, ARM_FEATURE_M)) { set_feature(&cpu->env, ARM_FEATURE_PMSA); } - /* Similarly for the VFP feature bits */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP4)) { - set_feature(&cpu->env, ARM_FEATURE_VFP3); - } - if (arm_feature(&cpu->env, ARM_FEATURE_VFP3)) { - set_feature(&cpu->env, ARM_FEATURE_VFP); - } =20 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { @@ -1442,10 +1435,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) uint64_t t; uint32_t u; =20 - unset_feature(env, ARM_FEATURE_VFP); - unset_feature(env, ARM_FEATURE_VFP3); - unset_feature(env, ARM_FEATURE_VFP4); - t =3D cpu->isar.id_aa64isar1; t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); cpu->isar.id_aa64isar1 =3D t; @@ -1865,7 +1854,6 @@ static void arm926_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,arm926"; set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); cpu->midr =3D 0x41069265; @@ -1906,7 +1894,6 @@ static void arm1026_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,arm1026"; set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_AUXCR); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); @@ -1954,7 +1941,6 @@ static void arm1136_r2_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,arm1136"; set_feature(&cpu->env, ARM_FEATURE_V6); - set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); @@ -1986,7 +1972,6 @@ static void arm1136_initfn(Object *obj) cpu->dtb_compatible =3D "arm,arm1136"; set_feature(&cpu->env, ARM_FEATURE_V6K); set_feature(&cpu->env, ARM_FEATURE_V6); - set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); @@ -2017,7 +2002,6 @@ static void arm1176_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,arm1176"; set_feature(&cpu->env, ARM_FEATURE_V6K); - set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_VAPA); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); @@ -2050,7 +2034,6 @@ static void arm11mpcore_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,arm11mpcore"; set_feature(&cpu->env, ARM_FEATURE_V6K); - set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_VAPA); set_feature(&cpu->env, ARM_FEATURE_MPIDR); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); @@ -2116,7 +2099,6 @@ static void cortex_m4_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M); set_feature(&cpu->env, ARM_FEATURE_M_MAIN); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - set_feature(&cpu->env, ARM_FEATURE_VFP4); cpu->midr =3D 0x410fc240; /* r0p0 */ cpu->pmsav7_dregion =3D 8; cpu->isar.mvfr0 =3D 0x10110021; @@ -2147,7 +2129,6 @@ static void cortex_m7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M); set_feature(&cpu->env, ARM_FEATURE_M_MAIN); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - set_feature(&cpu->env, ARM_FEATURE_VFP4); cpu->midr =3D 0x411fc272; /* r1p2 */ cpu->pmsav7_dregion =3D 8; cpu->isar.mvfr0 =3D 0x10110221; @@ -2179,7 +2160,6 @@ static void cortex_m33_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M_MAIN); set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - set_feature(&cpu->env, ARM_FEATURE_VFP4); cpu->midr =3D 0x410fd213; /* r0p3 */ cpu->pmsav7_dregion =3D 16; cpu->sau_sregion =3D 8; @@ -2263,7 +2243,6 @@ static void cortex_r5f_initfn(Object *obj) ARMCPU *cpu =3D ARM_CPU(obj); =20 cortex_r5_initfn(obj); - set_feature(&cpu->env, ARM_FEATURE_VFP3); cpu->isar.mvfr0 =3D 0x10110221; cpu->isar.mvfr1 =3D 0x00000011; } @@ -2282,7 +2261,6 @@ static void cortex_a8_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a8"; set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); @@ -2350,7 +2328,6 @@ static void cortex_a9_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a9"; set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_EL3); @@ -2415,7 +2392,6 @@ static void cortex_a7_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a7"; set_feature(&cpu->env, ARM_FEATURE_V7VE); - set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); @@ -2461,7 +2437,6 @@ static void cortex_a15_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a15"; set_feature(&cpu->env, ARM_FEATURE_V7VE); - set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index db695384ebc..8f2a43c938a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -102,7 +102,6 @@ static void aarch64_a57_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a57"; set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_AARCH64); @@ -156,7 +155,6 @@ static void aarch64_a53_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a53"; set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_AARCH64); @@ -210,7 +208,6 @@ static void aarch64_a72_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a72"; set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_AARCH64); diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 7981ae3bc4e..f703c4fcad8 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -147,7 +147,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) * bits, but a few must be tested. */ set_feature(&features, ARM_FEATURE_V7VE); - set_feature(&features, ARM_FEATURE_VFP3); set_feature(&features, ARM_FEATURE_GENERIC_TIMER); =20 if (extract32(id_pfr0, 12, 4) =3D=3D 1) { @@ -156,10 +155,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) if (extract32(ahcf->isar.mvfr1, 12, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_NEON); } - if (extract32(ahcf->isar.mvfr1, 28, 4) =3D=3D 1) { - /* FMAC support implies VFPv4 */ - set_feature(&features, ARM_FEATURE_VFP4); - } =20 ahcf->features =3D features; =20 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 0ad96c3500a..93ba1448daf 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -649,7 +649,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) * feature bits. */ set_feature(&features, ARM_FEATURE_V8); - set_feature(&features, ARM_FEATURE_VFP4); set_feature(&features, ARM_FEATURE_NEON); set_feature(&features, ARM_FEATURE_AARCH64); set_feature(&features, ARM_FEATURE_PMU); --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582909385; cv=none; d=zohomail.com; s=zohoarc; b=may6ftjrE5U0nA1otyLAIDfbDowFZDi+UKl8bOL6I/VetR9OFbwTH6xBNF2DIuywghZo6DFD8Hg0iscnCCA9oANWBrcKVaghYIayv8YSo/iftY4ZZ5fhea4LHWi1WOd1PYZ92AGzWVvQa1Bh2GWivVzmzvHKYMm+2Oi1oTM+CTE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582909385; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rSk9BgFu3T3dOv7f971GWlTWgS0ZJflIP01745EcQLM=; b=gj5brchqdgI/amTi23tVmW2XbycLM7r1UHt2mkutGNpHWJsBiZcvQVzxWvB4eJqCQyh4PRDohRiobK0J6dkZSeDT5r7Lq5KWvr60QBBiLgluNZ1TbQJ9rE6bT190PMDizuzV+dK7chiahYjSy5IqabcL6WZ1R+k/bZzBRAIgjOQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582909385341895.4463281931044; Fri, 28 Feb 2020 09:03:05 -0800 (PST) Received: from localhost ([::1]:50884 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7j2U-0006Y0-Rn for importer@patchew.org; Fri, 28 Feb 2020 12:03:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56634) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifO-0007w2-6f for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:12 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifM-0001zU-Av for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:10 -0500 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:36855) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifM-0001z3-44 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:08 -0500 Received: by mail-wm1-x32f.google.com with SMTP id g83so1709463wme.1 for ; Fri, 28 Feb 2020 08:39:08 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.39.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:39:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rSk9BgFu3T3dOv7f971GWlTWgS0ZJflIP01745EcQLM=; b=DbU6El3RfmnBD5ebh6tX5a9FYmmYqlfIwZ3FDcWT+sAe9hyIQTMGwi2tt7k0VGY38z ysDUzJZRX/D+vOehNcc7LXetXOeYRGuuq7tC5pvWZEPyT+aaAa0MdvN5Cla+LgdZTTuF iyOpbO6tIc8ngH728DS2938tJquNOxlg07U17Njczm03+dCxOPHGHeZqG9sfY6XHUubX MO1WqrFUQ+Sz4edCJKk9rlRMsCxOTPdTVfuzwMjqNKiuo6IC99xNWf2TCoC88SsqAgcg e1rAYCkavheQR8xBw/hPthVC/oJwcYanYVt8P5C1dYp1OtV90CobO2Z1k0R52kaCBADs 5sqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rSk9BgFu3T3dOv7f971GWlTWgS0ZJflIP01745EcQLM=; b=MhgqqRyCQ+nK4z3/sK1XHtMpmnp27UKvWe51Z/WEqRQGQpUotCz9sLzfSzb+aL9UES 3XvjzmaupwR7Q4bJw2BQxtUvx81h2vgdke0VgBzb6QVkrsIrP82Js83Nnv0+AHWYCKOX VUIKnwdtl4E5KhMrnoIDDbhmVQWz2cVQMeFqa8ab3jk21eCdraw0BBUzw4W9oimzgyQa +eRHa5CKNWBV6QcJRKJoQ01jjwACYCDat/8F/oJvYseob1eUqnSOoZexCuskytxCv1pR MyyLTne0fq6JckTF9/BLrkW8RijwsryKrxEA/+heiMeBr6jk3Y9IIWerwRwZPXyGFeq3 zovw== X-Gm-Message-State: APjAAAVe1E395wuRHFNMUrSKwt89w+/4zS5SSEIeNpux6DhZ+4Xh/rXV nscOwlx6lr3ii601Gdbt7Y7OVDo6GaChuA== X-Google-Smtp-Source: APXvYqy5JoqQJH+iwmx+mffxRXSHEryBrnR/Fwcwm+U/joCHmjzPAFnHjMcxetxolDHKQUjOBSbOXg== X-Received: by 2002:a7b:c5d9:: with SMTP id n25mr5948290wmk.65.1582907946398; Fri, 28 Feb 2020 08:39:06 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/33] target/arm: Add formats for some vfp 2 and 3-register insns Date: Fri, 28 Feb 2020 16:38:27 +0000 Message-Id: <20200228163840.23585-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32f X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Those vfp instructions without extra opcode fields can share a common @format for brevity. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200224222232.13807-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/vfp.decode | 134 ++++++++++++++++-------------------------- 1 file changed, 52 insertions(+), 82 deletions(-) diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 592fe9e1e42..4f294f88be5 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -46,6 +46,14 @@ =20 %vmov_imm 16:4 0:4 =20 +@vfp_dnm_s ................................ vm=3D%vm_sp vn=3D%vn_sp vd= =3D%vd_sp +@vfp_dnm_d ................................ vm=3D%vm_dp vn=3D%vn_dp vd= =3D%vd_dp + +@vfp_dm_ss ................................ vm=3D%vm_sp vd=3D%vd_sp +@vfp_dm_dd ................................ vm=3D%vm_dp vd=3D%vd_dp +@vfp_dm_ds ................................ vm=3D%vm_sp vd=3D%vd_dp +@vfp_dm_sd ................................ vm=3D%vm_dp vd=3D%vd_sp + # VMOV scalar to general-purpose register; note that this does # include some Neon cases. VMOV_to_gp ---- 1110 u:1 1. 1 .... rt:4 1011 ... 1 0000 \ @@ -66,20 +74,15 @@ VDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e= :1 1 0000 \ vn=3D%vn_dp =20 VMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000 -VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 \ - vn=3D%vn_sp +VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 vn=3D%vn_sp =20 -VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... \ - vm=3D%vm_sp -VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... \ - vm=3D%vm_dp +VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... vm=3D%vm_sp +VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... vm=3D%vm_dp =20 # Note that the half-precision variants of VLDR and VSTR are # not part of this decodetree at all because they have bits [9:8] =3D=3D 0= b01 -VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 \ - vd=3D%vd_sp -VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 \ - vd=3D%vd_dp +VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=3D%vd_sp +VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=3D%vd_dp =20 # We split the load/store multiple up into two patterns to avoid # overlap with other insns in the "Advanced SIMD load/store and 64-bit mov= e" @@ -100,50 +103,32 @@ VLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \ vd=3D%vd_dp p=3D1 u=3D0 w=3D1 =20 # 3-register VFP data-processing; bits [23,21:20,6] identify the operation. -VMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... @vfp_dnm_s +VMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... @vfp_dnm_d =20 -VMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... @vfp_dnm_s +VMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... @vfp_dnm_d =20 -VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... @vfp_dnm_s +VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... @vfp_dnm_d =20 -VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... @vfp_dnm_s +VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... @vfp_dnm_d =20 -VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... @vfp_dnm_s +VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... @vfp_dnm_d =20 -VNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... @vfp_dnm_s +VNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... @vfp_dnm_d =20 -VADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... @vfp_dnm_s +VADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... @vfp_dnm_d =20 -VSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... @vfp_dnm_s +VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... @vfp_dnm_d =20 -VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s +VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d =20 VFM_sp ---- 1110 1.01 .... .... 1010 . o2:1 . 0 .... \ vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp o1=3D1 @@ -159,25 +144,17 @@ VMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \ VMOV_imm_dp ---- 1110 1.11 .... .... 1011 0000 .... \ vd=3D%vd_dp imm=3D%vmov_imm =20 -VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... \ - vd=3D%vd_sp vm=3D%vm_sp -VMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... \ - vd=3D%vd_dp vm=3D%vm_dp +VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... @vfp_dm_ss +VMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... @vfp_dm_dd =20 -VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... \ - vd=3D%vd_sp vm=3D%vm_sp -VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... \ - vd=3D%vd_dp vm=3D%vm_dp +VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... @vfp_dm_ss +VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... @vfp_dm_dd =20 -VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... \ - vd=3D%vd_sp vm=3D%vm_sp -VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... \ - vd=3D%vd_dp vm=3D%vm_dp +VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... @vfp_dm_ss +VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... @vfp_dm_dd =20 -VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... \ - vd=3D%vd_sp vm=3D%vm_sp -VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... \ - vd=3D%vd_dp vm=3D%vm_dp +VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... @vfp_dm_ss +VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... @vfp_dm_dd =20 VCMP_sp ---- 1110 1.11 010 z:1 .... 1010 e:1 1.0 .... \ vd=3D%vd_sp vm=3D%vm_sp @@ -190,32 +167,26 @@ VCVT_f32_f16 ---- 1110 1.11 0010 .... 1010 t:1 1.0 ..= .. \ VCVT_f64_f16 ---- 1110 1.11 0010 .... 1011 t:1 1.0 .... \ vd=3D%vd_dp vm=3D%vm_sp =20 -# VCVTB and VCVTT to f16: Vd format is always vd_sp; Vm format depends on = size bit +# VCVTB and VCVTT to f16: Vd format is always vd_sp; +# Vm format depends on size bit VCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 .... \ vd=3D%vd_sp vm=3D%vm_sp VCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \ vd=3D%vd_sp vm=3D%vm_dp =20 -VRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... \ - vd=3D%vd_sp vm=3D%vm_sp -VRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... \ - vd=3D%vd_dp vm=3D%vm_dp +VRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... @vfp_dm_ss +VRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... @vfp_dm_dd =20 -VRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... \ - vd=3D%vd_sp vm=3D%vm_sp -VRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... \ - vd=3D%vd_dp vm=3D%vm_dp +VRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... @vfp_dm_ss +VRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... @vfp_dm_dd =20 -VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... \ - vd=3D%vd_sp vm=3D%vm_sp -VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... \ - vd=3D%vd_dp vm=3D%vm_dp +VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... @vfp_dm_ss +VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... @vfp_dm_dd =20 -# VCVT between single and double: Vm precision depends on size; Vd is its = reverse -VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... \ - vd=3D%vd_dp vm=3D%vm_sp -VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... \ - vd=3D%vd_sp vm=3D%vm_dp +# VCVT between single and double: +# Vm precision depends on size; Vd is its reverse +VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... @vfp_dm_ds +VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... @vfp_dm_sd =20 # VCVT from integer to floating point: Vm always single; Vd depends on size VCVT_int_sp ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \ @@ -224,8 +195,7 @@ VCVT_int_dp ---- 1110 1.11 1000 .... 1011 s:1 1.0 ....= \ vd=3D%vd_dp vm=3D%vm_sp =20 # VJCVT is always dp to sp -VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... \ - vd=3D%vd_sp vm=3D%vm_dp +VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... @vfp_dm_sd =20 # VCVT between floating-point and fixed-point. The immediate value # is in the same format as a Vm single-precision register number. --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582909224; cv=none; d=zohomail.com; s=zohoarc; b=RP/XkbvZ1OSaQapMjVEiM/zigWsUh9Ik22iH3njHT6h5OIrYAt1p6IAP3+auoyohnNZWm7PaW3ZTAM8OioZt7F/AVkn04YrMu3nTe7PpjqSTUC47Goust/zTvtYWcmdb9BQtNmDIoFV9FiAJoey2fQ0K1Ik9r2jLrV/CF8fHy5U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582909224; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=H9vgJ1xHyPTbz5vgbyrb9N1PuwfNuQ0QSjFXbJuKM48=; b=f+aQKKS2akvAq39Qxkz75qKWaM9i6GDbTorniXozDqZEMokX9+AvjQ1gIX8pyAMa2b6Chg9lJa64EfteA91g0YCPsoUaRKk1ZgZk2IWcEzoMgypJPji061/6myDeD6ekVHxHBNL7uAsdUzhxsqZeRNa4ndx9UNDRx3Toi8tffAA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582909224812163.75432278249855; Fri, 28 Feb 2020 09:00:24 -0800 (PST) Received: from localhost ([::1]:50826 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7izu-0002ru-6W for importer@patchew.org; Fri, 28 Feb 2020 12:00:22 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56636) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifO-0007wH-7s for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifM-0001zk-SA for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:10 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:41893) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifM-0001zI-Le for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:08 -0500 Received: by mail-wr1-x441.google.com with SMTP id v4so3642525wrs.8 for ; Fri, 28 Feb 2020 08:39:08 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.39.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:39:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=H9vgJ1xHyPTbz5vgbyrb9N1PuwfNuQ0QSjFXbJuKM48=; b=d8Hb5eA9ftrUsULuODN5juju2IgEVy3sSpUaHbbx40qsXUSO0tstmosyZGiCCxCgSn BwaFsgunCSR/zn8S7qeheUXcXy/3WoCYzvW1whaS/PAF56jkXw7bpIYM1a9O4FjoWOUw 3ZVazTWpVuO4e3U/6DotxWHHIF13uI4UQ4LNCFgVYRCNYgiZ2N08ns7re5l6k1UBnGqp /FHLI7ybJJC2DyA5xro6z5EI7ctJ0CrANiY7+3eaob9I6wN9vOsaae3XdFcvNASKTnXc ur6WopbvutIUp352T1q2SklM/qlBfa7Bab93PPVWGpcuUu4TBpQYyUFK+iRnHQ41F3u4 i4Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=H9vgJ1xHyPTbz5vgbyrb9N1PuwfNuQ0QSjFXbJuKM48=; b=HfBnz32/SYn+BfgwoljVCw5Ls7QxQM89tKUImh6ozmYnjupQ3P361aTc8rRsrxNzly ++dl2OuSOy3ekpGOODo1Z5W7irLpsLvdrDFZq3+OK1Dp7XYJMz2954A56UAK2OSS8XEH PFe+w50ctJ1LB7eSG2pdADUfCswsFnTGyE3KoNF+gPj4UiqsXgfYc9atn/O47lyo1iV2 7zR4dKI1J0t8IxXqbMQUK7KyvSHupMJH/W8EkLv9VR6n2ILzxQdfAB0laOv5WXjXfa1/ m1ZNFeJSPcGDetrdJlnz1tUVWuqsfFpwrDGwtwZ43QbPFecoSRTH0+22FkmDr5MPIz24 dasA== X-Gm-Message-State: APjAAAVgH2D1iEast/tFW0NMPSqrs54RS4WIGiNrkblbG4qkwlEtbhPB r0yqZ+8vcFKVPI5AwEyMdyMj8iQ9x+dOiw== X-Google-Smtp-Source: APXvYqxxwZQ7PBWv2Y8MJOjF7eRG/uFopVTTz+P1pdFAQlaoz3nM0HpVUnWZNUtodiJgmUxQIGgWIA== X-Received: by 2002:a5d:5007:: with SMTP id e7mr5661156wrt.228.1582907947340; Fri, 28 Feb 2020 08:39:07 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/33] target/arm: Split VFM decode Date: Fri, 28 Feb 2020 16:38:28 +0000 Message-Id: <20200228163840.23585-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Passing the raw o1 and o2 fields from the manual is less instructive than it might be. Do the full decode and let the trans_* functions pass in booleans to a helper. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200224222232.13807-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-vfp.inc.c | 52 ++++++++++++++++++++++++++++++---- target/arm/vfp.decode | 17 +++++------ 2 files changed, 55 insertions(+), 14 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 1964af3ea5e..41aa67c133a 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1784,7 +1784,7 @@ static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_d= p *a) return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, fals= e); } =20 -static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a) +static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool ne= g_d) { /* * VFNMA : fd =3D muladd(-fd, fn, fm) @@ -1828,12 +1828,12 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_s= p *a) =20 neon_load_reg32(vn, a->vn); neon_load_reg32(vm, a->vm); - if (a->o2) { + if (neg_n) { /* VFNMS, VFMS */ gen_helper_vfp_negs(vn, vn); } neon_load_reg32(vd, a->vd); - if (a->o1 & 1) { + if (neg_d) { /* VFNMA, VFNMS */ gen_helper_vfp_negs(vd, vd); } @@ -1849,7 +1849,27 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp= *a) return true; } =20 -static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a) +static bool trans_VFMA_sp(DisasContext *s, arg_VFMA_sp *a) +{ + return do_vfm_sp(s, a, false, false); +} + +static bool trans_VFMS_sp(DisasContext *s, arg_VFMS_sp *a) +{ + return do_vfm_sp(s, a, true, false); +} + +static bool trans_VFNMA_sp(DisasContext *s, arg_VFNMA_sp *a) +{ + return do_vfm_sp(s, a, false, true); +} + +static bool trans_VFNMS_sp(DisasContext *s, arg_VFNMS_sp *a) +{ + return do_vfm_sp(s, a, true, true); +} + +static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool ne= g_d) { /* * VFNMA : fd =3D muladd(-fd, fn, fm) @@ -1905,12 +1925,12 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_d= p *a) =20 neon_load_reg64(vn, a->vn); neon_load_reg64(vm, a->vm); - if (a->o2) { + if (neg_n) { /* VFNMS, VFMS */ gen_helper_vfp_negd(vn, vn); } neon_load_reg64(vd, a->vd); - if (a->o1 & 1) { + if (neg_d) { /* VFNMA, VFNMS */ gen_helper_vfp_negd(vd, vd); } @@ -1926,6 +1946,26 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp= *a) return true; } =20 +static bool trans_VFMA_dp(DisasContext *s, arg_VFMA_dp *a) +{ + return do_vfm_dp(s, a, false, false); +} + +static bool trans_VFMS_dp(DisasContext *s, arg_VFMS_dp *a) +{ + return do_vfm_dp(s, a, true, false); +} + +static bool trans_VFNMA_dp(DisasContext *s, arg_VFNMA_dp *a) +{ + return do_vfm_dp(s, a, false, true); +} + +static bool trans_VFNMS_dp(DisasContext *s, arg_VFNMS_dp *a) +{ + return do_vfm_dp(s, a, true, true); +} + static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a) { uint32_t delta_d =3D 0; diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 4f294f88be5..5fd70f975ae 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -130,14 +130,15 @@ VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... = @vfp_dnm_d VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d =20 -VFM_sp ---- 1110 1.01 .... .... 1010 . o2:1 . 0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp o1=3D1 -VFM_dp ---- 1110 1.01 .... .... 1011 . o2:1 . 0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp o1=3D1 -VFM_sp ---- 1110 1.10 .... .... 1010 . o2:1 . 0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp o1=3D2 -VFM_dp ---- 1110 1.10 .... .... 1011 . o2:1 . 0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp o1=3D2 +VFMA_sp ---- 1110 1.10 .... .... 1010 .0. 0 .... @vfp_dnm_s +VFMS_sp ---- 1110 1.10 .... .... 1010 .1. 0 .... @vfp_dnm_s +VFNMA_sp ---- 1110 1.01 .... .... 1010 .0. 0 .... @vfp_dnm_s +VFNMS_sp ---- 1110 1.01 .... .... 1010 .1. 0 .... @vfp_dnm_s + +VFMA_dp ---- 1110 1.10 .... .... 1011 .0.0 .... @vfp_dnm_d +VFMS_dp ---- 1110 1.10 .... .... 1011 .1.0 .... @vfp_dnm_d +VFNMA_dp ---- 1110 1.01 .... .... 1011 .0.0 .... @vfp_dnm_d +VFNMS_dp ---- 1110 1.01 .... .... 1011 .1.0 .... @vfp_dnm_d =20 VMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \ vd=3D%vd_sp imm=3D%vmov_imm --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908458; cv=none; d=zohomail.com; s=zohoarc; b=BuGaTLlZXtEqYSkNspQeF61XbCzAqoxUlhk5mVhIMwTGanIz4HqlFh+xzRzCYq65NG79TTouXo7Sn/XCvnc4EiJGl3PauSDtf0oZUxSUbKM1sGqoeHbfwuMktaxHaLQWPi7esQKB2HsOwKI7Aw29NJxXNy/EgHjbBEGZs4SaOYA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908458; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=J50rehePz6YH1BM0Ziq+fv9dQfKqd43AZMRslmyChUs=; b=Kxgh60n+m5tyTN8OcHNgpmjjBCgRLBRv5e4UxeHTUkZssSrfjVXgBjp6XyvR9hSB+TOOkltjTWwlnIg+FnwTuTpMHCksvPfEvUX6m18fo3os3nrdeQMa6CGybVvraTTju/YKR/HCyEm3uOcFlvsHmqzuiDIwMdvJrsLfwFNKYuo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158290845892665.890970728502; Fri, 28 Feb 2020 08:47:38 -0800 (PST) Received: from localhost ([::1]:50530 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7inZ-00075B-LJ for importer@patchew.org; Fri, 28 Feb 2020 11:47:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56651) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifP-0007yr-8o for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifN-00020V-Up for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:11 -0500 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:52819) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifN-000203-Nv for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:09 -0500 Received: by mail-wm1-x32c.google.com with SMTP id p9so3856293wmc.2 for ; Fri, 28 Feb 2020 08:39:09 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.39.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:39:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=J50rehePz6YH1BM0Ziq+fv9dQfKqd43AZMRslmyChUs=; b=sKVKHBX29W6HKTR9ECigPAWgf6QXS/JoqiTP/4CjXpY2l63b1JyIXvm0e/MngSsBjJ 9tPH3+JnrIREtjbRg5B7etHyaXel9wIdsVRC5+dbe/LXU25pTLcQUjEeELeHjxTRYcB2 2+zWjs3KPEH54kGm65YIExBBNVAXOBEcHVP6R3jiAlhbqxbxOne7fgUbzm02JTUuB2Ke RJpjM1HD+EBHjcR6+V/09OT89fjEHgLkit+8MeiWsgpBPHjFYCsMFLaT9uJnXRL2hIxv G3Q+I1Z8GmwHu2VkzolauuVc6kK97MG3601JMbWWzBH6rbA/sz+9pOAI10hwW5bzhwFR Mp0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=J50rehePz6YH1BM0Ziq+fv9dQfKqd43AZMRslmyChUs=; b=kZHZ98rsC6IVfd6KY9m6jfmfyFvYhp3ODitaJ9jFvQWAowWoaCkznOqLi0RCCfoBAf Xh7IQEvC2ZEQ7oWF4FGfQyJfR+gj2b4rzyVn6goFY6+WKzzWm1KWN7yZ3LtNxSy49zCg /5EUYA7NBEFBuQ8RCV2SGU21GhhQe64yoQD/TbvSEXqEv4rl9Y7fKFUZYV9z+OyoSCUu 1zrYq7BXzSMrumYKZoI43Vd2fJtezh4vYz6cyScOup7YYAATDkNafBxzGuQALq9DTiZc P97MLZnfqVuJtfK6u2K6fjJBZe/awTw4YQgVsjS9icZEJW6Ax8hW7Q0aICYP6q7t9Wtj WByw== X-Gm-Message-State: APjAAAXbRs7cVJ5ojCdjdSKB2qa2rGl7QVNKK9wwqdrBZOPoONLCwjK7 OylIhpZuokvMvlN3wBAXfUkcXY0eji6DmA== X-Google-Smtp-Source: APXvYqzmLiesEvje1rvde5G2CjAU0H5LAurgPSkdtDaSrB/dKmKFQjJYVJ7OY8jtjgR5hlgMSXTbzw== X-Received: by 2002:a1c:7315:: with SMTP id d21mr5646544wmb.186.1582907948312; Fri, 28 Feb 2020 08:39:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/33] target/arm: Split VMINMAXNM decode Date: Fri, 28 Feb 2020 16:38:29 +0000 Message-Id: <20200228163840.23585-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Passing the raw op field from the manual is less instructive than it might be. Do the full decode and use the existing helpers to perform the expansion. Since these are v8 insns, VECLEN+VECSTRIDE are already RES0. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200224222232.13807-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-vfp.inc.c | 109 +++++++++++---------------------- target/arm/vfp-uncond.decode | 12 ++-- 2 files changed, 44 insertions(+), 77 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 41aa67c133a..b087bbd812e 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -322,79 +322,6 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) return true; } =20 -static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a) -{ - uint32_t rd, rn, rm; - bool dp =3D a->dp; - bool vmin =3D a->op; - TCGv_ptr fpst; - - if (!dc_isar_feature(aa32_vminmaxnm, s)) { - return false; - } - - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vn | a->vd) & 0x10)) { - return false; - } - - rd =3D a->vd; - rn =3D a->vn; - rm =3D a->vm; - - if (!vfp_access_check(s)) { - return true; - } - - fpst =3D get_fpstatus_ptr(0); - - if (dp) { - TCGv_i64 frn, frm, dest; - - frn =3D tcg_temp_new_i64(); - frm =3D tcg_temp_new_i64(); - dest =3D tcg_temp_new_i64(); - - neon_load_reg64(frn, rn); - neon_load_reg64(frm, rm); - if (vmin) { - gen_helper_vfp_minnumd(dest, frn, frm, fpst); - } else { - gen_helper_vfp_maxnumd(dest, frn, frm, fpst); - } - neon_store_reg64(dest, rd); - tcg_temp_free_i64(frn); - tcg_temp_free_i64(frm); - tcg_temp_free_i64(dest); - } else { - TCGv_i32 frn, frm, dest; - - frn =3D tcg_temp_new_i32(); - frm =3D tcg_temp_new_i32(); - dest =3D tcg_temp_new_i32(); - - neon_load_reg32(frn, rn); - neon_load_reg32(frm, rm); - if (vmin) { - gen_helper_vfp_minnums(dest, frn, frm, fpst); - } else { - gen_helper_vfp_maxnums(dest, frn, frm, fpst); - } - neon_store_reg32(dest, rd); - tcg_temp_free_i32(frn); - tcg_temp_free_i32(frm); - tcg_temp_free_i32(dest); - } - - tcg_temp_free_ptr(fpst); - return true; -} - /* * Table for converting the most common AArch32 encoding of * rounding mode to arm_fprounding order (which matches the @@ -1784,6 +1711,42 @@ static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_= dp *a) return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, fals= e); } =20 +static bool trans_VMINNM_sp(DisasContext *s, arg_VMINNM_sp *a) +{ + if (!dc_isar_feature(aa32_vminmaxnm, s)) { + return false; + } + return do_vfp_3op_sp(s, gen_helper_vfp_minnums, + a->vd, a->vn, a->vm, false); +} + +static bool trans_VMAXNM_sp(DisasContext *s, arg_VMAXNM_sp *a) +{ + if (!dc_isar_feature(aa32_vminmaxnm, s)) { + return false; + } + return do_vfp_3op_sp(s, gen_helper_vfp_maxnums, + a->vd, a->vn, a->vm, false); +} + +static bool trans_VMINNM_dp(DisasContext *s, arg_VMINNM_dp *a) +{ + if (!dc_isar_feature(aa32_vminmaxnm, s)) { + return false; + } + return do_vfp_3op_dp(s, gen_helper_vfp_minnumd, + a->vd, a->vn, a->vm, false); +} + +static bool trans_VMAXNM_dp(DisasContext *s, arg_VMAXNM_dp *a) +{ + if (!dc_isar_feature(aa32_vminmaxnm, s)) { + return false; + } + return do_vfp_3op_dp(s, gen_helper_vfp_maxnumd, + a->vd, a->vn, a->vm, false); +} + static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool ne= g_d) { /* diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode index 5af1f2ee664..34ca164266f 100644 --- a/target/arm/vfp-uncond.decode +++ b/target/arm/vfp-uncond.decode @@ -41,15 +41,19 @@ %vd_dp 22:1 12:4 %vd_sp 12:4 22:1 =20 +@vfp_dnm_s ................................ vm=3D%vm_sp vn=3D%vn_sp vd= =3D%vd_sp +@vfp_dnm_d ................................ vm=3D%vm_dp vn=3D%vn_dp vd= =3D%vd_dp + VSEL 1111 1110 0. cc:2 .... .... 1010 .0.0 .... \ vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp dp=3D0 VSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp dp=3D1 =20 -VMINMAXNM 1111 1110 1.00 .... .... 1010 . op:1 .0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp dp=3D0 -VMINMAXNM 1111 1110 1.00 .... .... 1011 . op:1 .0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp dp=3D1 +VMAXNM_sp 1111 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s +VMINNM_sp 1111 1110 1.00 .... .... 1010 .1.0 .... @vfp_dnm_s + +VMAXNM_dp 1111 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d +VMINNM_dp 1111 1110 1.00 .... .... 1011 .1.0 .... @vfp_dnm_d =20 VRINT 1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \ vm=3D%vm_sp vd=3D%vd_sp dp=3D0 --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908209; cv=none; d=zohomail.com; s=zohoarc; b=hyTmFkh0ptodZXqiT/oPbJDNGu3wBzskJWqM4+epBVOGso4ieBe9Tv8is/KONQa5cv2zT55ELo0oxGVuSwDlxjE3eaR8MgIg+gRQFYa0m3vzwep52DK84A5lMMNoXFJe7pD1QMrTYmJMsMdu51IVzI8/LJMJ2Pa5Mh9pkILgij8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908209; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nzBxpGRVoOvsVOJMyP7MLneRWhuVzeygLumjQm/0mJM=; b=gkQOctB1ZTMirG/vPFE13ApQQlhvZ8TtsAnnhiS/s97KGz7AM5iVyAicGYJljxIgx+u8KdGYQnvrU55hcxJCGvze5VN5haqgtUEbmT0sb9+uoEajwGC++aHbl1PyIgKYb5531MZ/U+SVWGkVqM4QAHwlREYdwY2PKpkmNyAoiq8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908209791347.48625319858286; Fri, 28 Feb 2020 08:43:29 -0800 (PST) Received: from localhost ([::1]:50264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ijY-0000Cd-G3 for importer@patchew.org; Fri, 28 Feb 2020 11:43:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56673) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifR-00081S-6a for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifO-00021I-TN for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:13 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:55832) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifO-00020j-Mq for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:10 -0500 Received: by mail-wm1-x342.google.com with SMTP id q9so3813156wmj.5 for ; Fri, 28 Feb 2020 08:39:10 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.39.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:39:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=nzBxpGRVoOvsVOJMyP7MLneRWhuVzeygLumjQm/0mJM=; b=M1xz/9odEHOQ0pmoGoBARbK67tiajNoZgo7Do6G4jCZBxG+o4/yauILySdCBb/7DjV ZrqGu5Yrg+eF24+SFAEeM4Ne/DuIsychEyl5iqJSO9kRAjGOORqTtC7LOZ1SYaRFEZrA t2A85dfftF9CLfB8vYvHLoBsnRZ8x7FomSRnc1aD9lbaIiQLdpQDbuXNPCy82AeJ7MwI /dnwb9TN7DzlCrPM6dzXoHJpivky4SN26sZskRlru+MzuJfdE8MEsbMdYo54VUfOBvKa QmHtOnlgL68W/WJGGyKiXEZHYt8ZhNxvNEo02VUQNGCZRTj4d9UQjhDQSht5e+u10zvt L7MA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nzBxpGRVoOvsVOJMyP7MLneRWhuVzeygLumjQm/0mJM=; b=NdhE/Muo6RPvS02rnTJ72LFqmO2weS1+0fh2pEGTpMVaLlXd9TycDfJGkddY6TmEH+ oG9Q7vo1EcrBW5bE9CKI1gzogRvoKwfH4m/JUmx1ZqxJcaluWS0sQefdlERjbtLkN6z9 NHrGT3dgERfM6Q6NNNtKklSSGhFJ17R/w2FBhaIzR53yBjwctTWO1lyQ6mKU6bbEMOjD 0uHFGSsRfXR7hPBskD1SJkWCta87RY/RIgeneqBr/5Ql+TqHr0Hg/TvIDpgmvhaaMzGl OiHP/r+t+Gu6aHLvuo7gLgYdH8mFhyudWlWM7WsJ8rUblSrnXo2mRQs5o1sLHhYGt8aq ihBQ== X-Gm-Message-State: APjAAAWPYflbPe4hvbSI/Tl5I4JJVhDV7a5uOELGJVdEa+9n9/4fGo/T uiPriMwvbQirEY+u561deWDFMgFyJGhUJQ== X-Google-Smtp-Source: APXvYqxKRzWILLJBqyaGyirS6WISdqfbggTVeWHI4NrMdd59N9hhSKzU9cWWE0QH/WhxVq95mEHaeQ== X-Received: by 2002:a1c:984a:: with SMTP id a71mr5800072wme.185.1582907949447; Fri, 28 Feb 2020 08:39:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/33] hw/arm/xilinx_zynq: Fix USB port instantiation Date: Fri, 28 Feb 2020 16:38:30 +0000 Message-Id: <20200228163840.23585-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Guenter Roeck USB ports on Xilinx Zync must be instantiated as TYPE_CHIPIDEA to work. Linux expects and checks various chipidea registers, which do not exist with the basic ehci emulation. This patch series fixes the problem. Without this patch, USB ports fail to instantiate under Linux. ci_hdrc ci_hdrc.0: doesn't support host ci_hdrc ci_hdrc.0: no supported roles With this patch, USB ports are instantiated, and it is possible to boot from USB drive. ci_hdrc ci_hdrc.0: EHCI Host Controller ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1 ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00 usb 1-1: new full-speed USB device number 2 using ci_hdrc usb 1-1: not running at top speed; connect to a high speed hub usb 1-1: config 1 interface 0 altsetting 0 endpoint 0x81 has invalid maxpac= ket 512, setting to 64 usb 1-1: config 1 interface 0 altsetting 0 endpoint 0x2 has invalid maxpack= et 512, setting to 64 usb-storage 1-1:1.0: USB Mass Storage device detected scsi host0: usb-storage 1-1:1.0 Signed-off-by: Guenter Roeck Reviewed-by: Gerd Hoffmann Message-id: 20200215122354.13706-2-linux@roeck-us.net Signed-off-by: Peter Maydell --- hw/arm/xilinx_zynq.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 3d439a45d57..571cdcd599e 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -29,6 +29,7 @@ #include "hw/loader.h" #include "hw/misc/zynq-xadc.h" #include "hw/ssi/ssi.h" +#include "hw/usb/chipidea.h" #include "qemu/error-report.h" #include "hw/sd/sdhci.h" #include "hw/char/cadence_uart.h" @@ -225,8 +226,8 @@ static void zynq_init(MachineState *machine) zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false); zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true); =20 - sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]); - sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]); + sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]); + sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]); =20 cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0)); cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1)); --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582909529; cv=none; d=zohomail.com; s=zohoarc; b=EOlbynjA4jvd1u+JSZvsLycXZJlM9SWDTEPGnAcViLqJ+LyKR0+JjOnIKQCjO/MELezthfUTySLOUTSpQX0I41q5v3c/MYVc+WRUYrJhfhXa86s/Q0zVFF/fBhDVlNKvVf/jD2S6aCdJGwQ5QFESlt6te0DeD24bKwRW9wy5vKI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582909529; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OBBHRjdd80h8GtLACN+1yFyC+k5vRKdVFPA1E7huKbI=; b=CP043olaDm1d36dIzZXHSOXK2TMzebsa9kamLUpBIpfOGMcrwSeQBfHL0LvB5W5CBEKRFjo1oioTLF67vGQm8k/UnDnKX8Mn3GwNE++iWmnGWChx13VQw9qnkE+Yfdj1bwAh0Eso4zgYZKkgG8hyIIuVyV6i0E3Tv2MpkyOSl+Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582909529813396.16037245353743; Fri, 28 Feb 2020 09:05:29 -0800 (PST) Received: from localhost ([::1]:50912 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7j4q-0001nL-FU for importer@patchew.org; Fri, 28 Feb 2020 12:05:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56686) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifR-00083L-SS for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:14 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifQ-00022s-QK for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:13 -0500 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:36851) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifP-00021W-K8 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:12 -0500 Received: by mail-wm1-x32a.google.com with SMTP id g83so1709756wme.1 for ; Fri, 28 Feb 2020 08:39:11 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.39.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:39:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=OBBHRjdd80h8GtLACN+1yFyC+k5vRKdVFPA1E7huKbI=; b=U75JsSpQT1vVB3OOXFAOHq6euP/J+fYRnOqpPa8FQSXG2fF/MiydB+qIwEvqCuanvt TLG4g/pMYlrF/DkDOtdYRVZXxviBLJf3/V0DypgS2edUjuSyFkcfpQ4rXYA/1kErUbGI b609CsLPqTOQdXOY3ifQkv0/6glv8DKNTp7+xoQlxqN7jnQiCUl4q+jEvnLQwwHq4axI kCmx739Wgo7r/ysvuV65Y59475fL0IADpql4LKtsf8jOvKllTRy0GvdiWzO0H+RqvGJ4 Lyg0nUOVQLxWvxErR0uOIjYltcZ2z+3KSlKeTik1FuYqDbNyvuhjSXqnyfEgzzvVhYab bn0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OBBHRjdd80h8GtLACN+1yFyC+k5vRKdVFPA1E7huKbI=; b=KxDG6RsGz7x/xXd2CwMflNkkFLY4+6AWqueB2OOFMUwkHl61cnSZzgQQpkk9YZ/xTF lDxj+e/BkUVc///GbFJC4vyZugrrkCMc9Q7yCJc0PdkhxbkRMf3we0uZvwfwFu1a2Feu 6KiI77Mzxm0ZXhPCwH9GTaZlt1Swb45YwVbi93oJUHo9Ht8uxV/GTtl5ismaJK7/PHzu 952ziW0vn865YPKe64SKqf4LYe3A7SywS5eLQFIhI4IhhuQv5uCIjcN4bO0wWgJDPXZ1 dEc9x/6T9e2XO6GLYvZ+QkxGB+p6wp+my2YjYbqeeXaDMJkOPjtZtFf1Rq9dgjhxcdbS sKrg== X-Gm-Message-State: APjAAAVt10iYrVvrdhxbw+TMTBvFPfP5E/ntadTJhRetMSQII797eMsl FFd9pykSetkWp+VQF7rQMZKZLAicVSfu8w== X-Google-Smtp-Source: APXvYqwF8AR7LyDXP84gYasKjIsrc5E3BFRmgLhvzQthdDZcpB6Nt+We8Wst4WonzMY1TMW6MbFqHw== X-Received: by 2002:a1c:2504:: with SMTP id l4mr5770429wml.72.1582907950410; Fri, 28 Feb 2020 08:39:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/33] hw/usb/hcd-ehci-sysbus: Remove obsolete xlnx, ps7-usb class Date: Fri, 28 Feb 2020 16:38:31 +0000 Message-Id: <20200228163840.23585-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32a X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Guenter Roeck Xilinx USB devices are now instantiated through TYPE_CHIPIDEA, and xlnx support in the EHCI code is no longer needed. Signed-off-by: Guenter Roeck Reviewed-by: Gerd Hoffmann Message-id: 20200215122354.13706-3-linux@roeck-us.net Signed-off-by: Peter Maydell --- hw/usb/hcd-ehci-sysbus.c | 17 ----------------- 1 file changed, 17 deletions(-) diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c index b22fb258be7..5b7991cffe4 100644 --- a/hw/usb/hcd-ehci-sysbus.c +++ b/hw/usb/hcd-ehci-sysbus.c @@ -115,22 +115,6 @@ static const TypeInfo ehci_platform_type_info =3D { .class_init =3D ehci_platform_class_init, }; =20 -static void ehci_xlnx_class_init(ObjectClass *oc, void *data) -{ - SysBusEHCIClass *sec =3D SYS_BUS_EHCI_CLASS(oc); - DeviceClass *dc =3D DEVICE_CLASS(oc); - - set_bit(DEVICE_CATEGORY_USB, dc->categories); - sec->capsbase =3D 0x100; - sec->opregbase =3D 0x140; -} - -static const TypeInfo ehci_xlnx_type_info =3D { - .name =3D "xlnx,ps7-usb", - .parent =3D TYPE_SYS_BUS_EHCI, - .class_init =3D ehci_xlnx_class_init, -}; - static void ehci_exynos4210_class_init(ObjectClass *oc, void *data) { SysBusEHCIClass *sec =3D SYS_BUS_EHCI_CLASS(oc); @@ -267,7 +251,6 @@ static void ehci_sysbus_register_types(void) { type_register_static(&ehci_type_info); type_register_static(&ehci_platform_type_info); - type_register_static(&ehci_xlnx_type_info); type_register_static(&ehci_exynos4210_type_info); type_register_static(&ehci_tegra2_type_info); type_register_static(&ehci_ppc4xx_type_info); --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582909660; cv=none; d=zohomail.com; s=zohoarc; b=ZsDtbU8xv9Wz5FGCEyXlAsFGokiZMU8Zf1ZUHyoIYex3vhU7UJIuwPTLiv9loA70U3zYOmvwCFFKWv2MmShFXY6LGakcscMYDHLI/NarawwxZGcqFXPpqXOxG3VUvWAz6pCQpxnr4+jlZCwnnKvhR3WolszNrE20Cnbn954sOFw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582909660; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7pnRJmXnO6IweO9cucbS1G2R/qlgmQQw2whsHVhkaZE=; b=j6u8eGT3BwBzSM1lDRspmbDXMsxi07YqaGQkvdj3/4K6GIoWJaiYbylk0aTY7fXiSMhcxzM0JM/V+kQs+kQuoL8oAiu/6ZQcBDe7K1pvnoA40YjIQsR3RYegQx2PEOy5FJW9HaLwmFdwbRcdWKqyPC1fJ6kNoEjnksyhFcY1Ef4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582909660426365.68925787419255; Fri, 28 Feb 2020 09:07:40 -0800 (PST) Received: from localhost ([::1]:50952 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7j6x-0005N7-5Q for importer@patchew.org; Fri, 28 Feb 2020 12:07:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56697) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifS-00084x-FB for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:15 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifR-00023B-54 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:14 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:42252) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifQ-00022m-US for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:13 -0500 Received: by mail-wr1-x42c.google.com with SMTP id p18so3638157wre.9 for ; Fri, 28 Feb 2020 08:39:12 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.39.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:39:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7pnRJmXnO6IweO9cucbS1G2R/qlgmQQw2whsHVhkaZE=; b=UTzyJPNqpQqlyXniKbEloNDMOAKtEzXo39ufOq2/p2LTGqGhnK6MkV2V9fkPJD2r22 NPnwbwi97+oSRoYuogSJv9h5Bz8OpUuRd0iz352HrYMdrjmj8BTZT7MUPkyV3dcbY6zv ozosodw0hFBxX28fIwsufXWifPX3wpsBFSL2kpaFd/q8zm30NWdMvKdZHKEg2d8YcGUv bj/uNI3gvnUZn9O0iELpCdeWmnCgHoKtTrXmhXRulwklPVHFOXuRyZnrolYqI88VX6fU bSlvYasapLp45T7KuljWM6j+eDGsJ/Zzz4pZm/FeKO8JtpHY9JDvaP/aJQVgz0URSMOQ aOsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7pnRJmXnO6IweO9cucbS1G2R/qlgmQQw2whsHVhkaZE=; b=eF8AktvlFi+BKE+weRlq/GcOSyJ66RjiBjWC8GEL1THB1ggyDOGl5WeR4GeLNfNOdf nqOiegAfOD4rU18yIYdN05MiXq3VwVIQrC86YU/okFyPq+dg3WR4BzGuzxsWmFsMxPVM HG8Eb0ppDtSDKfsf11oXy3lvvUYK+vF6OeGvL6Jz6fWc5zBRw8NATxxt8uEbHp3ixdW5 fnNgV9Ur/1ymoyNsSjo4fFwzvRXpMRjrgc56OpXN58ub82qrnN27pKYJixVOj5rueDps xuQf/Kb3gsfNtogmBlh407UxX92U3n7yT5TnG2+o34/zZKq/C9cxFZhRyFVEo8jv4ZGV twaQ== X-Gm-Message-State: APjAAAUzsHHSs6xOm+cc3mupeFkbexC61kL/hTBk0CMWbaG1IXctbsaC RYRCPS9v8wjL0JfXtQzoy7JKhVESHCCysw== X-Google-Smtp-Source: APXvYqwc6DYlF7hCRuwxyonVI3wnlvADI2R3tbkx2C2e4xdIXmLcjGa4w9N0VITc7OjFlIc4ANA7Xw== X-Received: by 2002:adf:9521:: with SMTP id 30mr5484988wrs.349.1582907951611; Fri, 28 Feb 2020 08:39:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/33] tests/acceptance: Add a test for the N800 and N810 arm machines Date: Fri, 28 Feb 2020 16:38:32 +0000 Message-Id: <20200228163840.23585-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Thomas Huth Old kernels from the Meego project can be used to check that Linux is at least starting on these machines. Signed-off-by: Thomas Huth Reviewed-by: Wainer dos Santos Moschetta Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200225172501.29609-2-philmd@redhat.com Message-Id: <20200129131920.22302-1-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell Acked-by: Igor Mammedov --- MAINTAINERS | 1 + tests/acceptance/machine_arm_n8x0.py | 49 ++++++++++++++++++++++++++++ 2 files changed, 50 insertions(+) create mode 100644 tests/acceptance/machine_arm_n8x0.py diff --git a/MAINTAINERS b/MAINTAINERS index b66c46dcb9f..264374adbe8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -686,6 +686,7 @@ F: hw/rtc/twl92230.c F: include/hw/display/blizzard.h F: include/hw/input/tsc2xxx.h F: include/hw/misc/cbus.h +F: tests/acceptance/machine_arm_n8x0.py =20 Palm M: Andrzej Zaborowski diff --git a/tests/acceptance/machine_arm_n8x0.py b/tests/acceptance/machin= e_arm_n8x0.py new file mode 100644 index 00000000000..e5741f2d8d1 --- /dev/null +++ b/tests/acceptance/machine_arm_n8x0.py @@ -0,0 +1,49 @@ +# Functional test that boots a Linux kernel and checks the console +# +# Copyright (c) 2020 Red Hat, Inc. +# +# Author: +# Thomas Huth +# +# This work is licensed under the terms of the GNU GPL, version 2 or +# later. See the COPYING file in the top-level directory. + +import os + +from avocado import skipUnless +from avocado_qemu import Test +from avocado_qemu import wait_for_console_pattern + +class N8x0Machine(Test): + """Boots the Linux kernel and checks that the console is operational""" + + timeout =3D 90 + + def __do_test_n8x0(self): + kernel_url =3D ('http://stskeeps.subnetmask.net/meego-n8x0/' + 'meego-arm-n8x0-1.0.80.20100712.1431-' + 'vmlinuz-2.6.35~rc4-129.1-n8x0') + kernel_hash =3D 'e9d5ab8d7548923a0061b6fbf601465e479ed269' + kernel_path =3D self.fetch_asset(kernel_url, asset_hash=3Dkernel_h= ash) + + self.vm.set_console(console_index=3D1) + self.vm.add_args('-kernel', kernel_path, + '-append', 'printk.time=3D0 console=3DttyS1') + self.vm.launch() + wait_for_console_pattern(self, 'TSC2005 driver initializing') + + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code= ') + def test_n800(self): + """ + :avocado: tags=3Darch:arm + :avocado: tags=3Dmachine:n800 + """ + self.__do_test_n8x0() + + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code= ') + def test_n810(self): + """ + :avocado: tags=3Darch:arm + :avocado: tags=3Dmachine:n810 + """ + self.__do_test_n8x0() --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908605; cv=none; d=zohomail.com; s=zohoarc; b=Lou+dpq4n1VS7e7ZzuTi9qdH1xSWJ30PPmv2YOuQovXroTF5G429CQbRoZ6BSoWELup0Ecm8QVHikVLUKUnalYoOe8kyZ5aVl9YPYWWENrmnj/Io5g1cq1LfCZtaEESsheKbAamjeDkbL4/Fg9ZJtEtZKc1dxl1CGB0Cqj0eQD8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908605; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MzcpXPRjhRqp+Fy3j7b0AOUvrSs6C4ggJpK7+di/i9I=; b=LcSqHfj3LManBTjwT5zEaGuyGO4BJwpwQGR6J2M8uPP7NjwLMKpdnMSZQo9uFuQSkgcnnS2LOJAv0qbzgmnRf1waPb7+hkxOVJps8+QepyYoN8JlQC8dGZ8sWaX2werBNoEgkgBeeRTu9WM5JNnc0EJQ9RBosHSh54qBgz5qCrY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908605123321.7698707223336; Fri, 28 Feb 2020 08:50:05 -0800 (PST) Received: from localhost ([::1]:50580 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ipu-0002FP-U4 for importer@patchew.org; Fri, 28 Feb 2020 11:50:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56711) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifT-00087h-Es for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifS-000242-1u for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:15 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:55833) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifR-00023P-Qr for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:13 -0500 Received: by mail-wm1-x342.google.com with SMTP id q9so3813325wmj.5 for ; Fri, 28 Feb 2020 08:39:13 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.39.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:39:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=MzcpXPRjhRqp+Fy3j7b0AOUvrSs6C4ggJpK7+di/i9I=; b=YHTEuaiywv6TwkaEpQ6y0Pr/eYo/MuLd+bW/CxXYFyS6XLWRgpJalfRmsEv33czlkp CqCSUX+5Z7hZ/8oYAf2G8WE2CIhmigaeQW9BURErQCN3FwoSLjQ12sQwyPGUn7fUnEt4 nUlbcTPXSA5R/eabQ5y9Oz1s4IExO/BELOocxKtzhgzVmU9N/jICp/lTSeRQxRKZGech WYKYumSxWRX6fbOnOiryoFmvFqPcGJ8om6ZcKcAC8Awj/pl5iauel4NedTOv15Eucu9K OHGW1Jf3iYJogkSZvhKjdIEl/Ofsf6TaaG3hqXSH7Sk2YC02TiuM9g8C6h24P1MxRYbN rzng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MzcpXPRjhRqp+Fy3j7b0AOUvrSs6C4ggJpK7+di/i9I=; b=b0JbWh8vlZH4uvpynV1gEEhI5MWpofN4wkg15DpaqJCg2mdZDn0/Moue0gYVienWd+ SzShAnr/L3rgZKVrzcaM2G95tuX/3PUpxIrWiwZSS8rE2IAn2Yr3ZGd/jQ4kN3RCiz3W L2DyVge6jFHbsAtG3r/yBG/M/5en9QqN/ueKxxYHP51Z8960WWi5+qGJmYN5oVpifICq uYSHuwuqQvwS2rH9s5uCSY2EbWPLqaPqqS9J5bm86A25BxnOEhAqujqzp2wNZ1tB7tl/ UvTMMoYvzhDsv1Xcft/i9Txwu14/xAR6bQDxMsRiB/FzLzkjoRgSN8olIQmD10fVxgk/ luMw== X-Gm-Message-State: APjAAAWPnAxQNvzHKv4aL3cGdDhf60fsYSjwF+ImhEb9Al0SwNhDVYUk 8LcQXQWrC+k/JsTtpe2yLKyAwnMuE+tVLA== X-Google-Smtp-Source: APXvYqweZBabnXeP+wV5O8uhPd4pdXk68ewudzcBz+O6ExOQJezLLbXdz/4m5kUMfvBq/PKV8r82Og== X-Received: by 2002:a1c:9c87:: with SMTP id f129mr5856634wme.26.1582907952559; Fri, 28 Feb 2020 08:39:12 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/33] tests/acceptance: Add a test for the integratorcp arm machine Date: Fri, 28 Feb 2020 16:38:33 +0000 Message-Id: <20200228163840.23585-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Thomas Huth There is a kernel and initrd available on github which we can use for testing this machine. Signed-off-by: Thomas Huth Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Wainer dos Santos Moschetta Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200225172501.29609-3-philmd@redhat.com Message-Id: <20200131170233.14584-1-thuth@redhat.com> [PMD: Renamed test method, moved description from class to method] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- MAINTAINERS | 1 + tests/acceptance/machine_arm_integratorcp.py | 43 ++++++++++++++++++++ 2 files changed, 44 insertions(+) create mode 100644 tests/acceptance/machine_arm_integratorcp.py diff --git a/MAINTAINERS b/MAINTAINERS index 264374adbe8..c258391cad8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -613,6 +613,7 @@ S: Maintained F: hw/arm/integratorcp.c F: hw/misc/arm_integrator_debug.c F: include/hw/misc/arm_integrator_debug.h +F: tests/acceptance/machine_arm_integratorcp.py =20 MCIMX6UL EVK / i.MX6ul M: Peter Maydell diff --git a/tests/acceptance/machine_arm_integratorcp.py b/tests/acceptanc= e/machine_arm_integratorcp.py new file mode 100644 index 00000000000..d928ed79b4c --- /dev/null +++ b/tests/acceptance/machine_arm_integratorcp.py @@ -0,0 +1,43 @@ +# Functional test that boots a Linux kernel and checks the console +# +# Copyright (c) 2020 Red Hat, Inc. +# +# Author: +# Thomas Huth +# +# This work is licensed under the terms of the GNU GPL, version 2 or +# later. See the COPYING file in the top-level directory. + +import os + +from avocado import skipUnless +from avocado_qemu import Test +from avocado_qemu import wait_for_console_pattern + +class IntegratorMachine(Test): + + timeout =3D 90 + + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code= ') + def test_integratorcp_console(self): + """ + Boots the Linux kernel and checks that the console is operational + :avocado: tags=3Darch:arm + :avocado: tags=3Dmachine:integratorcp + """ + kernel_url =3D ('https://github.com/zayac/qemu-arm/raw/master/' + 'arm-test/kernel/zImage.integrator') + kernel_hash =3D '0d7adba893c503267c946a3cbdc63b4b54f25468' + kernel_path =3D self.fetch_asset(kernel_url, asset_hash=3Dkernel_h= ash) + + initrd_url =3D ('https://github.com/zayac/qemu-arm/raw/master/' + 'arm-test/kernel/arm_root.img') + initrd_hash =3D 'b51e4154285bf784e017a37586428332d8c7bd8b' + initrd_path =3D self.fetch_asset(initrd_url, asset_hash=3Dinitrd_h= ash) + + self.vm.set_console() + self.vm.add_args('-kernel', kernel_path, + '-initrd', initrd_path, + '-append', 'printk.time=3D0 console=3DttyAMA0') + self.vm.launch() + wait_for_console_pattern(self, 'Log in as root') --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908436; cv=none; d=zohomail.com; s=zohoarc; b=MzPNuDOA2S9GZWXQfiiM4FajUVERSnB/QvICiIj1Hzjt5aB5KlbnaupdcF1PLgkQYEq7IzmJddubDxVAGD4bXRT4JhzZSXtJjg8g+ZtNd8F5E0q9nKvAOYEQci2SthU1o6sDueo3TU+Fky/1hkj1ektFqh1lngwhY26V/3p5UqI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908436; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=deB/lxPKVSLn1ypxY7579PxrzfoDtHNbi+JWV5TUv2w=; b=iL38U2kSricLcG5/73etaHZAp3rb89uPqzRx6QdKXVBM4YYZPn/AgolzEiZKPl+OfUhzBzFBKDrkaRgUenV6mjsDYJUPQv321TP6V94VM7ximkPN2YUMC0+XlA80kFBc4zdOnemMXXWXjVsBA54svNDPKVl8wuEEvn3T78mmBmg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908436686487.6011351528199; Fri, 28 Feb 2020 08:47:16 -0800 (PST) Received: from localhost ([::1]:50524 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7inD-0006g3-Gm for importer@patchew.org; Fri, 28 Feb 2020 11:47:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56723) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifU-0008AO-FN for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:17 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifT-00024s-83 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:16 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:39593) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifT-00024L-1P for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:15 -0500 Received: by mail-wm1-x334.google.com with SMTP id c84so3871855wme.4 for ; Fri, 28 Feb 2020 08:39:14 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.39.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:39:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=deB/lxPKVSLn1ypxY7579PxrzfoDtHNbi+JWV5TUv2w=; b=F7O+cBQJSbxljWBlBDC7IKP6gOcKhptKS2MtgYikp8W5ewT2oCm0d2BetfQD4vdXQQ p2+Lg49R49sOJqJQex3OVjAHI7/RdYLi4UH3J1NqefekI7o88AjcZqivCYw6L/pBeLLL IJEEBXnXmEtXsXhWd3+2dlPLYnXjg1/sjlId1QQIPCM0I62k17vOpVh7lkMO2Z2igFnm R36/oY5+sjvED4ch7JTrykwSlPvyiPZzTYYnGlkKEB5AiCaJPrRuhA+BBttpRiGRSVas UMVIkocRuxkPumx8QbZSe/sYdP45DGogAoflq6f91xY5z+WkerB3XP9faCML5TEvyUsQ H9Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=deB/lxPKVSLn1ypxY7579PxrzfoDtHNbi+JWV5TUv2w=; b=MxesmXY7jprNzXgh8tHYgm8R2fn53neAp9Ono8oFE80ZTf+QrHarnQgEYiGoxyxfcj ICSnMigEJQ9A08a/1wUco0gH9ye4VlKryD52Mkbv2IEbG5tdAlqJvycqYinyws4lRLTB UNJni7dZBoj2KEbRvcKme8upqf7epXTTKY2SlNPbr2dnIWZBPv/GWRSS/3Zg8Ws90frH v6PLznxU8rxlHw+LtLl+U3KwwkqUjSS3MEx5McpuOMEiG7NhMpA9+uL2ANo8c/1expAd lHn7domIR624AIu2xC3IZsYe7Vew/S7KS1vym2b+ftG3LGABBACuwcpSroJIijDpJZ/0 CLMw== X-Gm-Message-State: APjAAAXndCGsuB+/VMZ2mn7AOuXtTrkb5GovfCCVb0f9aDEIDysERUGz +FjEAREYRgUa2QjP+S0AUPalC13IDrPJJQ== X-Google-Smtp-Source: APXvYqzjmIUCdGcOimhBmCoRZDXENAetD+QGvhY3WU7wip4NRHRi+sHXFkIDbQ1qUfUO6LtibraXJg== X-Received: by 2002:a1c:a5c2:: with SMTP id o185mr3558677wme.173.1582907953570; Fri, 28 Feb 2020 08:39:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/33] tests/acceptance: Extract boot_integratorcp() from test_integratorcp() Date: Fri, 28 Feb 2020 16:38:34 +0000 Message-Id: <20200228163840.23585-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::334 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 As we want to re-use this code, extract it as a new function. Since we are using the PL011 serial console, add a Avocado tag to ease filtering of tests. Reviewed-by: Thomas Huth Reviewed-by: Wainer dos Santos Moschetta Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200225172501.29609-4-philmd@redhat.com Signed-off-by: Peter Maydell --- tests/acceptance/machine_arm_integratorcp.py | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/tests/acceptance/machine_arm_integratorcp.py b/tests/acceptanc= e/machine_arm_integratorcp.py index d928ed79b4c..22afd3b82a8 100644 --- a/tests/acceptance/machine_arm_integratorcp.py +++ b/tests/acceptance/machine_arm_integratorcp.py @@ -18,13 +18,7 @@ class IntegratorMachine(Test): =20 timeout =3D 90 =20 - @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code= ') - def test_integratorcp_console(self): - """ - Boots the Linux kernel and checks that the console is operational - :avocado: tags=3Darch:arm - :avocado: tags=3Dmachine:integratorcp - """ + def boot_integratorcp(self): kernel_url =3D ('https://github.com/zayac/qemu-arm/raw/master/' 'arm-test/kernel/zImage.integrator') kernel_hash =3D '0d7adba893c503267c946a3cbdc63b4b54f25468' @@ -40,4 +34,14 @@ class IntegratorMachine(Test): '-initrd', initrd_path, '-append', 'printk.time=3D0 console=3DttyAMA0') self.vm.launch() + + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code= ') + def test_integratorcp_console(self): + """ + Boots the Linux kernel and checks that the console is operational + :avocado: tags=3Darch:arm + :avocado: tags=3Dmachine:integratorcp + :avocado: tags=3Ddevice:pl011 + """ + self.boot_integratorcp() wait_for_console_pattern(self, 'Log in as root') --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582909760; cv=none; d=zohomail.com; s=zohoarc; b=WwTPLO0XxT32i5aUlyCTkTYWxtdRWO6NbGwjlL3+rLb8DGQYh09P7N7tfnHhjFxihOwfPhYOgZdfnUN0RMKdhUHAw8E17sSrCaYzDTqT9p8MaA07u6bewZMD1Thl4gZqPjQ1P7C4hrTrO62rOt9BK6nAdIbhCAWQwll2A/hZIeQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582909760; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hTbY0nJfRg44cC4x/jkt29PNMvHIJImu3BmtAxBXRUA=; b=GyKPBf3i6xuga+FoTfuz3JQ8h6Y3zK9e8G3PtsE8Byyyiuh7yzLMmxMCbOtDFz++t/GGwetOtFhfZyTl5I7ZcFC369XBj42bW4t3seXwURD4t59GA+0BbUAGTg4e9LWYzHY36EIA++YTl4/s8UvJnyAg+3lKSsWvxp01/nmkh3I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582909760069425.7754876899452; Fri, 28 Feb 2020 09:09:20 -0800 (PST) Received: from localhost ([::1]:50980 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7j8Y-0000HW-Jh for importer@patchew.org; Fri, 28 Feb 2020 12:09:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56738) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifV-0008DU-Lw for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifU-00025Y-8u for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:17 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:55450) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifU-000256-2D for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:16 -0500 Received: by mail-wm1-x334.google.com with SMTP id q9so3813450wmj.5 for ; Fri, 28 Feb 2020 08:39:15 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.39.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:39:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hTbY0nJfRg44cC4x/jkt29PNMvHIJImu3BmtAxBXRUA=; b=aeG0pYb/ggqslbXgJm/hF6BjCA4tRiDrvAm8kOn4xhxTdW1suW+X2lH1a0PaqaHj+d 1edvoZTMikv1vWDxLLgIchq6KuDR8FRp7SmJw/1B8yV+eCjTiskTX6ZinMqAtw6GNZD3 /oyGAqTKDhGBLgjFm4Qel2zIHkxdHkQ8BChUAYCZNJClB0tPdtP4PD55zlKsIr3RukoA Ir8St7AVjk5DH5AqAQnSKJnhsvXPdz5nl6zhyrETGRfSapUyDsy/wx1+sPagwX9PURzs B50ts03pxKt5ZACVJUcT2IDMYQM7KCD7p+REHsQ6zIpHFrW0mnBTdON60VHALvcexw+R e2nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hTbY0nJfRg44cC4x/jkt29PNMvHIJImu3BmtAxBXRUA=; b=fA0KA2X27xejjFaIagtxcZpdAY7Ra08T1TollTKDqFYDFH6WsVp4PYDwGiP8zkZ4lq gOkDeWh99eQKmMQwS51pPKWXrLTKMxPYqwYAjjll7KgoNOzimy3jgRTVawgvRSe0QbE7 CJZxfjEJDpJnPXh7OgnDtU8UmeXlhz1/SRB1LlhpS9jgurLLSLF79BFwvQV4mh265EwD RKI+HB+iwSXQJE17dWQX7oQUyf2hXzenX7WUO9hfww/GY7n32Owp2diP5m6ddDfVpyfm vJLDVEPL/Q7eirnBBm2Xif1gsYkXsrFzFai3uxmTlKhE54wP38gEbJ3ovyel1O5SNKlt epNw== X-Gm-Message-State: APjAAAUrtkNec2kL4hR67LN6qKXz6P7v+dG97faPcajrmPmDNNDqyeJ+ 9ewa6+AsIYgMJNHnbA9cuQsMFy1CVfnQtQ== X-Google-Smtp-Source: APXvYqwzkbW/MZ5n/ULQ9POm2Xt/rCkrJAFh4nPR4gciBW6mTqdU92Bn4tCNNLSYLXViozlcIQvJXQ== X-Received: by 2002:a05:600c:290:: with SMTP id 16mr3131736wmk.64.1582907954723; Fri, 28 Feb 2020 08:39:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/33] tests/acceptance/integratorcp: Verify Tux is displayed on framebuffer Date: Fri, 28 Feb 2020 16:38:35 +0000 Message-Id: <20200228163840.23585-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::334 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 Add a test that verifies the Tux logo is displayed on the framebuffer. We simply follow the OpenCV "Template Matching with Multiple Objects" tutorial, replacing Lionel Messi by Tux: https://docs.opencv.org/4.2.0/d4/dc6/tutorial_py_template_matching.html When OpenCV and NumPy are installed, this test can be run using: $ AVOCADO_ALLOW_UNTRUSTED_CODE=3Dhmmm \ avocado --show=3Dapp,framebuffer run -t device:framebuffer \ tests/acceptance/machine_arm_integratorcp.py JOB ID : 8c46b0f8269242e87d738247883ea2a470df949e JOB LOG : avocado/job-results/job-2020-01-31T21.38-8c46b0f/job.log (1/1) tests/acceptance/machine_arm_integratorcp.py:IntegratorMachine.tes= t_framebuffer_tux_logo: framebuffer: found Tux at position [x, y] =3D (0, 0) PASS (3.96 s) RESULTS : PASS 1 | ERROR 0 | FAIL 0 | SKIP 0 | WARN 0 | INTERRUPT 0 | = CANCEL 0 JOB TIME : 4.23 s Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Wainer dos Santos Moschetta Message-id: 20200225172501.29609-5-philmd@redhat.com Message-Id: <20200131211102.29612-3-f4bug@amsat.org> Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- tests/acceptance/machine_arm_integratorcp.py | 52 ++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/tests/acceptance/machine_arm_integratorcp.py b/tests/acceptanc= e/machine_arm_integratorcp.py index 22afd3b82a8..49c8ebff78b 100644 --- a/tests/acceptance/machine_arm_integratorcp.py +++ b/tests/acceptance/machine_arm_integratorcp.py @@ -9,11 +9,26 @@ # later. See the COPYING file in the top-level directory. =20 import os +import logging =20 from avocado import skipUnless from avocado_qemu import Test from avocado_qemu import wait_for_console_pattern =20 + +NUMPY_AVAILABLE =3D True +try: + import numpy as np +except ImportError: + NUMPY_AVAILABLE =3D False + +CV2_AVAILABLE =3D True +try: + import cv2 +except ImportError: + CV2_AVAILABLE =3D False + + class IntegratorMachine(Test): =20 timeout =3D 90 @@ -45,3 +60,40 @@ class IntegratorMachine(Test): """ self.boot_integratorcp() wait_for_console_pattern(self, 'Log in as root') + + @skipUnless(NUMPY_AVAILABLE, 'Python NumPy not installed') + @skipUnless(CV2_AVAILABLE, 'Python OpenCV not installed') + @skipUnless(os.getenv('AVOCADO_ALLOW_UNTRUSTED_CODE'), 'untrusted code= ') + def test_framebuffer_tux_logo(self): + """ + Boot Linux and verify the Tux logo is displayed on the framebuffer. + :avocado: tags=3Darch:arm + :avocado: tags=3Dmachine:integratorcp + :avocado: tags=3Ddevice:pl110 + :avocado: tags=3Ddevice:framebuffer + """ + screendump_path =3D os.path.join(self.workdir, "screendump.pbm") + tuxlogo_url =3D ('https://github.com/torvalds/linux/raw/v2.6.12/' + 'drivers/video/logo/logo_linux_vga16.ppm') + tuxlogo_hash =3D '3991c2ddbd1ddaecda7601f8aafbcf5b02dc86af' + tuxlogo_path =3D self.fetch_asset(tuxlogo_url, asset_hash=3Dtuxlog= o_hash) + + self.boot_integratorcp() + framebuffer_ready =3D 'Console: switching to colour frame buffer d= evice' + wait_for_console_pattern(self, framebuffer_ready) + self.vm.command('human-monitor-command', command_line=3D'stop') + self.vm.command('human-monitor-command', + command_line=3D'screendump %s' % screendump_path) + logger =3D logging.getLogger('framebuffer') + + cpu_count =3D 1 + match_threshold =3D 0.92 + screendump_bgr =3D cv2.imread(screendump_path) + screendump_gray =3D cv2.cvtColor(screendump_bgr, cv2.COLOR_BGR2GRA= Y) + result =3D cv2.matchTemplate(screendump_gray, cv2.imread(tuxlogo_p= ath, 0), + cv2.TM_CCOEFF_NORMED) + loc =3D np.where(result >=3D match_threshold) + tux_count =3D 0 + for tux_count, pt in enumerate(zip(*loc[::-1]), start=3D1): + logger.debug('found Tux at position [x, y] =3D %s', pt) + self.assertGreaterEqual(tux_count, cpu_count) --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908593; cv=none; d=zohomail.com; s=zohoarc; b=gWJrTeyUt/H4+9Y6YtxbwrRHlHuhO0GgIN0jOHbRYG3zbh8Ub/xYvT1WMiq2vtW0vb7ve8ZCM1GRk7uz6qqDdqj85sU3YqPhMnxWcZcTvSw+t37GUisv4l2Ee1cvqzf99XH32Z59E1PX0F5ij//S9IkkRzV47anBub8kuzRBCgc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908593; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hNvRKTnbKU1Ze0BRTs7wvEYB7FrEi57d2LPXeti1ezI=; b=ZBAQGEwjGlcoPjn6nt2DUYmHDIO+z9/gOfPIXkgN8OXH41VelOm9hzTeNgU2dk0MbCSFbXQsssdUIkXgVazcHh0UbIyQbXL4ABDWlp3Y+b4uioydsjgr3jU2iVfXU5oxI/HcGQcf/F6Hs64e0i5zk9DaZkHLb6Kidi1nb15I56U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908592919319.8898317412338; Fri, 28 Feb 2020 08:49:52 -0800 (PST) Received: from localhost ([::1]:50576 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ipj-0001nU-Oj for importer@patchew.org; Fri, 28 Feb 2020 11:49:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56745) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifW-0008Ep-5R for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifV-00026D-5R for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:18 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:33415) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifU-00025d-VL for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:17 -0500 Received: by mail-wr1-x42e.google.com with SMTP id x7so3711614wrr.0 for ; Fri, 28 Feb 2020 08:39:16 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.39.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:39:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hNvRKTnbKU1Ze0BRTs7wvEYB7FrEi57d2LPXeti1ezI=; b=l1j5jm4B4rdnikvoqsu8rgIZkESfAb7vg30sd777MvPd+qWdq3qRun3ZH6RJQX0EEH gd+jRGMNzbzvRVpRSpv8rHCJL76pA7nz6V7laEBIkyGNvBPoFglBCNOZjYvZNghuW/G8 Xx106gkDWsO67sI1W+6m3biDOeH0oHwKs1H0tgn/kuewqoCiZQryP75sezvVpxHMIfHx ARm2ZCSiYb7qmXculNt1t5+s26RFENZ6Y9jDXdrtk3ch6hJrlgnNp4+Uwp1I22qLJiFH C58EFGuSVwuYHMKyg49puqzu7rt+wbjzXLGcMIhE1whzaiknOr12MP57V7qWGb6Rk/Hr U2Ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hNvRKTnbKU1Ze0BRTs7wvEYB7FrEi57d2LPXeti1ezI=; b=E7pdIMf1m01DI7bx4wn8cyi7wNgUlsbR+cMUidIGX+IE+auK3PM0J9Lk8ka32ogvdu uPAKUcR1OQfpkFWJzTgDSlMw1pJxKjjL5Ur3sKlIt5dCo0C54pM4A5lhlDZDUGBBd6er dNJXhKGSAtK0C5K+0kkaDmQoSrMTJNZskGJVVwi2BeYqzZALVZL+PJzjr3BWr0UCHu49 bDw1Mp0svjlUc1lz2hMUa2heVDtWnfK0w6plh0hUUICLPrdCQfcAhDapCHS+hxT/MKBc bQNUHsCICNTZGII8F7pVofeWSFqY+G5xdyr5H5PluN1jH0BuJkUMhynj+NFr7DT9Prhe KhPQ== X-Gm-Message-State: APjAAAVpPfcq14PI7XM9O7vWb59vKMUciP6+QisZ2dDVwkBOWcfsPLdT TJSh+zKuznZfn8O8LEM1m5/dcvgwuekM0g== X-Google-Smtp-Source: APXvYqxfQDxZ0gWENdOjOrb2n3Xf9SXGemyJNJRbrxAo+7rn4aeYkeNTpKKD2TU1ZFqXgKMzK56UYw== X-Received: by 2002:a5d:638b:: with SMTP id p11mr5708897wru.338.1582907955755; Fri, 28 Feb 2020 08:39:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/33] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 Date: Fri, 28 Feb 2020 16:38:36 +0000 Message-Id: <20200228163840.23585-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42e X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) We missed an instance of using FIELD_EX32 on a 64-bit ID register, in isar_feature_aa64_pmu_8_4(). Fix it. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-id: 20200224172846.13053-2-peter.maydell@linaro.org --- target/arm/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 05aa9711cd8..6013287f623 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3770,8 +3770,8 @@ static inline bool isar_feature_aa64_pmu_8_1(const AR= MISARegisters *id) =20 static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) { - return FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 5 && - FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 5 && + FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 /* --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908704; cv=none; d=zohomail.com; s=zohoarc; b=hvL89XOiMrWYZZIX9DIY9zSzm//M53zOxJvYVhCMdTRr8JJ8UFWP43nHcnX/Y8vw+DAigIETvHv1quX47UOBbbAv7iw24235+iVGX1jnBBob10Z8UzpkX3i350scUvPyariyjxUbneBgidk4mC8sDzJmWGi1oyYCxyeJPRGRNYU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908704; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zxcAJSx6I1dBt0++qxyzNQdup6sZi0n4/zNIAaI5fJc=; b=GA/MPEN5EGxAqmDBgUKistUiqCWkLVm9wvDCqn2Khaiw83BWPoe3T2ATMiC8LVbbS6QLuuA/cfLt0m6lxLadXed5jUCEegxpH6EnEdHaoFZhjKM8iFk/Ks0wkDn86WtnyfWZul1S4Da/xq8OByOJlVQLZixJ+ZWlQ2EItYGW0tE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908704736281.3343244317675; Fri, 28 Feb 2020 08:51:44 -0800 (PST) Received: from localhost ([::1]:50636 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7irX-0005Im-80 for importer@patchew.org; Fri, 28 Feb 2020 11:51:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56766) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifX-0008Hy-E2 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:20 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifW-000272-5k for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:19 -0500 Received: from mail-wr1-x42e.google.com ([2a00:1450:4864:20::42e]:35766) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifV-00026P-VB for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:18 -0500 Received: by mail-wr1-x42e.google.com with SMTP id r7so3700178wro.2 for ; Fri, 28 Feb 2020 08:39:17 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.39.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:39:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zxcAJSx6I1dBt0++qxyzNQdup6sZi0n4/zNIAaI5fJc=; b=a8izAkQ+LahKJLwJkFwoQH2ql7SBI0sxUA6t2hCxx85lkFKE6x/iASCVu310eO1u36 pN//E3hTlLi0Eg5RtnjOSaGVTf/WdufwrCAUjJRdOqo0dPIlDo93CDDYNUY0rWhmQh5w 9PAu4oC83AI++SU9Twq026YeCX5k0IfHLlkXDMEuU05jQR+L+ud2AaLLy1z9TdIQCm4k 0ykJM0A3P24SKBaOfoAu5GHH6dz29fOWc+tsTXjkFHoDfyfQ0CKop4XzkdRZ0gIRUWPu e5BBvw0jQ6YWBangLOUkA4N3mFS6jg+qqunRvpthzDnxZWBqRp3FJe8ayxyJxGgZLVk0 cVFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zxcAJSx6I1dBt0++qxyzNQdup6sZi0n4/zNIAaI5fJc=; b=K/clyhASe7gZyo/i85EoQ4+cTjhczHP23KLZKLe4uWtBNDBeJQ0iZNBpzl4TDRDl4y tHVroaQ7jyjxajouo1HemN588ngbt8jKz7+fZC+sJIerVw/MXrvUI/YbujadnRUlamm4 1XGOwpTU1ZgGT8lM+Bx1cLkkeU6zaSHwLVTnBJAU8EUJZ7vSjJvg6I5NOUDt0Fg080QN 6DJPnuN7fFIhMN2jHzT7h6qDiC36NtTzogq8FOWGC/P+0iSvmXs93KUCbaYnYcbh5b3n tRD7KvzWdpXnGxWcfKgrX1lYymWoV+sbWEbj/RurOzYVcELQiMzsi3kfMbiYvTvqXiu9 AGTQ== X-Gm-Message-State: APjAAAVLFfmkrjK4eJ7DLoXVSh9SCByNqPXV/m+VrMWbuxBl/x6Q/Jst wiMd55f0MqfYzuH+cgeCB82Y4Cpfv9K3zQ== X-Google-Smtp-Source: APXvYqz0mZm6uzXMTYmEEvkxRXVUia+nsICpj+tbEFEW1PTOCBNhp6SV8X2dxgR1/gWfcCFvYOFeFA== X-Received: by 2002:adf:f012:: with SMTP id j18mr5551363wro.314.1582907956619; Fri, 28 Feb 2020 08:39:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/33] target/arm: Implement v8.3-RCPC Date: Fri, 28 Feb 2020 16:38:37 +0000 Message-Id: <20200228163840.23585-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42e X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The v8.3-RCPC extension implements three new load instructions which provide slightly weaker consistency guarantees than the existing load-acquire operations. For QEMU we choose to simply implement them with a full LDAQ barrier. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200224172846.13053-3-peter.maydell@linaro.org --- target/arm/cpu.h | 5 +++++ linux-user/elfload.c | 1 + target/arm/cpu64.c | 1 + target/arm/translate-a64.c | 24 ++++++++++++++++++++++++ 4 files changed, 31 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6013287f623..ff30985ead4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3774,6 +3774,11 @@ static inline bool isar_feature_aa64_pmu_8_4(const A= RMISARegisters *id) FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 +static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) !=3D 0; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 86cda127b78..d76b828a789 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -661,6 +661,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP); + GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC); =20 return hwcaps; } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 8f2a43c938a..18c7b40f98c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -654,6 +654,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 1); /* ARMv8.3-RCPC */ cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64pfr0; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 596bf4cf734..7a066fb7cb2 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3142,6 +3142,8 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, int rs =3D extract32(insn, 16, 5); int rn =3D extract32(insn, 5, 5); int o3_opc =3D extract32(insn, 12, 4); + bool r =3D extract32(insn, 22, 1); + bool a =3D extract32(insn, 23, 1); TCGv_i64 tcg_rs, clean_addr; AtomicThreeOpFn *fn; =20 @@ -3177,6 +3179,13 @@ static void disas_ldst_atomic(DisasContext *s, uint3= 2_t insn, case 010: /* SWP */ fn =3D tcg_gen_atomic_xchg_i64; break; + case 014: /* LDAPR, LDAPRH, LDAPRB */ + if (!dc_isar_feature(aa64_rcpc_8_3, s) || + rs !=3D 31 || a !=3D 1 || r !=3D 0) { + unallocated_encoding(s); + return; + } + break; default: unallocated_encoding(s); return; @@ -3186,6 +3195,21 @@ static void disas_ldst_atomic(DisasContext *s, uint3= 2_t insn, gen_check_sp_alignment(s); } clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + + if (o3_opc =3D=3D 014) { + /* + * LDAPR* are a special case because they are a simple load, not a + * fetch-and-do-something op. + * The architectural consistency requirements here are weaker than + * full load-acquire (we only need "load-acquire processor consist= ent"), + * but we choose to implement them as full LDAQ. + */ + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, + true, rt, disas_ldst_compute_iss_sf(size, false, 0), tru= e); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + return; + } + tcg_rs =3D read_cpu_reg(s, rs, true); =20 if (o3_opc =3D=3D 1) { /* LDCLR */ --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908339; cv=none; d=zohomail.com; s=zohoarc; b=QcwMQ+gUWyF57akM+BBMcW27BXqBStCpE76bdzos+9TlJF6QoyFRRXjG5C6OHcIUYHxtaC6+pE4xI/MDIsKZLh4tJSrFSTgzP+g/cg6PpXEPsQhHTS+U09+KP/6dTL77IAzU+eZmNsruzx/uuzR4Mvc3m6qDZQMcsKvQEMIsr7c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908339; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kVj8xiNy7P+impZo0PATu9zmL7PfKEv61GKapK4HB3M=; b=gmJWPNO1dXKFdcO9evrWdtpFLbDVcAY3CL1tx7pTwswfrFl95hXeFs1xaSKANHwvUbrgnnY2sgKha2vN2VmKyjddRpCUzjAaTpMvv8El6MNK72FF69b2ANpyjBqMPUZ/XNjlb/9qG+vFnFqOnjE2WLSYEoiGJcAAi2p0jGklAUA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582908339406604.5936154152976; Fri, 28 Feb 2020 08:45:39 -0800 (PST) Received: from localhost ([::1]:50392 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ild-0003ys-Eh for importer@patchew.org; Fri, 28 Feb 2020 11:45:37 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56779) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifY-0008Kw-Mb for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifX-00027f-9T for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:20 -0500 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:45277) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifX-00027E-26 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:19 -0500 Received: by mail-wr1-x430.google.com with SMTP id v2so3600858wrp.12 for ; Fri, 28 Feb 2020 08:39:18 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.39.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:39:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=kVj8xiNy7P+impZo0PATu9zmL7PfKEv61GKapK4HB3M=; b=n5u91R6eRFocJHArmg6rLlH+evDOkI7c6BcilazFITxHqvtq/bJY3sQarvwKrgrwbX sPfHUTvM9y5wy/6lbJb28KIFW/AGSyTZtVriET4U6gxh3jwcgrSZqFpURbPITOeoeL5s 2ohZoqhaHlj9Yaa5v5p+CQMc4wxwfDRKKjWoEP12YqnpScanRXds+pYnBv8C2WSOUPb4 wpVbulEpDdSXICerpOzLPBUHpRzTiNC8ESIAmusj9B33ExJNetE8C9fEE1RJZG9gc7uQ zBuBGF/C7H0N+9VW7V8pVhG7UqtqZI83mF+pASeNxJK+LkYzP7y06vA0xVoVyWnVOgzH e8hA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kVj8xiNy7P+impZo0PATu9zmL7PfKEv61GKapK4HB3M=; b=PFYgKiAyoat/rx2ja9pNZFCtmRDTosZ+GCjvzVcSixZfZb5Z32M7oKcPD8vmbyKvb/ PpdTj6sS07xpoZz0lmPgSP9tX16sVJnOBabdbHSjwhHhai97dV/5nwQ2wdYwxzw4TfdQ kXh/sLsnehg3moc3orRH23UATwun2LGYVgsSzzpMjLzHAaQAtFdbOznxy3UZs+o5Vm41 uufdcbZhMCImPITWs027NVi/g5hocjci1t+gtI0Jo6RCQ7se/Qvi6O2OxdE0pMNa9x4R EZB6v7LMMU7LTE+J3Oq2cIbn9CpCmPOrusNPwQijZvYbcMD1IQOa8PPyISfH9hRXe0La Kcrw== X-Gm-Message-State: APjAAAXe3rxkuH6HfQm7bM6gaIDb8t9E6PMHrBJ5wGZhLRfzuj+z86gI OsBjPt3htfR2e9dTC30TJGLkXiDrVSOnrw== X-Google-Smtp-Source: APXvYqyrTvJxaFQ4V9KyXYLkW+WuW/Fpa6jxejFBRmsdMHkhctjVLCTihkQuNafdYzCpWLZWhDMqtA== X-Received: by 2002:a5d:628e:: with SMTP id k14mr5318873wru.425.1582907957592; Fri, 28 Feb 2020 08:39:17 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/33] target/arm: Implement v8.4-RCPC Date: Fri, 28 Feb 2020 16:38:38 +0000 Message-Id: <20200228163840.23585-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::430 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The v8.4-RCPC extension implements some new instructions: * LDAPUR, LDAPURB, LDAPURH, LDAPRSB, LDAPRSH, LDAPRSW * STLUR, STLURB, STLURH These are all in a new subgroup of encodings that sits below the top-level "Loads and Stores" group in the Arm ARM. The STLUR* instructions have standard store-release semantics; the LDAPUR* have Load-AcquirePC semantics, but (as with LDAPR*) we choose to implement them as the slightly stronger Load-Acquire. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200224172846.13053-4-peter.maydell@linaro.org --- target/arm/cpu.h | 5 +++ linux-user/elfload.c | 1 + target/arm/cpu64.c | 2 +- target/arm/translate-a64.c | 90 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 97 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ff30985ead4..ce1e2a090e5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3779,6 +3779,11 @@ static inline bool isar_feature_aa64_rcpc_8_3(const = ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) !=3D 0; } =20 +static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >=3D 2; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index d76b828a789..db748c58775 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -662,6 +662,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP); GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC); + GET_FEATURE_ID(aa64_rcpc_8_4, ARM_HWCAP_A64_ILRCPC); =20 return hwcaps; } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 18c7b40f98c..b842e2b664a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -654,7 +654,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 1); /* ARMv8.3-RCPC */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64pfr0; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7a066fb7cb2..579180af0a9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3283,6 +3283,88 @@ static void disas_ldst_pac(DisasContext *s, uint32_t= insn, } } =20 +/* + * LDAPR/STLR (unscaled immediate) + * + * 31 30 24 22 21 12 10 5 0 + * +------+-------------+-----+---+--------+-----+----+-----+ + * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt | + * +------+-------------+-----+---+--------+-----+----+-----+ + * + * Rt: source or destination register + * Rn: base register + * imm9: unscaled immediate offset + * opc: 00: STLUR*, 01/10/11: various LDAPUR* + * size: size of load/store + */ +static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) +{ + int rt =3D extract32(insn, 0, 5); + int rn =3D extract32(insn, 5, 5); + int offset =3D sextract32(insn, 12, 9); + int opc =3D extract32(insn, 22, 2); + int size =3D extract32(insn, 30, 2); + TCGv_i64 clean_addr, dirty_addr; + bool is_store =3D false; + bool is_signed =3D false; + bool extend =3D false; + bool iss_sf; + + if (!dc_isar_feature(aa64_rcpc_8_4, s)) { + unallocated_encoding(s); + return; + } + + switch (opc) { + case 0: /* STLURB */ + is_store =3D true; + break; + case 1: /* LDAPUR* */ + break; + case 2: /* LDAPURS* 64-bit variant */ + if (size =3D=3D 3) { + unallocated_encoding(s); + return; + } + is_signed =3D true; + break; + case 3: /* LDAPURS* 32-bit variant */ + if (size > 1) { + unallocated_encoding(s); + return; + } + is_signed =3D true; + extend =3D true; /* zero-extend 32->64 after signed load */ + break; + default: + g_assert_not_reached(); + } + + iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); + + if (rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + dirty_addr =3D read_cpu_reg_sp(s, rn, 1); + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + clean_addr =3D clean_data_tbi(s, dirty_addr); + + if (is_store) { + /* Store-Release semantics */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, iss_sf, t= rue); + } else { + /* + * Load-AcquirePC semantics; we implement as the slightly more + * restrictive Load-Acquire. + */ + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, is_signed, extend, + true, rt, iss_sf, true); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } +} + /* Load/store register (all forms) */ static void disas_ldst_reg(DisasContext *s, uint32_t insn) { @@ -3634,6 +3716,14 @@ static void disas_ldst(DisasContext *s, uint32_t ins= n) case 0x0d: /* AdvSIMD load/store single structure */ disas_ldst_single_struct(s, insn); break; + case 0x19: /* LDAPR/STLR (unscaled immediate) */ + if (extract32(insn, 10, 2) !=3D 0 || + extract32(insn, 21, 1) !=3D 0) { + unallocated_encoding(s); + break; + } + disas_ldst_ldapr_stlr(s, insn); + break; default: unallocated_encoding(s); break; --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582908477; cv=none; d=zohomail.com; s=zohoarc; b=Qlx2aJquv7viDJkZ7WfH803VkCDyz8KgTlk8wTdSYpbREGgJoTtJxut9M0jBD8S/bGSlgd4aZBjbxPV5O69mIw08vW3naiMAv1xHBxgJwC1k6SBvyfzIWglA1s8iTB2b36xhxUw9ufJCcFMGVcbumSOXrfFakTmoaeyg2TFuFmg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582908477; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5oQ35QsMhetApJIHGz3Rua7oGdC5Wob+G0lA1+c8/Fw=; b=QtjlEVj9JEbZFfJ0czdMwA0raOOdaZ0/pVnpDpkoMkh0775xqmpcz+oKt+Z/mLRyPuotlAu4uLHY9dv7srtCMxSYoybSvt20tSBl6qucBYnmM5yhUpQ9IICLeu4/hJdYvDkh3TiA7BkiGPVY9693RVPl7QESJyJsDEACm4Y38b8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158290847720992.54239972113157; Fri, 28 Feb 2020 08:47:57 -0800 (PST) Received: from localhost ([::1]:50534 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7inr-0007pY-T3 for importer@patchew.org; Fri, 28 Feb 2020 11:47:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56791) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifZ-0008NU-O9 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifY-00028I-9A for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:21 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:40817) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifY-00027p-2c for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:20 -0500 Received: by mail-wm1-x342.google.com with SMTP id d138so2304968wmd.5 for ; Fri, 28 Feb 2020 08:39:20 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.39.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:39:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=5oQ35QsMhetApJIHGz3Rua7oGdC5Wob+G0lA1+c8/Fw=; b=SCghQKzZ0n5jys0ixaZ7beD5qPwkCXiQKVoGJ20dZ5/0G+sizZg5xvKWaLmkkll2DB OFyHBjEJN5jqdG6kY4xVjH4D+1qulKIG2c2ywWSlLw1v7iKRRHk0CYQZVOaJlEzU6Q7C XfaIOZQxTrVnqnl5w3Ul2X79GXh5PnbrTzVqkX1g58JuTTuM2YhXvjzgusSVCtmzr+4W VFaz8BirU53/Hm5OxGictG37WLGgy6aLycahac4zrkM67slOmV9pzh0x5dmujhbCQTQp w0xjAIXJeRTdKjTbxAo1qtPUr7AHjjpP7VyBnHGgnZhTJeKhofrOAAuw1lPsd3AZgc+Y XsBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5oQ35QsMhetApJIHGz3Rua7oGdC5Wob+G0lA1+c8/Fw=; b=hIWZkcYPHU13m+4CmSvH7MOcR2+oesCfqMuxl5aSZoJgdbQSzcmDXiEo9TnVEDMxXo BDEUN2baF+wyFLurA0sjkA1ttObXRc7SOlJTFfSe5zXUqlTgJwNC9hawr2IC2ujsgBLd JR6b4w0OHkNS64EAbYUTNoR2BmjAjJHdvW8UVFVj8Fhm+dv/UYpGf6/0D6fCeBxAKw9n sisoxa5NHkx5WkAa/bAUNEW0BAhuJW1IPnZY5ndmcmIvEG2UzvC7pN8XO7MNCFyOglHS +NqA7Yq4qojU0py0wCHM1rOpwsqxx2LVz9a+gRmjQ6CWvQAfMrh6a88zDTHjq1/wpjFl qxhw== X-Gm-Message-State: APjAAAXFfCQTbmPbTFFZCUMdTti9PbwU09m2wV8B9AKfUntP/a4LRJ/a jTOtA5Hp/Q8J3FokFD8VjhVTykArWuBRKQ== X-Google-Smtp-Source: APXvYqzLA2MHcxBIs1BgVBXpU97gJfV1kBa/rD3UY91e4uu4953h+6GsBVgDgujcT+rAgcOPbfuj+A== X-Received: by 2002:a1c:750f:: with SMTP id o15mr5708199wmc.111.1582907958750; Fri, 28 Feb 2020 08:39:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/33] target/arm: Implement ARMv8.3-CCIDX Date: Fri, 28 Feb 2020 16:38:39 +0000 Message-Id: <20200228163840.23585-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The ARMv8.3-CCIDX extension makes the CCSIDR_EL1 system ID registers have a format that uses the full 64 bit width of the register, and adds a new CCSIDR2 register so AArch32 can get at the high 32 bits. QEMU doesn't implement caches, so we just treat these ID registers as opaque values that are set to the correct constant values for each CPU. The only thing we need to do is allow 64-bit values in our cssidr[] array and provide the CCSIDR2 accessors. We don't set the CCIDX field in our 'max' CPU because the CCSIDR constant values we use are the same as the ones used by the Cortex-A57 and they are in the old 32-bit format. This means that the extra regdef added here is unused currently, but it means that whenever in the future we add a CPU that does need the new 64-bit format it will just work when we set the cssidr values and the ID registers for it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200224182626.29252-1-peter.maydell@linaro.org --- target/arm/cpu.h | 17 ++++++++++++++++- target/arm/helper.c | 19 +++++++++++++++++++ 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ce1e2a090e5..0b84742b66a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -904,7 +904,7 @@ struct ARMCPU { /* The elements of this array are the CCSIDR values for each cache, * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc. */ - uint32_t ccsidr[16]; + uint64_t ccsidr[16]; uint64_t reset_cbar; uint32_t reset_auxcr; bool reset_hivecs; @@ -3577,6 +3577,11 @@ static inline bool isar_feature_aa32_ac2(const ARMIS= ARegisters *id) return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) !=3D 0; } =20 +static inline bool isar_feature_aa32_ccidx(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_mmfr4, ID_MMFR4, CCIDX) !=3D 0; +} + /* * 64-bit feature tests via id registers. */ @@ -3784,6 +3789,11 @@ static inline bool isar_feature_aa64_rcpc_8_4(const = ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >=3D 2; } =20 +static inline bool isar_feature_aa64_ccidx(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, CCIDX) !=3D 0; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ @@ -3807,6 +3817,11 @@ static inline bool isar_feature_any_pmu_8_4(const AR= MISARegisters *id) return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); } =20 +static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) +{ + return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 8841cc7fde8..6be9ffa09ef 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6726,6 +6726,21 @@ static const ARMCPRegInfo predinv_reginfo[] =3D { REGINFO_SENTINEL }; =20 +static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + /* Read the high 32 bits of the current CCSIDR */ + return extract64(ccsidr_read(env, ri), 32, 32); +} + +static const ARMCPRegInfo ccsidr2_reginfo[] =3D { + { .name =3D "CCSIDR2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 0, .crm =3D 0, .opc2 =3D 2, + .access =3D PL1_R, + .accessfn =3D access_aa64_tid2, + .readfn =3D ccsidr2_read, .type =3D ARM_CP_NO_RAW }, + REGINFO_SENTINEL +}; + static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInf= o *ri, bool isread) { @@ -7788,6 +7803,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, predinv_reginfo); } =20 + if (cpu_isar_feature(any_ccidx, cpu)) { + define_arm_cp_regs(cpu, ccsidr2_reginfo); + } + #ifndef CONFIG_USER_ONLY /* * Register redirections and aliases must be done last, --=20 2.20.1 From nobody Thu Dec 18 22:20:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582909903; cv=none; d=zohomail.com; s=zohoarc; b=O5bNhJuCRfKG4ro0uGBVOrJPE9lBUqv3YQO4cSAFCUFn9dXSP/pNhCd94/8tnSswyUAGKVoL59zvAAaJKTmidD9a9J/vDwv8AFVeNrEw1L1rV4opAwipIPAQ+VY+fIYnUs5RPFsAC2xsoitHssy3E3xLQB1Uupyfk5KBYqqNwm4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582909903; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9eBbOH0iWuMB9GEnPRYXejUJxzdgvoce0O5T0LTK50c=; b=Tc1tYQ6tlFegEs8uUI5uyGOshrxCAAwCerdhbRv4Gny4/V2/vQlOFYkieqITtUDJ1UF8XYlS3cEg1oMc61FnzwhgBINAa0bHkD5d/UbOZIx+E+hbnix7WGShiDjNwu4769sPCWOnqT9uxmsOiRgIQ/JQfRV0YpSw51gdCqpNylI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582909903877847.2740757895697; Fri, 28 Feb 2020 09:11:43 -0800 (PST) Received: from localhost ([::1]:51034 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7jAs-0004BL-I9 for importer@patchew.org; Fri, 28 Feb 2020 12:11:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56800) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7ifa-0008PR-H0 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:23 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ifZ-00028p-Cj for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:22 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:37428) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j7ifZ-00028S-5T for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:39:21 -0500 Received: by mail-wm1-x343.google.com with SMTP id a141so3906052wme.2 for ; Fri, 28 Feb 2020 08:39:21 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id c9sm13335214wrq.44.2020.02.28.08.39.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2020 08:39:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9eBbOH0iWuMB9GEnPRYXejUJxzdgvoce0O5T0LTK50c=; b=vjaRrWkXCn/6xIFIZqWZ9vmo176BfKUwna2HsJnX5ctBNlYEcnuvNESEjEe2BkFILl wgxV8MdTm8054TpkKhmgBAf7WKoUp5zmAtb553tDN7gM8zAFou1DG6thQiqhHHUtTuLF NgkLE6kjGw0yfek887/ionU7N1NkN1G3oZ92dPGvZ8dBJvrFSf+R2rCk5k0D1bA18x9c MEdES4sMGPireYNO7+DxK7zmVBKNPA9OLtbhXluRan5lCCkaV8qNcrrqTcK4JaI4mapw JrBPFNy+F41kR5iQQL7uc+aJxGKR4CRUS8KSXH/1SRqnYOPNNTBjKS88E2sk8ZDYfB8j DWcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9eBbOH0iWuMB9GEnPRYXejUJxzdgvoce0O5T0LTK50c=; b=l2NGK59FkTahJX4TpD8rI+YE6H3M1pm3wcbu1fxQGGdrE54evfgbnyDcETP249/eK+ EFTTWXKhiRL+ig+hx9lCL2ZQ3j/9d8DXUAbp9Rx5taeKBiSwJ1/96b+5HAyxhzJw+/AW MeZKVBbxC1/DnwenjJlwPt4UDL1mlQKaJOw5+U5Utaf02S2d+Iz484SCXUZbAWJZKxQn EYra0KJY9Ib2YGFfMHaw16EEJfQxB/iFklgkknBsKWdhP04A5nfaIhfYcUxqPIAbhLGS m6RpC5kgzB+YVUWN3PYkHuHnzylG/m3w0Sk0unH69TpK3763+Vm3yxkTxrMTggBsgDEr FsiQ== X-Gm-Message-State: APjAAAW9kht9cK3Fag/kJfYQaHz4/BlqxkrWWSpW92umUVMPcBmnUfsw xeLI7oDPqxD2UGK4/SVqiqA+z/1wkchGDg== X-Google-Smtp-Source: APXvYqy+HaQZtC+M6A7ZKd592/T/7G2eP+lMgXh+J0NCw/kFlt/YlXtePH9KPF7y4BOnuWLoeRIYyA== X-Received: by 2002:a1c:3b89:: with SMTP id i131mr3926263wma.171.1582907959828; Fri, 28 Feb 2020 08:39:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/33] hw/intc/arm_gic_kvm: Don't assume kernel can provide a GICv2 Date: Fri, 28 Feb 2020 16:38:40 +0000 Message-Id: <20200228163840.23585-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200228163840.23585-1-peter.maydell@linaro.org> References: <20200228163840.23585-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) In our KVM GICv2 realize function, we try to cope with old kernels that don't provide the device control API (KVM_CAP_DEVICE_CTRL): we try to use the device control, and if that fails we fall back to assuming that the kernel has the old style KVM_CREATE_IRQCHIP and that it will provide a GICv2. This doesn't cater for the possibility of a kernel and hardware which only provide a GICv3, which is very common now. On that setup we will abort() later on in kvm_arm_pmu_set_irq() when we try to wire up an interrupt to the GIC we failed to create: qemu-system-aarch64: PMU: KVM_SET_DEVICE_ATTR: Invalid argument qemu-system-aarch64: failed to set irq for PMU Aborted If the kernel advertises KVM_CAP_DEVICE_CTRL we should trust it if it says it can't create a GICv2, rather than assuming it has one. We can then produce a more helpful error message including a hint about the most probable reason for the failure. If the kernel doesn't advertise KVM_CAP_DEVICE_CTRL then it is truly ancient by this point but we might as well still fall back to a KVM_CREATE_IRQCHIP GICv2. With this patch then the user misconfiguration which previously caused an abort now prints: qemu-system-aarch64: Initialization of device kvm-arm-gic failed: error cre= ating in-kernel VGIC: No such device Perhaps the host CPU does not support GICv2? Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Andrew Jones Tested-by: Andrew Jones Message-id: 20200225182435.1131-1-peter.maydell@linaro.org --- hw/intc/arm_gic_kvm.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index 9deb15e7e69..d7df423a7a3 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -551,7 +551,16 @@ static void kvm_arm_gic_realize(DeviceState *dev, Erro= r **errp) KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); } + } else if (kvm_check_extension(kvm_state, KVM_CAP_DEVICE_CTRL)) { + error_setg_errno(errp, -ret, "error creating in-kernel VGIC"); + error_append_hint(errp, + "Perhaps the host CPU does not support GICv2?\n"= ); } else if (ret !=3D -ENODEV && ret !=3D -ENOTSUP) { + /* + * Very ancient kernel without KVM_CAP_DEVICE_CTRL: assume that + * ENODEV or ENOTSUP mean "can't create GICv2 with KVM_CREATE_DEVI= CE", + * and that we will get a GICv2 via KVM_CREATE_IRQCHIP. + */ error_setg_errno(errp, -ret, "error creating in-kernel VGIC"); return; } --=20 2.20.1