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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id g9sm3578527wme.41.2020.02.25.11.38.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Feb 2020 11:38:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=f7lizJW39lrCrOSU4Pue7Wc6hbrhiEMu+Lp7n3SwT3I=; b=UxL+IhZtH8qghvDvr4gPV8rzVvFEyD534RRZ9v6vfXVF22iC0BtPNshDHbXlaiLlzv Fvdx8Z40WnMN3YmQcyspH+itMYbEFS9y1/p8c4yGxYJLL0nIM3LdyKZEPs1haRKIi5FS gm+69csvJ05Tj1KHkcwCRr6VRJ6FzupOj/IAlozsXThLD6gHPLj8uMY1nULaF1xmAWJ/ F6d+AJRFTFUEbmana168bOnCADZwK7ahiBNAASsxi8NKkSgAGzmix1NwYqpR08KJe0/M /0Xlmsf0E5Xi2xlcxfnXm9jkCQQaj+9YABB9nxzloSxKZCktdxgEkhTbXimnBwtaJKkw XfQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=f7lizJW39lrCrOSU4Pue7Wc6hbrhiEMu+Lp7n3SwT3I=; b=JvQs9dkZWsDA5MZE1AKg4OVUtlKupWaw7AazA7cZL0FShO40ACJ+vppnSJOnSuYumu jBh+x/ypANOfYHycMRIVAA71eoyE/PxbfmjXwGKAc78wHtNLUvGI0IhgL7zOUbG/UFcc uWa7s39uxufFyiOBnZTTOutNDiTKHDA1xD7IZBpkzsPwLB8eyLy1O79ct0c3Pnp4hxvP Oh67bgIHd7CrCKC1gxrOJnfOhBpyfV93x1ydlsuuJ6WHZ3XUv/1Ig+u9FoNOh8w67lkF 6Kp9374/MCbC8a6xqsodeQV061QzyZ53kcd0g6ikIbxWu9yC0NOEDq1aE96SLWp2U0x2 Jkwg== X-Gm-Message-State: APjAAAU+V9DgsQ47f2HBk7IaN+iUxAm1907Huc1Iu5ABf6KMKt0sADca 2Sd5yIWzbQYGJ9jnHsC8svZ6Ww== X-Google-Smtp-Source: APXvYqzdu3vj+sgIgBJaxRIaBlxsvI/+PBhMtH3SSCaqqH0N86xNbQ8ZyBgS3u2uvD+jWawmG1eBJQ== X-Received: by 2002:a1c:1b11:: with SMTP id b17mr726822wmb.93.1582659505735; Tue, 25 Feb 2020 11:38:25 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH] target/arm: Implement (trivially) ARMv8.2-TTCNP Date: Tue, 25 Feb 2020 19:38:22 +0000 Message-Id: <20200225193822.18874-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The ARMv8.2-TTCNP extension allows an implementation to optimize by sharing TLB entries between multiple cores, provided that software declares that it's ready to deal with this by setting a CnP bit in the TTBRn_ELx. It is mandatory from ARMv8.2 onward. For QEMU's TLB implementation, sharing TLB entries between different cores would not really benefit us and would be a lot of work to implement. So we implement this extension in the "trivial" manner: we allow the guest to set and read back the CnP bit, but don't change our behaviour (this is an architecturally valid implementation choice). The only code path which looks at the TTBRn_ELx values for the long-descriptor format where the CnP bit is defined is already doing enough masking to not get confused when the CnP bit at the bottom of the register is set, so we can simply add a comment noting why we're relying on that mask. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.c | 1 + target/arm/cpu64.c | 2 ++ target/arm/helper.c | 4 ++++ 3 files changed, 7 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2eadf4dcb8b..64dc9509927 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2720,6 +2720,7 @@ static void arm_max_initfn(Object *obj) t =3D cpu->isar.id_mmfr4; t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ cpu->isar.id_mmfr4 =3D t; } #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0929401a4dd..e4d793a2415 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -679,6 +679,7 @@ static void aarch64_max_initfn(Object *obj) =20 t =3D cpu->isar.id_aa64mmfr2; t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); + t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ cpu->isar.id_aa64mmfr2 =3D t; =20 /* Replicate the same data to the 32-bit id registers. */ @@ -705,6 +706,7 @@ static void aarch64_max_initfn(Object *obj) =20 u =3D cpu->isar.id_mmfr4; u =3D FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ cpu->isar.id_mmfr4 =3D u; =20 u =3D cpu->isar.id_aa64dfr0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 79db169e046..911baf7bcb7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10572,6 +10572,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, t= arget_ulong address, =20 /* Now we can extract the actual base address from the TTBR */ descaddr =3D extract64(ttbr, 0, 48); + /* + * We rely on this masking to clear the RES0 bits at the bottom of the= TTBR + * and also to mask out CnP (bit 0) which could validly be non-zero. + */ descaddr &=3D ~indexmask; =20 /* The address field in the descriptor goes up to bit 39 for ARMv7 --=20 2.20.1