From nobody Thu Nov 13 22:09:57 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582654565; cv=none; d=zohomail.com; s=zohoarc; b=V6b7/R4DHGCspIv9NchNlYRIc7Y6T0Bwi3WG4F4ovA+td0uAgsjIwBbmAS8yH2zWx3gYvp74eTXaRKonVUUl969dCJM2rTFnpZ79u+dVewcuuR/gTvTuWTslahunVKJ+TSKjG0JLJqHpsinqp1NtzZUSoVWLT6PgO173WeyiiEI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582654565; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XSq3h8eAOylAKZlE56of8ferQEzDe3R6wID0JCCEJjA=; b=XNUUbzQJjROk4PyrWz7nCO11vimuhZwJUUKNMQJG5fcuEjkczjJEH2o5WhklRbgxwfMmO1QmTqiDQOlWpXP1a1NRYpYuwRygygWqY4rJUE/YGAh0SPsdOjPaExWnttnwMJQl7VQWKcxwIykKSBioeHsWWVpS+LJfNsBZFx7tnFA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582654565126448.4669334354834; Tue, 25 Feb 2020 10:16:05 -0800 (PST) Received: from localhost ([::1]:33514 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6ekV-0001Yz-V7 for importer@patchew.org; Tue, 25 Feb 2020 13:16:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35596) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6eda-0002ix-3n for qemu-devel@nongnu.org; Tue, 25 Feb 2020 13:08:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j6edY-0004mF-9T for qemu-devel@nongnu.org; Tue, 25 Feb 2020 13:08:53 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:35208) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j6edY-0004ko-1o for qemu-devel@nongnu.org; Tue, 25 Feb 2020 13:08:52 -0500 Received: by mail-pf1-x444.google.com with SMTP id i19so7617513pfa.2 for ; Tue, 25 Feb 2020 10:08:51 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id d69sm19069704pfd.72.2020.02.25.10.08.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Feb 2020 10:08:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=XSq3h8eAOylAKZlE56of8ferQEzDe3R6wID0JCCEJjA=; b=oiMCnCKTwt+ySdRPwFSeo5Q8Z5l9k+4mZxN6gOAn1BRWIa1u1FUYE5AbQtDP/s/rK2 YbVWtLUOa6KEYcxJyU9/SS87alehtb5SKfxgsWiq/HS3iGKtq9WKZonAI7kpqOyLmyPJ m+hvD7ZQV3iKZcMngcYIzciE2hd2hw1mMrqD2Ly/J3d6II0k8+XVNHbih5AMjEpi7nlU mAygIMu0/KL8uT4kG5IQLiQpiwsYTdeXUFm3ZYrE6/G03gFIJHzZdvRe+D9bosqL7f4B Q+L7o7j9Gb3kKa1Lvv7XH3WDpIFTQo0IhFXGJnsDe9fdc1PcHEGcsNCCgOYfyQXGGIlc /UaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XSq3h8eAOylAKZlE56of8ferQEzDe3R6wID0JCCEJjA=; b=ucSRW+MVrcwQ45qhO3R2toVqC8+9rNOQbPrr/TRg9f17Vflr7b3Vc4RH8ElyAv2tjZ p328Mzsiz/H/j6wRtkk0lIcEe6tLXTq3gaMt8eiTHPMxyoV3IRhSWC5iUM9X9AM+G/bU mrGC6U4hxBkHepYcdPqoaxh5MD4Pe/1K5FmqHvMh4e43RiiP6lyuzcaLNTYnGljQahT5 BybgXwlqyDItDxK8j7jJd4iQ1uXC4gDWh6XsiQzDvknM7LPCtr5Fz/SxF+mnl8+yoD87 SPiU9tXm+dH6/bKnu3YSzTi1WUt4u2H1vV9BxASIcpU2eKOpVXQ4i2wTWOmJok7ALsih JMFw== X-Gm-Message-State: APjAAAWMMtJo0yj0xU2nDdcSk+JkJioSI9vemdG/sXXIp+LkxSmbANe9 paukUaMZzrwsB3TAbQ3Ycv5D6QiZbLU= X-Google-Smtp-Source: APXvYqyiGBMUbAJ5qqNEWKEJjt7jt+ZzLG1zUDESAYHseCzR+q7xJp4ZKnLtnOEDTzv0Z+/3bGpdIg== X-Received: by 2002:a63:1a50:: with SMTP id a16mr57812863pgm.389.1582654130035; Tue, 25 Feb 2020 10:08:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 7/7] target/arm: Honor the HCR_EL2.TTLB bit Date: Tue, 25 Feb 2020 10:08:31 -0800 Message-Id: <20200225180831.26078-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200225180831.26078-1-richard.henderson@linaro.org> References: <20200225180831.26078-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This bit traps EL1 access to tlb maintenance insns. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 85 +++++++++++++++++++++++++++++---------------- 1 file changed, 55 insertions(+), 30 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ca67d6a770..20688d1a18 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -563,6 +563,16 @@ static CPAccessResult access_tacr(CPUARMState *env, co= nst ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +/* Check for traps from EL1 due to HCR_EL2.TTLB. */ +static CPAccessResult access_ttlb(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 1 && (arm_hcr_el2_eff(env) & HCR_TTLB))= { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_OK; +} + static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = value) { ARMCPU *cpu =3D env_archcpu(env); @@ -2285,41 +2295,53 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .type =3D ARM_CP_NO_RAW, .access =3D PL1_R, .readfn =3D isr_read }, /* 32 bit ITLB invalidates */ { .name =3D "ITLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 5, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiall_wri= te }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiall_write }, { .name =3D "ITLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 5, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_wri= te }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_write }, { .name =3D "ITLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 5, .opc2 =3D 2, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiasid_wr= ite }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiasid_write }, /* 32 bit DTLB invalidates */ { .name =3D "DTLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 6, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiall_wri= te }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiall_write }, { .name =3D "DTLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 6, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_wri= te }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_write }, { .name =3D "DTLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 6, .opc2 =3D 2, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiasid_wr= ite }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiasid_write }, /* 32 bit TLB invalidates */ { .name =3D "TLBIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D 7= , .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiall_wri= te }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiall_write }, { .name =3D "TLBIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D 7= , .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_wri= te }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_write }, { .name =3D "TLBIASID", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 2, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiasid_wr= ite }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiasid_write }, { .name =3D "TLBIMVAA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 3, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimvaa_wr= ite }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimvaa_write }, REGINFO_SENTINEL }; =20 static const ARMCPRegInfo v7mp_cp_reginfo[] =3D { /* 32 bit TLB invalidates, Inner Shareable */ { .name =3D "TLBIALLIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 3, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbiall_is_= write }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbiall_is_write }, { .name =3D "TLBIMVAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 3, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_is_= write }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_is_write }, { .name =3D "TLBIASIDIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 2, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, .writefn =3D tlbiasid_is_write }, { .name =3D "TLBIMVAAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 3, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, .writefn =3D tlbimvaa_is_write }, REGINFO_SENTINEL }; @@ -4780,51 +4802,51 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { /* TLBI operations */ { .name =3D "TLBI_VMALLE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vmalle1is_write }, { .name =3D "TLBI_VAE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_ASIDE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vmalle1is_write }, { .name =3D "TLBI_VAAE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 3, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VALE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VAALE1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 3, .opc2 =3D 7, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_VMALLE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vmalle1_write }, { .name =3D "TLBI_VAE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1_write }, { .name =3D "TLBI_ASIDE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 2, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vmalle1_write }, { .name =3D "TLBI_VAAE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 3, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1_write }, { .name =3D "TLBI_VALE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1_write }, { .name =3D "TLBI_VAALE1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 8, .crm =3D 7, .opc2 =3D 7, - .access =3D PL1_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL1_W, .accessfn =3D access_ttlb, .type =3D ARM_CP_NO_RA= W, .writefn =3D tlbi_aa64_vae1_write }, { .name =3D "TLBI_IPAS2E1IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 0, .opc2 =3D 1, @@ -4910,14 +4932,17 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { #endif /* TLB invalidate last level of translation table walk */ { .name =3D "TLBIMVALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 5, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_is_= write }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_is_write }, { .name =3D "TLBIMVAALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 7, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, .writefn =3D tlbimvaa_is_write }, { .name =3D "TLBIMVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 5, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimva_wri= te }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimva_write }, { .name =3D "TLBIMVAAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D= 7, .opc2 =3D 7, - .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .writefn =3D tlbimvaa_wr= ite }, + .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, + .writefn =3D tlbimvaa_write }, { .name =3D "TLBIMVALH", .cp =3D 15, .opc1 =3D 4, .crn =3D 8, .crm =3D= 7, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, .writefn =3D tlbimva_hyp_write }, --=20 2.20.1