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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id d69sm19069704pfd.72.2020.02.25.10.08.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Feb 2020 10:08:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VKycPInt6AkbSPRRcFBDTfCzpdXuH+EqY1piUn22Z/U=; b=gcoX65pX5P31puoa4CaN+lbwv6Li0z1XpohXEVfO5jperOWidBsQk+KiKSjxy2LQ39 MPx8G/ILZd+t2kJvwI1/bjngDFyxolXEpeh9f3/wqbolGSwcvd/s/ErN0NxLrE+ZYGYA ddv6MnLkpOeCfzrd1BLhXTgYy6de0U57Diyvn7FyOOCSgatZv7bMgM/2jQhm3TVxD/lM 6UaLjjGndXWb6SmDRaajGXSVKk3FB5gth62Rdj+PSwqkG7zVx8fjCvnWYf6FeoP8UZx2 1+NMn+DxEGZat62Oiq8VtTsrxNcYjfifJQAwYV/oJUlaTf0Y5XQ1r+XxBcldxqjSCnA2 pgFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VKycPInt6AkbSPRRcFBDTfCzpdXuH+EqY1piUn22Z/U=; b=fxIkujS2tSy/fmjnkI9g/zJspJc7pL46B5M4dIbyOuUXykmMq0K0rk6jJWq/wAlNiW 0oyS6zklDr48yS47ka63c8pxfNDGGv14EZW+aEfF2Ety1rp/nBzhnCDbWFrJfTOdEm3i HkYSR8sY2jGaTjteIPvHzNGKZxI15OopH/N99RDsCJKHGjnUgQuwHEnYehcdPzkrjcKz krzGIVA5zDRDy085h2P6SCJv4ZB1D4Xv3QpTlK7b5XBSsvcypjJBzzO2ARjuCvtsXQzF GVYe7s/6OqwU7U4xfXV8M0fZ72juHTOCKDVRLuorYLGw/uVvRew6j4qD6qHHZtBhGo6a bqNw== X-Gm-Message-State: APjAAAVCOCDUsAzrU04jy11L8iMzipvqSgFF09LtkqXg3j+qx8LNIH93 WBO4CyNI1eF9yZ7eBumeZUswFuuPBw8= X-Google-Smtp-Source: APXvYqzexH+SHtJ//5l4OVltNdvusd1W1CpfTqx/kBo6CfCUmL8tnkBMjhFzQKHQd3aLIgwg3OY+ig== X-Received: by 2002:a17:90a:c390:: with SMTP id h16mr181939pjt.131.1582654125937; Tue, 25 Feb 2020 10:08:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 6/7] target/arm: Honor the HCR_EL2.TPU bit Date: Tue, 25 Feb 2020 10:08:30 -0800 Message-Id: <20200225180831.26078-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200225180831.26078-1-richard.henderson@linaro.org> References: <20200225180831.26078-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This bit traps EL1 access to cache maintenance insns that operate to the point of unification. There are no longer any references to plain aa64_cacheop_access, so remove it. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v4: Fix el0 fallthru (pmm). --- target/arm/helper.c | 53 +++++++++++++++++++++++++++------------------ 1 file changed, 32 insertions(+), 21 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2d488554b7..ca67d6a770 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4301,19 +4301,6 @@ static const ARMCPRegInfo uao_reginfo =3D { .readfn =3D aa64_uao_read, .writefn =3D aa64_uao_write }; =20 -static CPAccessResult aa64_cacheop_access(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless - * SCTLR_EL1.UCI is set. - */ - if (arm_current_el(env) =3D=3D 0 && !(arm_sctlr(env, 0) & SCTLR_UCI)) { - return CP_ACCESS_TRAP; - } - return CP_ACCESS_OK; -} - static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) @@ -4336,6 +4323,28 @@ static CPAccessResult aa64_cacheop_poc_access(CPUARM= State *env, return CP_ACCESS_OK; } =20 +static CPAccessResult aa64_cacheop_pou_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* Cache invalidate/clean to Point of Unification... */ + switch (arm_current_el(env)) { + case 0: + /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ + if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { + return CP_ACCESS_TRAP; + } + /* fall through */ + case 1: + /* ... EL1 must trap to EL2 if HCR_EL2.TPU is set. */ + if (arm_hcr_el2_eff(env) & HCR_TPU) { + return CP_ACCESS_TRAP_EL2; + } + break; + } + return CP_ACCESS_OK; +} + /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru= ctions * Page D4-1736 (DDI0487A.b) */ @@ -4733,14 +4742,16 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { /* Cache ops: all NOPs since we don't emulate caches */ { .name =3D "IC_IALLUIS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 1, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .type =3D ARM_CP_NOP, + .accessfn =3D aa64_cacheop_pou_access }, { .name =3D "IC_IALLU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 5, .opc2 =3D 0, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .type =3D ARM_CP_NOP, + .accessfn =3D aa64_cacheop_pou_access }, { .name =3D "IC_IVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 5, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_access }, + .accessfn =3D aa64_cacheop_pou_access }, { .name =3D "DC_IVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 1, .access =3D PL1_W, .accessfn =3D aa64_cacheop_poc_access, @@ -4758,7 +4769,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DC_CVAU", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 11, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_access }, + .accessfn =3D aa64_cacheop_pou_access }, { .name =3D "DC_CIVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, @@ -4932,13 +4943,13 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .writefn =3D tlbiipas2_is_write }, /* 32 bit cache operations */ { .name =3D "ICIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 0, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, { .name =3D "BPIALLUIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D= 1, .opc2 =3D 6, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "ICIALLU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5= , .opc2 =3D 0, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, { .name =3D "ICIMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5= , .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, { .name =3D "BPIALL", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 6, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "BPIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 7, @@ -4952,7 +4963,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DCCSW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 10,= .opc2 =3D 2, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DCCMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 1, .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= pou_access }, { .name =3D "DCCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D = 14, .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, { .name =3D "DCCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 14= , .opc2 =3D 2, --=20 2.20.1