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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id d69sm19069704pfd.72.2020.02.25.10.08.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Feb 2020 10:08:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1+nBZoDaBAGVfWBfiFQULthtVj8wbsWbsm7r45A6ZqY=; b=Xrg+UwIgd2VBTIgfHkiRViOB/P9/VAD+BIIOqXfQwaIXs5Ftn9Ditm163s1n3zOy0v xOAw1N3iRm7RIb1EjgSwtu1dki+HaETltEUgBs0bd5v1YTnuwSLPmcarpEGM9eqNMcd2 De3jWgICdh+1WeUynrTS6d9rcbykWI/kSYFhmQ0tHI6KBSjMCaW1E9mX3U4ykmrONJ1e yVETPDL/tiDmB81oGrbVSS/GE/SMiyGUCO3ybAB05A2ouH1fij6Ve9kIcGFBZuEmtjeY lgJZ492NUf1JolZLDchcg671CIu9mKIT9gUK/wjHpVsgSdDWMprTCscJkTE9OCZcFO5I s1nw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1+nBZoDaBAGVfWBfiFQULthtVj8wbsWbsm7r45A6ZqY=; b=dV5syXtUO7nrA+ar9vibuQOu9O0ad7f2qibOrgZNmiIWlkejEzBPB+U3xr/DxEOAtb Pn/8Rf6iDNvUQEhce1j6NEhib2uhbssrwxbfEGBYLHrzILHZuNvrMJKs0HEmitmDvoy9 gF9KRIZd2FRZJXOsBhqk89G6bGwGRbvqRjX4Ob7vK/IS4/iI+/D8m3LZvV0fyyUNZOTB Kp2nXnRKTzlbYRYMXCOSAv79CEXu+KCRnNnl8Whf4nHu7eB+Ol8JSdmArpsbSw8vn4/J GDUDkgY/6T5was8BRcZX/ZF2ugRIuurVEiWvsbyL01Vj0G+HSBJXKehLKmreS9uEe+1y 3RxA== X-Gm-Message-State: APjAAAXWh7cmnO5aN/L69HKu2Hm9VkWrhE+zBF4edOJUc0i30ywAWhO3 jhmsiOxISIRFgXPLA+XsI8rPgiCf2kA= X-Google-Smtp-Source: APXvYqw2XNWhjtXR9XCV0qHnJqgpI0vFH4EdI2IPxgypKcLEOokI2/RIsrLdEFzsb+/1Am0G1THKkw== X-Received: by 2002:a17:90a:3841:: with SMTP id l1mr242449pjf.108.1582654122942; Tue, 25 Feb 2020 10:08:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 5/7] target/arm: Honor the HCR_EL2.TPCP bit Date: Tue, 25 Feb 2020 10:08:29 -0800 Message-Id: <20200225180831.26078-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200225180831.26078-1-richard.henderson@linaro.org> References: <20200225180831.26078-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This bit traps EL1 access to cache maintenance insns that operate to the point of coherency or persistence. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v4: Fix el0 fallthru (pmm). --- target/arm/helper.c | 39 +++++++++++++++++++++++++++++++-------- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5cb7844f3f..2d488554b7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4314,6 +4314,28 @@ static CPAccessResult aa64_cacheop_access(CPUARMStat= e *env, return CP_ACCESS_OK; } =20 +static CPAccessResult aa64_cacheop_poc_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + /* Cache invalidate/clean to Point of Coherency or Persistence... */ + switch (arm_current_el(env)) { + case 0: + /* ... EL0 must UNDEF unless SCTLR_EL1.UCI is set. */ + if (!(arm_sctlr(env, 0) & SCTLR_UCI)) { + return CP_ACCESS_TRAP; + } + /* fall through */ + case 1: + /* ... EL1 must trap to EL2 if HCR_EL2.TPCP is set. */ + if (arm_hcr_el2_eff(env) & HCR_TPCP) { + return CP_ACCESS_TRAP_EL2; + } + break; + } + return CP_ACCESS_OK; +} + /* See: D4.7.2 TLB maintenance requirements and the TLB maintenance instru= ctions * Page D4-1736 (DDI0487A.b) */ @@ -4721,14 +4743,15 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .accessfn =3D aa64_cacheop_access }, { .name =3D "DC_IVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 1, - .access =3D PL1_W, .type =3D ARM_CP_NOP }, + .access =3D PL1_W, .accessfn =3D aa64_cacheop_poc_access, + .type =3D ARM_CP_NOP }, { .name =3D "DC_ISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, { .name =3D "DC_CVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 10, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_access }, + .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 10, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, @@ -4739,7 +4762,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "DC_CIVAC", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NOP, - .accessfn =3D aa64_cacheop_access }, + .accessfn =3D aa64_cacheop_poc_access }, { .name =3D "DC_CISW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 2, .access =3D PL1_W, .accessfn =3D access_tsw, .type =3D ARM_CP_NOP }, @@ -4921,17 +4944,17 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "BPIMVA", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 5,= .opc2 =3D 7, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6= , .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, { .name =3D "DCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 6, = .opc2 =3D 2, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DCCMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 0, .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, { .name =3D "DCCSW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 10,= .opc2 =3D 2, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, { .name =3D "DCCMVAU", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 1= 1, .opc2 =3D 1, .type =3D ARM_CP_NOP, .access =3D PL1_W }, { .name =3D "DCCIMVAC", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D = 14, .opc2 =3D 1, - .type =3D ARM_CP_NOP, .access =3D PL1_W }, + .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D aa64_cacheop_= poc_access }, { .name =3D "DCCISW", .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 14= , .opc2 =3D 2, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, /* MMU Domain access control / MPU write buffer control */ @@ -6728,7 +6751,7 @@ static const ARMCPRegInfo dcpop_reg[] =3D { { .name =3D "DC_CVAP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, - .accessfn =3D aa64_cacheop_access, .writefn =3D dccvap_writefn }, + .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, REGINFO_SENTINEL }; =20 @@ -6736,7 +6759,7 @@ static const ARMCPRegInfo dcpodp_reg[] =3D { { .name =3D "DC_CVADP", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, - .accessfn =3D aa64_cacheop_access, .writefn =3D dccvap_writefn }, + .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, REGINFO_SENTINEL }; #endif /*CONFIG_USER_ONLY*/ --=20 2.20.1