From nobody Fri Dec 19 17:18:51 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (BodyHash is different from the expected one) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582638214626346.097142376997; Tue, 25 Feb 2020 05:43:34 -0800 (PST) Received: from localhost ([::1]:56274 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6aUn-0006wG-EG for importer@patchew.org; Tue, 25 Feb 2020 08:43:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37509) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6a2r-00089D-Vu for qemu-devel@nongnu.org; Tue, 25 Feb 2020 08:14:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j6a2q-0002A8-Co for qemu-devel@nongnu.org; Tue, 25 Feb 2020 08:14:41 -0500 Received: from beetle.greensocs.com ([5.135.226.135]:57274) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j6a2m-00023D-MW; Tue, 25 Feb 2020 08:14:37 -0500 Received: from crumble.bar.greensocs.com (crumble.bar.greensocs.com [172.16.11.102]) by beetle.greensocs.com (Postfix) with ESMTPS id 43BAC96F57; Tue, 25 Feb 2020 13:14:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1582636470; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dRPQZ/ZK2BoNEjn5Iae8tGrhXrd6S6a/K4s/XgUw0a8=; b=wqG+5fnL1CDhHpdZN5to1M66ss5nJJ9V4wq4RxrjVx/S9HHh81Om+Oe5Gq8WPoAVYCM2k5 Trw7jW4VH42IHKDq3QJabQdn3IaqBaWJeqNqpsK4KbuUb5dePsGLIgvyNRZulbaNu83fK/ urCVCEzOVNxtuDR4thVLJ+lC01rcud4= From: Damien Hedde To: qemu-devel@nongnu.org Subject: [PATCH v8 8/9] hw/arm/xilinx_zynq: connect uart clocks to slcr Date: Tue, 25 Feb 2020 14:14:21 +0100 Message-Id: <20200225131422.53368-9-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200225131422.53368-1-damien.hedde@greensocs.com> References: <20200225131422.53368-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1582636470; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dRPQZ/ZK2BoNEjn5Iae8tGrhXrd6S6a/K4s/XgUw0a8=; b=OcOMTevjEHmyYNLPDIvP6YIRGVwyhBGr2Q0iel9AoeIMk0uzLQeeUZum3VPHSJvk5nDqdX Tz6orngak2UX0gLKg53iDI3oLxH7twY2iHepw4XyrIGEBtQre55FpmgzlwVpLlKPMCsAxM uUjqhqvn8vDPS7lA5pxfePLKXJxvRzA= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1582636470; a=rsa-sha256; cv=none; b=1AkDBRjC572VUiL2K8brXzrsjisEpxxmlrSdb2+S5wyCnP72IQl27CMj25rHkIW/xk755n zntEOenRCoMixKgR+rqDAj6qi9WAeJmTOsoaNQRA8gamxdfvkwkVm9wJ+9jymQxBaQ2w/v sodxYGdg+EbkSlBc8g4mjDxWKVoK/qQ= ARC-Authentication-Results: i=1; beetle.greensocs.com; none X-Spam: Yes Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 5.135.226.135 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , peter.maydell@linaro.org, berrange@redhat.com, ehabkost@redhat.com, pbonzini@redhat.com, alistair@alistair23.me, mark.burton@greensocs.com, qemu-arm@nongnu.org, marcandre.lureau@redhat.com, edgar.iglesias@gmail.com, philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add the connection between the slcr's output clocks and the uarts inputs. Also add the main board clock 'ps_clk', which is hard-coded to 33.33MHz (the default frequency). This clock is used to feed the slcr's input clock. Signed-off-by: Damien Hedde Reviewed-by: Alistair Francis --- v7 + update ClockIn/ClockOut types + simplify the ps_clk frequency init --- hw/arm/xilinx_zynq.c | 57 +++++++++++++++++++++++++++++++++++++------- 1 file changed, 49 insertions(+), 8 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 3a0fa5b23f..261a1690a8 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -34,6 +34,15 @@ #include "hw/char/cadence_uart.h" #include "hw/net/cadence_gem.h" #include "hw/cpu/a9mpcore.h" +#include "hw/qdev-clock.h" +#include "sysemu/reset.h" + +#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") +#define ZYNQ_MACHINE(obj) \ + OBJECT_CHECK(ZynqMachineState, (obj), TYPE_ZYNQ_MACHINE) + +/* board base frequency: 33.333333 MHz */ +#define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3) =20 #define NUM_SPI_FLASHES 4 #define NUM_QSPI_FLASHES 2 @@ -74,6 +83,11 @@ static const int dma_irqs[8] =3D { 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \ 0xe5801000 + (addr) =20 +typedef struct ZynqMachineState { + MachineState parent; + Clock *ps_clk; +} ZynqMachineState; + static void zynq_write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) { @@ -158,12 +172,13 @@ static inline void zynq_init_spi_flashes(uint32_t bas= e_addr, qemu_irq irq, =20 static void zynq_init(MachineState *machine) { + ZynqMachineState *zynq_machine =3D ZYNQ_MACHINE(machine); ram_addr_t ram_size =3D machine->ram_size; ARMCPU *cpu; MemoryRegion *address_space_mem =3D get_system_memory(); MemoryRegion *ext_ram =3D g_new(MemoryRegion, 1); MemoryRegion *ocm_ram =3D g_new(MemoryRegion, 1); - DeviceState *dev; + DeviceState *dev, *slcr; SysBusDevice *busdev; qemu_irq pic[64]; int n; @@ -208,9 +223,18 @@ static void zynq_init(MachineState *machine) 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, 0); =20 - dev =3D qdev_create(NULL, "xilinx,zynq_slcr"); - qdev_init_nofail(dev); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000); + /* Create slcr, keep a pointer to connect clocks */ + slcr =3D qdev_create(NULL, "xilinx,zynq_slcr"); + qdev_init_nofail(slcr); + sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); + + /* Create the main clock source, and feed slcr with it */ + zynq_machine->ps_clk =3D CLOCK(object_new(TYPE_CLOCK)); + object_property_add_child(OBJECT(zynq_machine), "ps_clk", + OBJECT(zynq_machine->ps_clk), &error_abort); + object_unref(OBJECT(zynq_machine->ps_clk)); + clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY); + qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk); =20 dev =3D qdev_create(NULL, TYPE_A9MPCORE_PRIV); qdev_prop_set_uint32(dev, "num-cpu", 1); @@ -231,8 +255,12 @@ static void zynq_init(MachineState *machine) sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]); sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[76-IRQ_OFFSET]); =20 - cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0)); - cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1)); + dev =3D cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_h= d(0)); + qdev_connect_clock_in(dev, "refclk", + qdev_get_clock_out(slcr, "uart0_ref_clk")); + dev =3D cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_h= d(1)); + qdev_connect_clock_in(dev, "refclk", + qdev_get_clock_out(slcr, "uart1_ref_clk")); =20 sysbus_create_varargs("cadence_ttc", 0xF8001000, pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NU= LL); @@ -310,8 +338,9 @@ static void zynq_init(MachineState *machine) arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo); } =20 -static void zynq_machine_init(MachineClass *mc) +static void zynq_machine_class_init(ObjectClass *oc, void *data) { + MachineClass *mc =3D MACHINE_CLASS(oc); mc->desc =3D "Xilinx Zynq Platform Baseboard for Cortex-A9"; mc->init =3D zynq_init; mc->max_cpus =3D 1; @@ -320,4 +349,16 @@ static void zynq_machine_init(MachineClass *mc) mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a9"); } =20 -DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init) +static const TypeInfo zynq_machine_type =3D { + .name =3D TYPE_ZYNQ_MACHINE, + .parent =3D TYPE_MACHINE, + .class_init =3D zynq_machine_class_init, + .instance_size =3D sizeof(ZynqMachineState), +}; + +static void zynq_machine_register_types(void) +{ + type_register_static(&zynq_machine_type); +} + +type_init(zynq_machine_register_types) --=20 2.25.1