From nobody Thu Nov 13 16:18:20 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1582626989; cv=none; d=zohomail.com; s=zohoarc; b=khefaPMpOdjlqNJN4FEwDA3TLA+03e61+Ii5NR5xNoZmAjMmkASGCAymSXIzk48HZ09/nDlCe8WX07nr5pwhGtUYLGyV8S0y//uG+g8p0C45W/G7SK0WRc7qx9sR94c31nbiOHtPS2rcyyD7Wnni78itKSef/csOPTzhlZR+ScE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582626989; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RrfAp9btfQWXRXMAtz4AsvepEB+RzKg+KwPKJ3KK8XM=; b=g6T086wNS+bmPk57yR6xhD1FEBjJ5Vy4EYUFmrFzAT1kIDphJj9zNMMZQwhs/kUvkQwmg4JzXgdU+zP/Wi6ggxY4zqaM8JslbbPn3mNMFhw4tXz/PGL8WPJBUZd8m9P9FZtsfkcaDcYuuY1wsowwynMHpC7bT1c3oIS3CVjMBjQ= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582626989829431.39793620098; Tue, 25 Feb 2020 02:36:29 -0800 (PST) Received: from localhost ([::1]:52212 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6XZk-00032T-I8 for importer@patchew.org; Tue, 25 Feb 2020 05:36:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:35269) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6XYh-0001Ak-Ew for qemu-devel@nongnu.org; Tue, 25 Feb 2020 05:35:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j6XYd-0001PX-SY for qemu-devel@nongnu.org; Tue, 25 Feb 2020 05:35:23 -0500 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:46025) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j6XYd-0001O1-8t; Tue, 25 Feb 2020 05:35:19 -0500 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.GsFPuQz_1582626910) by smtp.aliyun-inc.com(10.147.40.44); Tue, 25 Feb 2020 18:35:13 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.65445-0.0401631-0.305387; DS=CONTINUE|ham_system_inform|0.686825-0.000258514-0.312917; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03308; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.GsFPuQz_1582626910; From: LIU Zhiwei To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Subject: [PATCH v4 4/5] target/riscv: add fault-only-first unit stride load Date: Tue, 25 Feb 2020 18:35:07 +0800 Message-Id: <20200225103508.7651-5-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200225103508.7651-1-zhiwei_liu@c-sky.com> References: <20200225103508.7651-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, qemu-devel@nongnu.org, linux-csky@vger.kernel.org, wenmeng_zhang@c-sky.com, wxy194768@alibaba-inc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The unit-stride fault-only-fault load instructions are used to vectorize loops with data-dependent exit conditions(while loops). These instructions execute as a regular load except that they will only take a trap on element 0. Signed-off-by: LIU Zhiwei --- target/riscv/helper.h | 22 ++++ target/riscv/insn32.decode | 7 ++ target/riscv/insn_trans/trans_rvv.inc.c | 66 ++++++++++++ target/riscv/vector_helper.c | 136 ++++++++++++++++++++++++ 4 files changed, 231 insertions(+) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index f9b3da60ca..72ba4d9bdb 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -218,3 +218,25 @@ DEF_HELPER_6(vsxe_v_b, void, ptr, ptr, tl, ptr, env, i= 32) DEF_HELPER_6(vsxe_v_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsxe_v_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vsxe_v_d, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_5(vlbff_v_b, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlbff_v_h, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlbff_v_w, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlbff_v_d, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlhff_v_h, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlhff_v_w, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlhff_v_d, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlwff_v_w, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlwff_v_d, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vleff_v_b, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vleff_v_h, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vleff_v_w, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vleff_v_d, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlbuff_v_b, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlbuff_v_h, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlbuff_v_w, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlbuff_v_d, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlhuff_v_h, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlhuff_v_w, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlhuff_v_d, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlwuff_v_w, void, ptr, ptr, tl, env, i32) +DEF_HELPER_5(vlwuff_v_d, void, ptr, ptr, tl, env, i32) diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode index 6a363a6b7e..973ac63fda 100644 --- a/target/riscv/insn32.decode +++ b/target/riscv/insn32.decode @@ -219,6 +219,13 @@ vle_v ... 000 . 00000 ..... 111 ..... 0000111 @r2= _nfvm vlbu_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm vlhu_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm vlwu_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm +vlbff_v ... 100 . 10000 ..... 000 ..... 0000111 @r2_nfvm +vlhff_v ... 100 . 10000 ..... 101 ..... 0000111 @r2_nfvm +vlwff_v ... 100 . 10000 ..... 110 ..... 0000111 @r2_nfvm +vleff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm +vlbuff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm +vlhuff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm +vlwuff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm vsb_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm vsh_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm vsw_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_tr= ans/trans_rvv.inc.c index c0d560d789..dda3ba555c 100644 --- a/target/riscv/insn_trans/trans_rvv.inc.c +++ b/target/riscv/insn_trans/trans_rvv.inc.c @@ -510,3 +510,69 @@ static bool trans_vsuxe_v(DisasContext *s, arg_rnfvm* = a) { return trans_vsxe_v(s, a); } + +/* + *** unit stride fault-only-first load + */ +static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data, + gen_helper_ldst_us *fn, DisasContext *s) +{ + TCGv_ptr dest, mask; + TCGv base; + TCGv_i32 desc; + + dest =3D tcg_temp_new_ptr(); + mask =3D tcg_temp_new_ptr(); + base =3D tcg_temp_new(); + desc =3D tcg_const_i32(simd_desc(0, s->vlen / 8, data)); + + gen_get_gpr(base, rs1); + tcg_gen_addi_ptr(dest, cpu_env, vreg_ofs(s, vd)); + tcg_gen_addi_ptr(mask, cpu_env, vreg_ofs(s, 0)); + + fn(dest, mask, base, cpu_env, desc); + + tcg_temp_free_ptr(dest); + tcg_temp_free_ptr(mask); + tcg_temp_free(base); + tcg_temp_free_i32(desc); + return true; +} + +static bool ldff_op(DisasContext *s, arg_r2nfvm *a, uint8_t seq) +{ + uint8_t nf =3D a->nf + 1; + uint32_t data =3D s->mlen | (a->vm << 8) | (s->lmul << 9) | (nf << 11); + gen_helper_ldst_us *fn; + static gen_helper_ldst_us * const fns[7][4] =3D { + { gen_helper_vlbff_v_b, gen_helper_vlbff_v_h, + gen_helper_vlbff_v_w, gen_helper_vlbff_v_d }, + { NULL, gen_helper_vlhff_v_h, + gen_helper_vlhff_v_w, gen_helper_vlhff_v_d }, + { NULL, NULL, + gen_helper_vlwff_v_w, gen_helper_vlwff_v_d }, + { gen_helper_vleff_v_b, gen_helper_vleff_v_h, + gen_helper_vleff_v_w, gen_helper_vleff_v_d }, + { gen_helper_vlbuff_v_b, gen_helper_vlbuff_v_h, + gen_helper_vlbuff_v_w, gen_helper_vlbuff_v_d }, + { NULL, gen_helper_vlhuff_v_h, + gen_helper_vlhuff_v_w, gen_helper_vlhuff_v_d }, + { NULL, NULL, + gen_helper_vlwuff_v_w, gen_helper_vlwuff_v_d } + }; + + fn =3D fns[seq][s->sew]; + if (fn =3D=3D NULL) { + return false; + } + + return ldff_trans(a->rd, a->rs1, data, fn, s); +} + +GEN_VEXT_TRANS(vlbff_v, 0, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vlhff_v, 1, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vlwff_v, 2, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vleff_v, 3, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vlbuff_v, 4, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vlhuff_v, 5, r2nfvm, ldff_op, ld_us_check) +GEN_VEXT_TRANS(vlwuff_v, 6, r2nfvm, ldff_op, ld_us_check) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 908f48e216..6772e31ecb 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -277,6 +277,28 @@ GEN_VEXT_LD_ELEM(vlxhu_v_w, uint16_t, uint32_t, H4, ld= uw) GEN_VEXT_LD_ELEM(vlxhu_v_d, uint16_t, uint64_t, H8, lduw) GEN_VEXT_LD_ELEM(vlxwu_v_w, uint32_t, uint32_t, H4, ldl) GEN_VEXT_LD_ELEM(vlxwu_v_d, uint32_t, uint64_t, H8, ldl) +GEN_VEXT_LD_ELEM(vlbff_v_b, int8_t, int8_t, H1, ldsb) +GEN_VEXT_LD_ELEM(vlbff_v_h, int8_t, int16_t, H2, ldsb) +GEN_VEXT_LD_ELEM(vlbff_v_w, int8_t, int32_t, H4, ldsb) +GEN_VEXT_LD_ELEM(vlbff_v_d, int8_t, int64_t, H8, ldsb) +GEN_VEXT_LD_ELEM(vlhff_v_h, int16_t, int16_t, H2, ldsw) +GEN_VEXT_LD_ELEM(vlhff_v_w, int16_t, int32_t, H4, ldsw) +GEN_VEXT_LD_ELEM(vlhff_v_d, int16_t, int64_t, H8, ldsw) +GEN_VEXT_LD_ELEM(vlwff_v_w, int32_t, int32_t, H4, ldl) +GEN_VEXT_LD_ELEM(vlwff_v_d, int32_t, int64_t, H8, ldl) +GEN_VEXT_LD_ELEM(vleff_v_b, int8_t, int8_t, H1, ldsb) +GEN_VEXT_LD_ELEM(vleff_v_h, int16_t, int16_t, H2, ldsw) +GEN_VEXT_LD_ELEM(vleff_v_w, int32_t, int32_t, H4, ldl) +GEN_VEXT_LD_ELEM(vleff_v_d, int64_t, int64_t, H8, ldq) +GEN_VEXT_LD_ELEM(vlbuff_v_b, uint8_t, uint8_t, H1, ldub) +GEN_VEXT_LD_ELEM(vlbuff_v_h, uint8_t, uint16_t, H2, ldub) +GEN_VEXT_LD_ELEM(vlbuff_v_w, uint8_t, uint32_t, H4, ldub) +GEN_VEXT_LD_ELEM(vlbuff_v_d, uint8_t, uint64_t, H8, ldub) +GEN_VEXT_LD_ELEM(vlhuff_v_h, uint16_t, uint16_t, H2, lduw) +GEN_VEXT_LD_ELEM(vlhuff_v_w, uint16_t, uint32_t, H4, lduw) +GEN_VEXT_LD_ELEM(vlhuff_v_d, uint16_t, uint64_t, H8, lduw) +GEN_VEXT_LD_ELEM(vlwuff_v_w, uint32_t, uint32_t, H4, ldl) +GEN_VEXT_LD_ELEM(vlwuff_v_d, uint32_t, uint64_t, H8, ldl) =20 #define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF) \ static void vext_##NAME##_st_elem(CPURISCVState *env, abi_ptr addr, \ @@ -840,3 +862,117 @@ GEN_VEXT_ST_INDEX(vsxe_v_b, int8_t, int8_t) GEN_VEXT_ST_INDEX(vsxe_v_h, int16_t, int16_t) GEN_VEXT_ST_INDEX(vsxe_v_w, int32_t, int32_t) GEN_VEXT_ST_INDEX(vsxe_v_d, int64_t, int64_t) + +/* + *** unit-stride fault-only-fisrt load instructions + */ +static inline void vext_ldff(void *vd, void *v0, target_ulong base, + CPURISCVState *env, uint32_t desc, + vext_ld_elem_fn ld_elem, + vext_ld_clear_elem clear_elem, + int mmuidx, uint32_t esz, uint32_t msz, uintptr_t ra) +{ + void *host; + uint32_t i, k, vl =3D 0; + uint32_t mlen =3D vext_mlen(desc); + uint32_t nf =3D vext_nf(desc); + uint32_t vm =3D vext_vm(desc); + uint32_t vlmax =3D vext_maxsz(desc) / esz; + target_ulong addr, offset, remain; + + if (env->vl =3D=3D 0) { + return; + } + /* probe every access*/ + for (i =3D 0; i < env->vl; i++) { + if (!vm && !vext_elem_mask(v0, mlen, i)) { + continue; + } + addr =3D base + nf * i * msz; + if (i =3D=3D 0) { + probe_read_access(env, addr, nf * msz, ra); + } else { + /* if it triggles an exception, no need to check watchpoint */ + offset =3D -(addr | TARGET_PAGE_MASK); + remain =3D nf * msz; + while (remain > 0) { + host =3D tlb_vaddr_to_host(env, addr, MMU_DATA_LOAD, mmuid= x); + if (host) { +#ifdef CONFIG_USER_ONLY + if (page_check_range(addr, nf * msz, PAGE_READ) < 0) { + vl =3D i; + goto ProbeSuccess; + } +#else + probe_read_access(env, addr, nf * msz, ra); +#endif + } else { + vl =3D i; + goto ProbeSuccess; + } + if (remain <=3D offset) { + break; + } + remain -=3D offset; + addr +=3D offset; + offset =3D -(addr | TARGET_PAGE_MASK); + } + } + } +ProbeSuccess: + /* load bytes from guest memory */ + if (vl !=3D 0) { + env->vl =3D vl; + } + for (i =3D 0; i < env->vl; i++) { + k =3D 0; + if (!vm && !vext_elem_mask(v0, mlen, i)) { + continue; + } + while (k < nf) { + target_ulong addr =3D base + (i * nf + k) * msz; + ld_elem(env, addr, i + k * vlmax, vd, ra); + k++; + } + } + /* clear tail elements */ + if (vl !=3D 0) { + return; + } + for (k =3D 0; k < nf; k++) { + clear_elem(vd, env->vl + k * vlmax, env->vl * esz, vlmax * esz); + } +} + +#define GEN_VEXT_LDFF(NAME, MTYPE, ETYPE, MMUIDX) \ +void HELPER(NAME)(void *vd, void *v0, target_ulong base, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + vext_ldff(vd, v0, base, env, desc, \ + vext_##NAME##_ld_elem, \ + vext_##NAME##_clear_elem, \ + MMUIDX, sizeof(ETYPE), sizeof(MTYPE), GETPC()); \ +} + +GEN_VEXT_LDFF(vlbff_v_b, int8_t, int8_t, MO_SB) +GEN_VEXT_LDFF(vlbff_v_h, int8_t, int16_t, MO_SB) +GEN_VEXT_LDFF(vlbff_v_w, int8_t, int32_t, MO_SB) +GEN_VEXT_LDFF(vlbff_v_d, int8_t, int64_t, MO_SB) +GEN_VEXT_LDFF(vlhff_v_h, int16_t, int16_t, MO_LESW) +GEN_VEXT_LDFF(vlhff_v_w, int16_t, int32_t, MO_LESW) +GEN_VEXT_LDFF(vlhff_v_d, int16_t, int64_t, MO_LESW) +GEN_VEXT_LDFF(vlwff_v_w, int32_t, int32_t, MO_LESL) +GEN_VEXT_LDFF(vlwff_v_d, int32_t, int64_t, MO_LESL) +GEN_VEXT_LDFF(vleff_v_b, int8_t, int8_t, MO_SB) +GEN_VEXT_LDFF(vleff_v_h, int16_t, int16_t, MO_LESW) +GEN_VEXT_LDFF(vleff_v_w, int32_t, int32_t, MO_LESL) +GEN_VEXT_LDFF(vleff_v_d, int64_t, int64_t, MO_LEQ) +GEN_VEXT_LDFF(vlbuff_v_b, uint8_t, uint8_t, MO_UB) +GEN_VEXT_LDFF(vlbuff_v_h, uint8_t, uint16_t, MO_UB) +GEN_VEXT_LDFF(vlbuff_v_w, uint8_t, uint32_t, MO_UB) +GEN_VEXT_LDFF(vlbuff_v_d, uint8_t, uint64_t, MO_UB) +GEN_VEXT_LDFF(vlhuff_v_h, uint16_t, uint16_t, MO_LEUW) +GEN_VEXT_LDFF(vlhuff_v_w, uint16_t, uint32_t, MO_LEUW) +GEN_VEXT_LDFF(vlhuff_v_d, uint16_t, uint64_t, MO_LEUW) +GEN_VEXT_LDFF(vlwuff_v_w, uint32_t, uint32_t, MO_LEUL) +GEN_VEXT_LDFF(vlwuff_v_d, uint32_t, uint64_t, MO_LEUL) --=20 2.23.0