From nobody Mon Feb 9 11:07:18 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1582595607; cv=none; d=zohomail.com; s=zohoarc; b=R7onUFDlcOmkYDpHWh4XvrgwZ/nTdwGzNBFc7N+hDA8S/yhTiODJ/SKMWFqiUs07eHcYWqZw8mDrzdzUFUiJomAjNX4K9EeA7mkQdL64AehfnjNQLzIr+WfrUiUam3o7Q/NG6Qq6bB/YDCKlfIWvarUNwBzFYZ3VgaDTG9357cc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582595607; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gVBAmphUfjHqk/sLk9dg2yfUzw9JUXuveR79mHjQ/dU=; b=QNgNbLmXkOrimcnGdANYnFbee0XnWYtizdo17LmPqVifCxe5HkX63FyIeP2nlm0HWX0jy4bsdoGH/uz26Sm3CalbJ2Ote22ObffGoxqBXr8TSt0gKglz9y4nJpcUXpzKEXNe3OxvGiygzYHx+/e87DeG3LRT/3y7ynQHF2BkxEE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582595607270841.6702260169229; Mon, 24 Feb 2020 17:53:27 -0800 (PST) Received: from localhost ([::1]:47450 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6PPa-0001yB-2n for importer@patchew.org; Mon, 24 Feb 2020 20:53:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34885) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6PO4-0000SW-Kk for qemu-devel@nongnu.org; Mon, 24 Feb 2020 20:51:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j6PNz-0002ft-5t for qemu-devel@nongnu.org; Mon, 24 Feb 2020 20:51:51 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2729 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j6PNx-0002dU-BX for qemu-devel@nongnu.org; Mon, 24 Feb 2020 20:51:46 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 43FEFD928091389C0C37; Tue, 25 Feb 2020 09:50:52 +0800 (CST) Received: from DESKTOP-D7EVK5B.china.huawei.com (10.173.221.29) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.439.0; Tue, 25 Feb 2020 09:50:44 +0800 From: Yubo Miao To: , Subject: [PATCH v4 1/3] acpi:Extract two APIs from acpi_dsdt_add_pci Date: Tue, 25 Feb 2020 09:50:24 +0800 Message-ID: <20200225015026.940-2-miaoyubo@huawei.com> X-Mailer: git-send-email 2.24.1.windows.2 In-Reply-To: <20200225015026.940-1-miaoyubo@huawei.com> References: <20200225015026.940-1-miaoyubo@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.173.221.29] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.190 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: berrange@redhat.com, mst@redhat.com, qemu-devel@nongnu.org, xiexiangyou@huawei.com, miaoyubo@huawei.com, imammedo@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: miaoyubo Extract two APIs acpi_dsdt_add_pci_route_table and acpi_dsdt_add_pci_osc form acpi_dsdt_add_pci. The first API is used to specify the pci route table and the second API is used to declare the operation system capabilities. These two APIs would be used to specify the pxb-pcie in DSDT. Signed-off-by: miaoyubo --- hw/arm/virt-acpi-build.c | 129 ++++++++++++++++++++++----------------- 1 file changed, 72 insertions(+), 57 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index fb4b166f82..37c34748a6 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -146,29 +146,11 @@ static void acpi_dsdt_add_virtio(Aml *scope, } } =20 -static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, - uint32_t irq, bool use_highmem, bool highmem= _ecam) +static void acpi_dsdt_add_pci_route_table(Aml *dev, Aml *scope, + uint32_t irq) { - int ecam_id =3D VIRT_ECAM_ID(highmem_ecam); - Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; int i, slot_no; - hwaddr base_mmio =3D memmap[VIRT_PCIE_MMIO].base; - hwaddr size_mmio =3D memmap[VIRT_PCIE_MMIO].size; - hwaddr base_pio =3D memmap[VIRT_PCIE_PIO].base; - hwaddr size_pio =3D memmap[VIRT_PCIE_PIO].size; - hwaddr base_ecam =3D memmap[ecam_id].base; - hwaddr size_ecam =3D memmap[ecam_id].size; - int nr_pcie_buses =3D size_ecam / PCIE_MMCFG_SIZE_MIN; - - Aml *dev =3D aml_device("%s", "PCI0"); - aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); - aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); - aml_append(dev, aml_name_decl("_SEG", aml_int(0))); - aml_append(dev, aml_name_decl("_BBN", aml_int(0))); - aml_append(dev, aml_name_decl("_UID", aml_string("PCI0"))); - aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); - aml_append(dev, aml_name_decl("_CCA", aml_int(1))); - + Aml *method, *crs; /* Declare the PCI Routing Table. */ Aml *rt_pkg =3D aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS); for (slot_no =3D 0; slot_no < PCI_SLOT_MAX; slot_no++) { @@ -204,41 +186,11 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMa= pEntry *memmap, aml_append(dev_gsi, method); aml_append(dev, dev_gsi); } +} =20 - method =3D aml_method("_CBA", 0, AML_NOTSERIALIZED); - aml_append(method, aml_return(aml_int(base_ecam))); - aml_append(dev, method); - - method =3D aml_method("_CRS", 0, AML_NOTSERIALIZED); - Aml *rbuf =3D aml_resource_template(); - aml_append(rbuf, - aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, - 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, - nr_pcie_buses)); - aml_append(rbuf, - aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_m= mio, - base_mmio + size_mmio - 1, 0x0000, size_mmio)); - aml_append(rbuf, - aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, - AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_= pio, - size_pio)); - - if (use_highmem) { - hwaddr base_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].base; - hwaddr size_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].size; - - aml_append(rbuf, - aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, - base_mmio_high, - base_mmio_high + size_mmio_high - 1, 0x0000, - size_mmio_high)); - } - - aml_append(method, aml_return(rbuf)); - aml_append(dev, method); - +static void acpi_dsdt_add_pci_osc(Aml *dev, Aml *scope) +{ + Aml *method, *UUID, *ifctx, *ifctx1, *elsectx, *buf; /* Declare an _OSC (OS Control Handoff) method */ aml_append(dev, aml_name_decl("SUPP", aml_int(0))); aml_append(dev, aml_name_decl("CTRL", aml_int(0))); @@ -246,7 +198,8 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapE= ntry *memmap, aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); =20 - /* PCI Firmware Specification 3.0 + /* + * PCI Firmware Specification 3.0 * 4.5.1. _OSC Interface for PCI Host Bridge Devices * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is * identified by the Universal Unique IDentifier (UUID) @@ -291,7 +244,8 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapE= ntry *memmap, =20 method =3D aml_method("_DSM", 4, AML_NOTSERIALIZED); =20 - /* PCI Firmware Specification 3.0 + /* + * PCI Firmware Specification 3.0 * 4.6.1. _DSM for PCI Express Slot Information * The UUID in _DSM in this context is * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} @@ -309,6 +263,67 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMap= Entry *memmap, buf =3D aml_buffer(1, byte_list); aml_append(method, aml_return(buf)); aml_append(dev, method); +} + +static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, + uint32_t irq, bool use_highmem, bool highmem= _ecam) +{ + int ecam_id =3D VIRT_ECAM_ID(highmem_ecam); + Aml *method, *crs; + hwaddr base_mmio =3D memmap[VIRT_PCIE_MMIO].base; + hwaddr size_mmio =3D memmap[VIRT_PCIE_MMIO].size; + hwaddr base_pio =3D memmap[VIRT_PCIE_PIO].base; + hwaddr size_pio =3D memmap[VIRT_PCIE_PIO].size; + hwaddr base_ecam =3D memmap[ecam_id].base; + hwaddr size_ecam =3D memmap[ecam_id].size; + int nr_pcie_buses =3D size_ecam / PCIE_MMCFG_SIZE_MIN; + + Aml *dev =3D aml_device("%s", "PCI0"); + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); + aml_append(dev, aml_name_decl("_SEG", aml_int(0))); + aml_append(dev, aml_name_decl("_BBN", aml_int(0))); + aml_append(dev, aml_name_decl("_UID", aml_string("PCI0"))); + aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); + + acpi_dsdt_add_pci_route_table(dev, scope, irq); + + method =3D aml_method("_CBA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(base_ecam))); + aml_append(dev, method); + + method =3D aml_method("_CRS", 0, AML_NOTSERIALIZED); + Aml *rbuf =3D aml_resource_template(); + aml_append(rbuf, + aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, + 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, + nr_pcie_buses)); + aml_append(rbuf, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_m= mio, + base_mmio + size_mmio - 1, 0x0000, size_mmio)); + aml_append(rbuf, + aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, + AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_= pio, + size_pio)); + + if (use_highmem) { + hwaddr base_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].base; + hwaddr size_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].size; + + aml_append(rbuf, + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, + base_mmio_high, + base_mmio_high + size_mmio_high - 1, 0x0000, + size_mmio_high)); + } + + aml_append(method, aml_return(rbuf)); + aml_append(dev, method); + + acpi_dsdt_add_pci_osc(dev, scope); =20 Aml *dev_res0 =3D aml_device("%s", "RES0"); aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); --=20 2.19.1 From nobody Mon Feb 9 11:07:18 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1582595583; cv=none; d=zohomail.com; s=zohoarc; b=HOjU9ua8HjlAhauaGucTBq2FOmXu6a0I5vqOAVZiqdRPqjc/xWGBTxMbUZnteoYn4fh77EHDW2tMw3FlcosA3C/tyRA1CLOmkz19cALAlq1bQUBQq9MLTjui03WlApNamhSf7baBf7sd7976uuSBbtx77vcpTyrDycFrXrgeuXk= ARC-Message-Signature: i=1; a=rsa-sha256; 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Mon, 24 Feb 2020 20:53:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34884) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6PO4-0000SV-KU for qemu-devel@nongnu.org; Mon, 24 Feb 2020 20:51:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j6PNz-0002fo-5j for qemu-devel@nongnu.org; Mon, 24 Feb 2020 20:51:51 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:3165 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j6PNx-0002dh-Eo for qemu-devel@nongnu.org; Mon, 24 Feb 2020 20:51:46 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 37728DD0AF38BF9D0A9C; Tue, 25 Feb 2020 09:50:52 +0800 (CST) Received: from DESKTOP-D7EVK5B.china.huawei.com (10.173.221.29) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.439.0; Tue, 25 Feb 2020 09:50:45 +0800 From: Yubo Miao To: , Subject: [PATCH v4 2/3] acpi:pci-expender-bus: Add pxb support for arm Date: Tue, 25 Feb 2020 09:50:25 +0800 Message-ID: <20200225015026.940-3-miaoyubo@huawei.com> X-Mailer: git-send-email 2.24.1.windows.2 In-Reply-To: <20200225015026.940-1-miaoyubo@huawei.com> References: <20200225015026.940-1-miaoyubo@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.173.221.29] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.190 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: berrange@redhat.com, mst@redhat.com, qemu-devel@nongnu.org, xiexiangyou@huawei.com, miaoyubo@huawei.com, imammedo@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: miaoyubo Currently virt machine is not supported by pxb-pcie, and only one main host bridge described in ACPI tables. In this patch,PXB-PCIE is supproted by arm and certain resource is allocated for each pxb-pcie in acpi table. The resource for the main host bridge is also reallocated. Signed-off-by: miaoyubo --- hw/arm/virt-acpi-build.c | 115 ++++++++++++++++++++++++++++++++++++--- hw/arm/virt.c | 3 + include/hw/arm/virt.h | 7 +++ 3 files changed, 118 insertions(+), 7 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 37c34748a6..be1986c60d 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -49,6 +49,8 @@ #include "kvm_arm.h" #include "migration/vmstate.h" =20 +#include "hw/arm/virt.h" +#include "hw/pci/pci_bus.h" #define ARM_SPI_BASE 32 =20 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) @@ -266,19 +268,116 @@ static void acpi_dsdt_add_pci_osc(Aml *dev, Aml *sco= pe) } =20 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, - uint32_t irq, bool use_highmem, bool highmem= _ecam) + uint32_t irq, bool use_highmem, bool highmem= _ecam, + VirtMachineState *vms) { int ecam_id =3D VIRT_ECAM_ID(highmem_ecam); - Aml *method, *crs; + Aml *method, *crs, *dev; + int count =3D 0; hwaddr base_mmio =3D memmap[VIRT_PCIE_MMIO].base; hwaddr size_mmio =3D memmap[VIRT_PCIE_MMIO].size; hwaddr base_pio =3D memmap[VIRT_PCIE_PIO].base; hwaddr size_pio =3D memmap[VIRT_PCIE_PIO].size; hwaddr base_ecam =3D memmap[ecam_id].base; hwaddr size_ecam =3D memmap[ecam_id].size; + /* + * 0x600000 would be enough for pxb device + * if it is too small, there is no enough space + * for a pcie device plugged in a pcie-root port + */ + hwaddr size_addr =3D 0x600000; + hwaddr size_io =3D 0x4000; int nr_pcie_buses =3D size_ecam / PCIE_MMCFG_SIZE_MIN; + PCIBus *bus =3D VIRT_MACHINE(vms)->bus; + + if (bus) { + QLIST_FOREACH(bus, &bus->child, sibling) { + uint8_t bus_num =3D pci_bus_num(bus); + uint8_t numa_node =3D pci_bus_numa_node(bus); + + if (!pci_bus_is_root(bus)) { + continue; + } + /* + * Coded up the MIN of the busNr defined for pxb-pcie, + * the MIN - 1 would be the MAX bus number for the main + * host bridge. + */ + if (bus_num < nr_pcie_buses) { + nr_pcie_buses =3D bus_num; + } + count++; + dev =3D aml_device("PC%.02X", bus_num); + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); + aml_append(dev, aml_name_decl("_ADR", aml_int(0))); + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); + aml_append(dev, aml_name_decl("_SEG", aml_int(0))); + aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); + aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); + aml_append(dev, aml_name_decl("_STR", aml_unicode("pxb Device"= ))); + if (numa_node !=3D NUMA_NODE_UNASSIGNED) { + method =3D aml_method("_PXM", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(numa_node))); + aml_append(dev, method); + } + + acpi_dsdt_add_pci_route_table(dev, scope, irq); + + method =3D aml_method("_CBA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(base_ecam))); + aml_append(dev, method); + + method =3D aml_method("_CRS", 0, AML_NOTSERIALIZED); + Aml *rbuf =3D aml_resource_template(); + aml_append(rbuf, + aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, + AML_POS_DECODE, 0x0000, + bus_num, bus_num + 1, 0x0000, + 2)); + aml_append(rbuf, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, + AML_MAX_FIXED, AML_NON_CACHEABLE, + AML_READ_WRITE, 0x0000, + base_mmio + size_mmio - + size_addr * count, + base_mmio + size_mmio - 1 - + size_addr * (count - 1), + 0x0000, size_addr)); + aml_append(rbuf, + aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, + AML_POS_DECODE, AML_ENTIRE_RANGE, + 0x0000, size_pio - size_io * count, + size_pio - 1 - size_io * (count - 1), + base_pio, size_io)); + + if (use_highmem) { + hwaddr base_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].base; + hwaddr size_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].size; + + aml_append(rbuf, + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, + AML_MAX_FIXED, AML_NON_CACHEABLE, + AML_READ_WRITE, 0x0000, + base_mmio_high + size_mmio_high - + size_addr * count, + base_mmio_high + size_mmio_high - + 1 - size_addr * (count - 1), + 0x0000, size_addr)); + } + + aml_append(method, aml_name_decl("RBUF", rbuf)); + aml_append(method, aml_return(rbuf)); + aml_append(dev, method); + + acpi_dsdt_add_pci_osc(dev, scope); + + aml_append(scope, dev); + + } + } =20 - Aml *dev =3D aml_device("%s", "PCI0"); + dev =3D aml_device("%s", "PCI0"); aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); aml_append(dev, aml_name_decl("_SEG", aml_int(0))); @@ -302,11 +401,13 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMa= pEntry *memmap, aml_append(rbuf, aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_m= mio, - base_mmio + size_mmio - 1, 0x0000, size_mmio)); + base_mmio + size_mmio - 1 - size_addr * count, + 0x0000, size_mmio - size_addr * count)); aml_append(rbuf, aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, - AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_= pio, - size_pio)); + AML_ENTIRE_RANGE, 0x0000, 0x0000, + size_pio - 1 - size_io * count, base_pio, + size_pio - size_io * count)); =20 if (use_highmem) { hwaddr base_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].base; @@ -746,7 +847,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPO= RTS); acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), - vms->highmem, vms->highmem_ecam); + vms->highmem, vms->highmem_ecam, vms); if (vms->acpi_dev) { build_ged_aml(scope, "\\_SB."GED_DEVICE, HOTPLUG_HANDLER(vms->acpi_dev), diff --git a/hw/arm/virt.c b/hw/arm/virt.c index f788fe27d6..6314928671 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1246,6 +1246,9 @@ static void create_pcie(VirtMachineState *vms) } =20 pci =3D PCI_HOST_BRIDGE(dev); + + VIRT_MACHINE(qdev_get_machine())->bus =3D pci->bus; + if (pci->bus) { for (i =3D 0; i < nb_nics; i++) { NICInfo *nd =3D &nd_table[i]; diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 71508bf40c..90f10a1e46 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -140,6 +140,13 @@ typedef struct { DeviceState *gic; DeviceState *acpi_dev; Notifier powerdown_notifier; + /* + * pointer to devices and objects + * Via going through the bus, all + * pci devices and related objectes + * could be gained. + */ + PCIBus *bus; } VirtMachineState; =20 #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) --=20 2.19.1 From nobody Mon Feb 9 11:07:18 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1582595667; cv=none; d=zohomail.com; s=zohoarc; b=gDg58N79Pp/66lRqqJRc4Q7KiGDcF1XwD7KT7MYlxp0YW3/MtuS0TpKkPeyDzQIo/HZopDWocQwWy0jhBL8qGEM8GVVRHYSZZw+08ogYozpAEqyVnwzPM8yVUWrFxhBGJl8Yog67LkVXvdPdKvwvEIGyuAVufKAssoW264NOBC4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582595667; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=C38ohDGY4iXxbeUNrTccAJi+wrT5ju1UClJwgtmK4gk=; b=gdrXPshExnGmWxew77P+ofDgLebD5Xh4I3aF/3TvypKLBbp1wGYg0Ai2z6Nwf0zbHflyc5+Mxnf3IDnZ6APCt6d9Mn+Z+TI94I0+TXztol1XIm5C3i9hii+qBYdHmOOZc+s7FAUwxlgIcu5nSLKTwD136P8zisgKZoB1XRTEDV0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582595667962790.4031586343045; Mon, 24 Feb 2020 17:54:27 -0800 (PST) Received: from localhost ([::1]:47463 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6PQY-0003ZI-S6 for importer@patchew.org; Mon, 24 Feb 2020 20:54:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34943) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6PO8-0000UH-2N for qemu-devel@nongnu.org; Mon, 24 Feb 2020 20:51:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j6PO4-0002hm-HC for qemu-devel@nongnu.org; Mon, 24 Feb 2020 20:51:55 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:3164 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j6PNz-0002dV-50 for qemu-devel@nongnu.org; Mon, 24 Feb 2020 20:51:51 -0500 Received: from DGGEMS403-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 3DB3BCE495CB07FCCF32; Tue, 25 Feb 2020 09:50:52 +0800 (CST) Received: from DESKTOP-D7EVK5B.china.huawei.com (10.173.221.29) by DGGEMS403-HUB.china.huawei.com (10.3.19.203) with Microsoft SMTP Server id 14.3.439.0; Tue, 25 Feb 2020 09:50:46 +0800 From: Yubo Miao To: , Subject: [PATCH v4 3/3] ACPI/unit-test: Add a new test for pxb-pcie for arm Date: Tue, 25 Feb 2020 09:50:26 +0800 Message-ID: <20200225015026.940-4-miaoyubo@huawei.com> X-Mailer: git-send-email 2.24.1.windows.2 In-Reply-To: <20200225015026.940-1-miaoyubo@huawei.com> References: <20200225015026.940-1-miaoyubo@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.173.221.29] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.190 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: berrange@redhat.com, mst@redhat.com, qemu-devel@nongnu.org, xiexiangyou@huawei.com, miaoyubo@huawei.com, imammedo@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: miaoyubo Currently, pxb-pcie could be defined by the cmdline like --device pxb-pcie,id=3Dpci.9,bus_nr=3D128 However pxb-pcie is not described in acpi tables for arm. The formal two patches support pxb-pcie for arm, escpcially the specification for pxb-pcie in DSDT table. Add a testcase to make sure the ACPI table is correct for guest. The following table need to be added for this test: tests/data/acpi/virt/DSDT.pxb Since the ASL diff has 1000+ lines, it would be presented in commit log with the simply diff. the diff are: Device (PC80) is presented in DSDT. Resources allocated for Device (PCI0) is changed. * Disassembling to symbolic ASL+ operators * - * Disassembly of /home/DSDT, Mon Feb 24 19:35:28 2020 + * Disassembly of /home/DSDT.pxb, Mon Feb 24 19:33:38 2020 * * Original Table Header: * Signature "DSDT" - * Length 0x000014BB (5307) + * Length 0x00001F70 (8048) * Revision 0x02 - * Checksum 0xD1 + * Checksum 0xCF * OEM ID "BOCHS " * OEM Table ID "BXPCDSDT" * OEM Revision 0x00000001 (1) }) } + Device (PC80) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar= e ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_ADR, Zero) // _ADR: Address + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_SEG, Zero) // _SEG: PCI Segment + Name (_BBN, 0x80) // _BBN: BIOS Bus Number + Name (_UID, 0x80) // _UID: Unique ID + Name (_STR, Unicode ("pxb Device")) // _STR: Description Stri= ng + Name (_PRT, Package (0x80) // _PRT: PCI Routing Table + { + Package (0x04) + { + 0xFFFF, + Zero, + GSI0, + Zero + }, Packages are omitted. + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSI2, + Zero + } + }) + Device (GSI0) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) //= _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resourc= e Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclus= ive, ,, ) + { + 0x00000023, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource= Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclus= ive, ,, ) + { + 0x00000023, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Set= tings + { + } + } + GSI1,2,3 are omitted. + Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base A= ddress + { + Return (0x0000004010000000) + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Set= tings + { + Name (RBUF, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P= osDecode, + 0x0000, // Granularity + 0x0080, // Range Minimum + 0x0081, // Range Maximum + 0x0000, // Translation Offset + 0x0002, // Length + ,, ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x3E9F0000, // Range Minimum + 0x3EFEFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00600000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDeco= de, EntireRange, + 0x00000000, // Granularity + 0x0000C000, // Range Minimum + 0x0000FFFF, // Range Maximum + 0x3EFF0000, // Translation Offset + 0x00004000, // Length + ,, , TypeStatic, DenseTranslation) + QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x000000FFFFA00000, // Range Minimum + 0x000000FFFFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000000600000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Return (ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P= osDecode, + 0x0000, // Granularity + 0x0080, // Range Minimum + 0x0081, // Range Maximum + 0x0000, // Translation Offset + 0x0002, // Length + ,, ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x3E9F0000, // Range Minimum + 0x3EFEFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00600000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDeco= de, EntireRange, + 0x00000000, // Granularity + 0x0000C000, // Range Minimum + 0x0000FFFF, // Range Maximum + 0x3EFF0000, // Translation Offset + 0x00004000, // Length + ,, , TypeStatic, DenseTranslation) + QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x000000FFFFA00000, // Range Minimum + 0x000000FFFFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000000600000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + + Name (SUPP, Zero) + Name (CTRL, Zero) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap= abilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 =3D=3D ToUUID ("33db4d5b-1ff7-401c-9657-7441c03d= d766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + SUPP =3D CDW2 /* \_SB_.PC80._OSC.CDW2 */ + CTRL =3D CDW3 /* \_SB_.PC80._OSC.CDW3 */ + CTRL &=3D 0x1F + If ((Arg1 !=3D One)) + { + CDW1 |=3D 0x08 + } + + If ((CDW3 !=3D CTRL)) + { + CDW1 |=3D 0x10 + } + + CDW3 =3D CTRL /* \_SB_.PC80.CTRL */ + Return (Arg3) + } + Else + { + CDW1 |=3D 0x04 + Return (Arg3) + } + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Meth= od + { + If ((Arg0 =3D=3D ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3= 434d") /* Device Labeling Interface */)) + { + If ((Arg2 =3D=3D Zero)) + { + Return (Buffer (One) + { + 0x01 = // . + }) + } + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + } + Device (PCI0) { Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar= e ID WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P= osDecode, 0x0000, // Granularity 0x0000, // Range Minimum - 0x00FF, // Range Maximum + 0x007F, // Range Maximum 0x0000, // Translation Offset - 0x0100, // Length + 0x0080, // Length ,, ) DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite, 0x00000000, // Granularity 0x10000000, // Range Minimum - 0x3EFEFFFF, // Range Maximum + 0x3E9EFFFF, // Range Maximum 0x00000000, // Translation Offset - 0x2EFF0000, // Length + 0x2E9F0000, // Length ,, , AddressRangeMemory, TypeStatic) DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDeco= de, EntireRange, 0x00000000, // Granularity 0x00000000, // Range Minimum - 0x0000FFFF, // Range Maximum + 0x0000BFFF, // Range Maximum 0x3EFF0000, // Translation Offset - 0x00010000, // Length + 0x0000C000, // Length ,, , TypeStatic, DenseTranslation) QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma= xFixed, NonCacheable, ReadWrite, 0x0000000000000000, // Granularity Signed-off-by: miaoyubo --- tests/data/acpi/virt/DSDT.pxb | Bin 0 -> 8048 bytes tests/qtest/bios-tables-test-allowed-diff.h | 1 + tests/qtest/bios-tables-test.c | 54 +++++++++++++++++--- 3 files changed, 49 insertions(+), 6 deletions(-) create mode 100644 tests/data/acpi/virt/DSDT.pxb diff --git a/tests/data/acpi/virt/DSDT.pxb b/tests/data/acpi/virt/DSDT.pxb new file mode 100644 index 0000000000000000000000000000000000000000..6ac0b5212db49513c27ef50da83= 8240826c2deb7 GIT binary patch literal 8048 zcmeI1%WoT16o;=3DJC$Yzm*opISUQVG@JS#t%CM|7o60v0?=3D~7OdH@MqY)rM~D>q0l*0chOsHtU7-0 z>RNjpy|b)0W2O9FG^j|>QZ!THEg^Hd)0RlkGT+#;8>Z!rdUF%AFX1fCM#YMw$F7|1 z49CX&`Bfq}+kv<_TY*gQr1MnKQej`QKoM-h0YablDMVPEB8onus%KH6&H=3D&-ON$m=3DvMF=3Dhy3kuv0UnvodK z5JrVEi|af34Cbvhw2E)&M< zlp(LvNr^E}7^{>auhS`sag{Kdgi)5)>9oYSMi^_9A+OWC#8@DVb)R8>-?HcZd9>DA zg-T%_xy42ZGgTQ?rPkK_yd2@wm#|%}u37tDIMXlAMmv+UM)uT4>Mb>+YU&;Jp}MW! z#;d~MR(oS;^#f~vFdm7!u3BQ3;zvB*hgtY7KQU?@V6J|l*DohWrDX5)?R@j8PU^eEjK4DB(U80vMR z)SZ}-*NH@E#`=3D}-=3DnX|^@-2gsdiFBUUhkZNXRqlDCXbSO_AyU{U(6sFijYM;QBu!- z=3DGo6Y`?)7d>KSF8QLi(2OAyMaCrauWW1fiZ=3DH2t&k{I_yNj)v*X)#ZPIO>U#dd8V& zoO#B%Crav>V4ex)iO@$qQBuz&^Gq_&B=3DWt^BiTKqudiE^~B{R`Trbao(RR%6D9S` zG0zZkT)`#MhB3Hc~LGcXkH6j0Q80cG}`pl;|{`4N|)^c@4rdQM=3DO zeVpY-UCzRt1IoG}u*^Q6l}&f-YDFF6Z>UNy;wig6px+P`ZC5uNndN@#&gV%L#-DYy zukPbHtUkl1EP<4vACDJY_iufHhR2RR5=3DtNo;PFH$gcm&A1+}Qu!A`yc@$R=3DNvtOU2c)Xi^rBid7k)v~FHowgM^t&_rar3LuKbpB8?dDPJ@O`|2 zJ)w|(!Y#d}?^-tfJV>GSB&eECN>X=3DVQ)kt@HQ7?OT0uUYQ3d=3Dvn^;ZM?dH}X&vkRF zzSijGR@d$3R=3DpCsxz%;MxmB-(ZfX4M>>YR_g?v;VI8A123Uq+Jhw4K~*q`e#~wy;QaeXEVLI ze!#nvU&Q-F9=3DKOxep{~g-@2%Oy6TL1t6 literal 0 HcmV?d00001 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..90c53925fc 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,2 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/virt/DSDT.pxb", diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index b4752c644c..91e91e0fec 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -620,12 +620,21 @@ static void test_acpi_one(const char *params, test_da= ta *data) * TODO: convert '-drive if=3Dpflash' to new syntax (see e33763be7= cd3) * when arm/virt boad starts to support it. */ - args =3D g_strdup_printf("-machine %s %s -accel tcg -nodefaults -n= ographic " - "-drive if=3Dpflash,format=3Draw,file=3D%s,readonly " - "-drive if=3Dpflash,format=3Draw,file=3D%s,snapshot=3Don -cdro= m %s %s", - data->machine, data->tcg_only ? "" : "-accel kvm", - data->uefi_fl1, data->uefi_fl2, data->cd, params ? params : ""= ); - + if (data->cd) { + args =3D g_strdup_printf("-machine %s %s -accel tcg " + "-nodefaults -nographic " + "-drive if=3Dpflash,format=3Draw,file=3D%s,readonly " + "-drive if=3Dpflash,format=3Draw,file=3D%s,snapshot=3Don -= cdrom %s %s", + data->machine, data->tcg_only ? "" : "-accel kvm", + data->uefi_fl1, data->uefi_fl2, data->cd, params ? params = : ""); + } else { + args =3D g_strdup_printf("-machine %s %s -accel tcg " + "-nodefaults -nographic " + "-drive if=3Dpflash,format=3Draw,file=3D%s,readonly " + "-drive if=3Dpflash,format=3Draw,file=3D%s,snapshot=3Don %= s", + data->machine, data->tcg_only ? "" : "-accel kvm", + data->uefi_fl1, data->uefi_fl2, params ? params : ""); + } } else { /* Disable kernel irqchip to be able to override apic irq0. */ args =3D g_strdup_printf("-machine %s,kernel-irqchip=3Doff %s -acc= el tcg " @@ -960,6 +969,38 @@ static void test_acpi_virt_tcg_numamem(void) =20 } =20 +static void test_acpi_virt_tcg_pxb(void) +{ + test_data data =3D { + .machine =3D "virt", + .tcg_only =3D true, + .uefi_fl1 =3D "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 =3D "pc-bios/edk2-arm-vars.fd", + .ram_start =3D 0x40000000ULL, + .scan_len =3D 128ULL * 1024 * 1024, + }; + /* + * While using -cdrom, the cdrom would auto plugged into pxb-pcie, + * the reason is the bus of pxb-pcie is also root bus, it would lead + * to the error only PCI/PCIE bridge could plug onto pxb. + * Therefore,thr cdrom is defined and plugged onto the scsi controller + * to solve the conflicts. + */ + data.variant =3D ".pxb"; + test_acpi_one(" -device pcie-root-port,chassis=3D1,id=3Dpci.1" + " -device virtio-scsi-pci,id=3Dscsi0,bus=3Dpci.1" + " -drive file=3D" + "tests/data/uefi-boot-images/bios-tables-test.aarch64.is= o.qcow2," + "if=3Dnone,media=3Dcdrom,id=3Ddrive-scsi0-0-0-1,readonly= =3Don" + " -device scsi-cd,bus=3Dscsi0.0,scsi-id=3D0," + "drive=3Ddrive-scsi0-0-0-1,id=3Dscsi0-0-0-1,bootindex=3D= 1" + " -cpu cortex-a57" + " -device pxb-pcie,bus_nr=3D128", + &data); + + free_test_data(&data); +} + static void test_acpi_tcg_acpi_hmat(const char *machine) { test_data data; @@ -1052,6 +1093,7 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/virt", test_acpi_virt_tcg); qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem); qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp); + qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb); } ret =3D g_test_run(); boot_sector_cleanup(disk); --=20 2.19.1