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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id o6sm13897097pgg.37.2020.02.24.14.22.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 14:22:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=04w4nAykREQYlFaDlCPkF+ClHIRvIg4T3qLIcZORCLQ=; b=RESOnh7ZVqABL9e9EkhNypENrNTmIKFmCDKjHRkcvufJlnIaC9RFyKDoEJFf1Smggp ZHSp1nb9lEGqnGBLq73Y9irDfXnuXHdtMPad+XEFGkD4utjPp3p+Co1jO5R37pkxmhmY 1n2d2LjG7T/OGZA9V2uOoy6YC/RJLnH1kbxK8dU9UtV4rSsyANp6vNN4oEW64CdttH07 MyIZwJbXfwT0pMB1M+uOd5dUVgFelzZBvOAMkyk7+bk0pSHvDbHE7y0lW3Gf7O7F2cbi MEGUhJT+kUlf0pCrO6X4bLOegZ+tHoUoO0424X1zVf7iqMrrEMvhhckceleTAZmOItfS ZFGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=04w4nAykREQYlFaDlCPkF+ClHIRvIg4T3qLIcZORCLQ=; b=Uwj/q6BQPRIEttvUzaJgPSvn193ULyVgtN2itYuTY9/7FeXfzwr77zzQb5UPBNdXao yBsumYCi3pN6TCf3HOlvekR9gOZXjntdaE0RQ9xeLcXUxbVzuf6tE/v449ZYQwWn0gb1 OBwE8NUg16GqpTFgHMCDANriqwGFPL5vS7goNdr8tH/toEK7oYXRTt6hcXjg6zftRyn/ qQEP5ERYE/ZUt9bQh8UC3zMCI4qJqjSzonZHkC5KJ+oYBXMFIuua6Ao2XbeWRwlXjthG c40e3rwBzSlMXbG9jVRVxHLMvnQBt0SMSMAUuUu3pHfJPdp87zaKP2tPChFqIFwqP7ch DzdQ== X-Gm-Message-State: APjAAAVAYTzlDprM9c/dtm/t3Q7K7Ga8MewrJ4DBLan7irqLWHM5WQtG usVbj7da6Mo0y+jzrcsRov4RnCYPR2U= X-Google-Smtp-Source: APXvYqxKy6234epOsW9E8YZ1XRGBdazrx2Qb1QMsg5KAAe/ZZ+zEX7myG2O9gp0PyO+Sulp0peJMWQ== X-Received: by 2002:a65:65c8:: with SMTP id y8mr25943548pgv.36.1582582962103; Mon, 24 Feb 2020 14:22:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 06/17] target/arm: Perform fpdp_v2 check first Date: Mon, 24 Feb 2020 14:22:21 -0800 Message-Id: <20200224222232.13807-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224222232.13807-1-richard.henderson@linaro.org> References: <20200224222232.13807-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 140 +++++++++++++++++---------------- 1 file changed, 71 insertions(+), 69 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index e94876c30c..ff30165045 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -200,13 +200,13 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vn | a->vd) & 0x10)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && + ((a->vm | a->vn | a->vd) & 0x10)) { return false; } =20 @@ -333,13 +333,13 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMIN= MAXNM *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vn | a->vd) & 0x10)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && + ((a->vm | a->vn | a->vd) & 0x10)) { return false; } =20 @@ -419,13 +419,13 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vd) & 0x10)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && + ((a->vm | a->vd) & 0x10)) { return false; } =20 @@ -483,12 +483,12 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 @@ -1308,12 +1308,12 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3O= pDPFn *fn, TCGv_i64 f0, f1, fd; TCGv_ptr fpst; =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) { return false; } =20 @@ -1457,12 +1457,12 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2O= pDPFn *fn, int vd, int vm) int veclen =3D s->vec_len; TCGv_i64 f0, fd; =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) { return false; } =20 @@ -1827,7 +1827,9 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp = *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { return false; } =20 @@ -1921,12 +1923,12 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_= VMOV_imm_dp *a) =20 vd =3D a->vd; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) { return false; } =20 @@ -2060,6 +2062,10 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_= dp *a) { TCGv_i64 vd, vm; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + /* Vm/M bits must be zero for the Z variant */ if (a->z && a->vm !=3D 0) { return false; @@ -2070,10 +2076,6 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_= dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2134,6 +2136,10 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_= VCVT_f64_f16 *a) TCGv_i32 tmp; TCGv_i64 vd; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_fp16_dpconv, s)) { return false; } @@ -2143,10 +2149,6 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_= VCVT_f64_f16 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2200,6 +2202,10 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_= VCVT_f16_f64 *a) TCGv_i32 tmp; TCGv_i64 vm; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_fp16_dpconv, s)) { return false; } @@ -2209,10 +2215,6 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_= VCVT_f16_f64 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2260,6 +2262,10 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRI= NTR_dp *a) TCGv_ptr fpst; TCGv_i64 tmp; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_vrint, s)) { return false; } @@ -2269,10 +2275,6 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRI= NTR_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2321,6 +2323,10 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRI= NTZ_dp *a) TCGv_i64 tmp; TCGv_i32 tcg_rmode; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_vrint, s)) { return false; } @@ -2330,10 +2336,6 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRI= NTZ_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2380,6 +2382,10 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRI= NTX_dp *a) TCGv_ptr fpst; TCGv_i64 tmp; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_vrint, s)) { return false; } @@ -2389,10 +2395,6 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRI= NTX_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2412,12 +2414,12 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT= _sp *a) TCGv_i64 vd; TCGv_i32 vm; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; } =20 @@ -2440,12 +2442,12 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT= _dp *a) TCGv_i64 vm; TCGv_i32 vd; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 @@ -2494,12 +2496,12 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_= VCVT_int_dp *a) TCGv_i64 vd; TCGv_ptr fpst; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; } =20 @@ -2530,6 +2532,10 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *= a) TCGv_i32 vd; TCGv_i64 vm; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_jscvt, s)) { return false; } @@ -2539,10 +2545,6 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *= a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2623,6 +2625,10 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_V= CVT_fix_dp *a) TCGv_ptr fpst; int frac_bits; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { return false; } @@ -2632,10 +2638,6 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_V= CVT_fix_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2723,12 +2725,12 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_= VCVT_dp_int *a) TCGv_i64 vm; TCGv_ptr fpst; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 --=20 2.20.1