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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id o6sm13897097pgg.37.2020.02.24.14.22.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 14:22:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Sk0MOHyrllS0IcT8aMOfzN1UEtehTWfA11kplAVqlII=; b=uxlYRhCSH4fS8zWfj8VjQDzE3g3bBU/eoB0Vtq5JAmM3GnyuIpRxWGbviTEvhBPt5z 7bQ9XP4JsMhy7wq9Juq87Fvo+9dlonqBwvfy/UDnqmokfRaYnKyn9BJ5ArIYd5sT9Lni P+aFXA840NgV3/nsAJOAvPPpD8tkJZ3erQMGM7pBgQrSFA7mvbuxkgqvhziviYdCzIaQ T349Rsuc0vg/tuJT69bl2YlTR4pBk63TbMi+NMXWChKK99SLUIGJjcs+eAGSTOUQ1RZ8 F6U/D4plCkjczUamaNFnp9/UW5ItQlvBfBbg2+/wqtVX6uyPzeNMw049L0krORY2v+Xx UlWQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Sk0MOHyrllS0IcT8aMOfzN1UEtehTWfA11kplAVqlII=; b=NSaetnvaTX5zf7HXQm1AndGjvDTdTrnUxFHXhxcmcNEXeBJjjm1hIcZgyI3IHvqRIH Vm1pzbcVKRi/YsVQkYfWGHcCmx0p/vQ3NEH2TX+TFcI3ndy6Imy7X0Jc2YcKYikeyFdC mgz6kuHgMT0Re5l/dQsJvK3te5/7vFaSfFyt8511J874kjnLjhTa4rtxyY2kzLJYLiSg VeDE1OOO+UlYRlmZxU2qttFAdJwP5Ywg5paV/UvHr7pakJfXyuYvB7PcRMxBOGg4mfoh O8SZBbNzrUaSfLjSlf09T/QaXv8Ldccyf4aZAPX79HkwUmr2rBH4ybYJSlCnq1F9XDZ/ Mwaw== X-Gm-Message-State: APjAAAVASnRE3rSf0gcC0eVYLf2ZD4otLT9GjfpqtR7HQGKJdevr6+N4 Nf/LYQZrpVmCU0VeCwrlXLovpDUkL3k= X-Google-Smtp-Source: APXvYqw9YQFEW9vALio9hD/0U0J/E1oUUJdhZx3Qyy97bUnvHl/7FtsMiW12EIQwpJnPGfHe8wL3Uw== X-Received: by 2002:a62:f94d:: with SMTP id g13mr53023785pfm.60.1582582955690; Mon, 24 Feb 2020 14:22:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 01/17] target/arm: Add isar_feature_aa32_vfp_simd Date: Mon, 24 Feb 2020 14:22:16 -0800 Message-Id: <20200224222232.13807-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224222232.13807-1-richard.henderson@linaro.org> References: <20200224222232.13807-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use this in the places that were checking ARM_FEATURE_VFP, and are obviously testing for the existance of the register set as opposed to testing for some particular instruction extension. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 9 +++++++++ hw/intc/armv7m_nvic.c | 20 ++++++++++---------- linux-user/arm/signal.c | 4 ++-- target/arm/arch_dump.c | 11 ++++++----- target/arm/cpu.c | 4 ++-- target/arm/helper.c | 4 ++-- target/arm/m_helper.c | 11 ++++++----- 7 files changed, 37 insertions(+), 26 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 65171cb30e..a128d48d40 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3450,6 +3450,15 @@ static inline bool isar_feature_aa32_fp16_arith(cons= t ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) =3D=3D 1; } =20 +static inline bool isar_feature_aa32_vfp_simd(const ARMISARegisters *id) +{ + /* + * Return true if either VFP or SIMD is implemented. + * In this case, a minimum of VFP w/ D0-D15. + */ + return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; +} + static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) { /* Return true if D16-D31 are implemented */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 22a43e4984..a62587eb3f 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1262,12 +1262,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) case 0xd84: /* CSSELR */ return cpu->env.v7m.csselr[attrs.secure]; case 0xd88: /* CPACR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } return cpu->env.v7m.cpacr[attrs.secure]; case 0xd8c: /* NSACR */ - if (!attrs.secure || !arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!attrs.secure || !cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } return cpu->env.v7m.nsacr; @@ -1417,7 +1417,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) } return cpu->env.v7m.sfar; case 0xf34: /* FPCCR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } if (attrs.secure) { @@ -1444,12 +1444,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) return value; } case 0xf38: /* FPCAR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } return cpu->env.v7m.fpcar[attrs.secure]; case 0xf3c: /* FPDSCR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } return cpu->env.v7m.fpdscr[attrs.secure]; @@ -1711,13 +1711,13 @@ static void nvic_writel(NVICState *s, uint32_t offs= et, uint32_t value, } break; case 0xd88: /* CPACR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { /* We implement only the Floating Point extension's CP10/CP11 = */ cpu->env.v7m.cpacr[attrs.secure] =3D value & (0xf << 20); } break; case 0xd8c: /* NSACR */ - if (attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (attrs.secure && cpu_isar_feature(aa32_vfp_simd, cpu)) { /* We implement only the Floating Point extension's CP10/CP11 = */ cpu->env.v7m.nsacr =3D value & (3 << 10); } @@ -1951,7 +1951,7 @@ static void nvic_writel(NVICState *s, uint32_t offset= , uint32_t value, break; } case 0xf34: /* FPCCR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { /* Not all bits here are banked. */ uint32_t fpccr_s; =20 @@ -2005,13 +2005,13 @@ static void nvic_writel(NVICState *s, uint32_t offs= et, uint32_t value, } break; case 0xf38: /* FPCAR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { value &=3D ~7; cpu->env.v7m.fpcar[attrs.secure] =3D value; } break; case 0xf3c: /* FPDSCR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { value &=3D 0x07c00000; cpu->env.v7m.fpdscr[attrs.secure] =3D value; } diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c index b0e753801b..d96fc27ce1 100644 --- a/linux-user/arm/signal.c +++ b/linux-user/arm/signal.c @@ -346,7 +346,7 @@ static void setup_sigframe_v2(struct target_ucontext_v2= *uc, setup_sigcontext(&uc->tuc_mcontext, env, set->sig[0]); /* Save coprocessor signal frame. */ regspace =3D uc->tuc_regspace; - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { regspace =3D setup_sigframe_v2_vfp(regspace, env); } if (arm_feature(env, ARM_FEATURE_IWMMXT)) { @@ -671,7 +671,7 @@ static int do_sigframe_return_v2(CPUARMState *env, =20 /* Restore coprocessor signal frame */ regspace =3D uc->tuc_regspace; - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { regspace =3D restore_sigframe_v2_vfp(env, regspace); if (!regspace) { return 1; diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 2345dec3c2..7693e17e96 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -363,9 +363,11 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, = CPUState *cs, int cpuid, void *opaque) { struct arm_note note; - CPUARMState *env =3D &ARM_CPU(cs)->env; + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; DumpState *s =3D opaque; - int ret, i, fpvalid =3D !!arm_feature(env, ARM_FEATURE_VFP); + int ret, i; + bool fpvalid =3D cpu_isar_feature(aa32_vfp_simd, cpu); =20 arm_note_init(¬e, s, "CORE", 5, NT_PRSTATUS, sizeof(note.prstatus)); =20 @@ -444,7 +446,6 @@ int cpu_get_dump_info(ArchDumpInfo *info, ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) { ARMCPU *cpu =3D ARM_CPU(first_cpu); - CPUARMState *env =3D &cpu->env; size_t note_size; =20 if (class =3D=3D ELFCLASS64) { @@ -452,12 +453,12 @@ ssize_t cpu_get_note_size(int class, int machine, int= nr_cpus) note_size +=3D AARCH64_PRFPREG_NOTE_SIZE; #ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_sve, cpu)) { - note_size +=3D AARCH64_SVE_NOTE_SIZE(env); + note_size +=3D AARCH64_SVE_NOTE_SIZE(&cpu->env); } #endif } else { note_size =3D ARM_PRSTATUS_NOTE_SIZE; - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { note_size +=3D ARM_VFP_NOTE_SIZE; } } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2eadf4dcb8..be4c2a1253 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -293,7 +293,7 @@ static void arm_cpu_reset(CPUState *s) env->v7m.ccr[M_REG_S] |=3D R_V7M_CCR_UNALIGN_TRP_MASK; } =20 - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { env->v7m.fpccr[M_REG_NS] =3D R_V7M_FPCCR_ASPEN_MASK; env->v7m.fpccr[M_REG_S] =3D R_V7M_FPCCR_ASPEN_MASK | R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; @@ -1011,7 +1011,7 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f,= int flags) int numvfpregs =3D 0; if (cpu_isar_feature(aa32_simd_r32, cpu)) { numvfpregs =3D 32; - } else if (arm_feature(env, ARM_FEATURE_VFP)) { + } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { numvfpregs =3D 16; } for (i =3D 0; i < numvfpregs; i++) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 79db169e04..8841cc7fde 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -894,7 +894,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. * TRCDIS [28] is RAZ/WI since we do not implement a trace macroce= ll. */ - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { /* VFP coprocessor: cp10 & cp11 [23:20] */ mask |=3D (1 << 31) | (1 << 30) | (0xf << 20); =20 @@ -7814,7 +7814,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 35, "arm-vfp3.xml", 0); - } else if (arm_feature(env, ARM_FEATURE_VFP)) { + } else if (cpu_isar_feature(aa32_vfp_simd, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 19, "arm-vfp.xml", 0); } diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 33d414a684..5e8a795d20 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -738,7 +738,8 @@ static uint32_t v7m_integrity_sig(CPUARMState *env, uin= t32_t lr) */ uint32_t sig =3D 0xfefa125a; =20 - if (!arm_feature(env, ARM_FEATURE_VFP) || (lr & R_V7M_EXCRET_FTYPE_MAS= K)) { + if (!cpu_isar_feature(aa32_vfp_simd, env_archcpu(env)) + || (lr & R_V7M_EXCRET_FTYPE_MASK)) { sig |=3D 1; } return sig; @@ -841,7 +842,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t l= r, bool dotailchain, =20 if (dotailchain) { /* Sanitize LR FType and PREFIX bits */ - if (!arm_feature(env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { lr |=3D R_V7M_EXCRET_FTYPE_MASK; } lr =3D deposit32(lr, 24, 8, 0xff); @@ -1373,7 +1374,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) =20 ftype =3D excret & R_V7M_EXCRET_FTYPE_MASK; =20 - if (!arm_feature(env, ARM_FEATURE_VFP) && !ftype) { + if (!ftype && !cpu_isar_feature(aa32_vfp_simd, cpu)) { qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception= " "exit PC value 0x%" PRIx32 " is UNPREDICTABLE " "if FPU not present\n", @@ -2450,7 +2451,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskr= eg, uint32_t val) * SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 =3D=3D 0, * RES0 if the FPU is not present, and is stored in the S bank */ - if (arm_feature(env, ARM_FEATURE_VFP) && + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env)) && extract32(env->v7m.nsacr, 10, 1)) { env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_FPCA_MASK; env->v7m.control[M_REG_S] |=3D val & R_V7M_CONTROL_FPCA_MA= SK; @@ -2565,7 +2566,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskr= eg, uint32_t val) env->v7m.control[env->v7m.secure] &=3D ~R_V7M_CONTROL_NPRIV_MA= SK; env->v7m.control[env->v7m.secure] |=3D val & R_V7M_CONTROL_NPR= IV_MASK; } - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { /* * SFPA is RAZ/WI from NS or if no FPU. * FPCA is RO if NSACR.CP10 =3D=3D 0, RES0 if the FPU is not p= resent. --=20 2.20.1 From nobody Sun May 19 07:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582583026; cv=none; d=zohomail.com; s=zohoarc; b=RsR/5FgoGNnhe8aI31j6afjjKsWkF3Emn0lo0zfpV2qwbRJNt08iSsPfEa+vkNq7CChbJi+VUqvXAHr871+Ch0aQ41amIzx5Tr+e7JryF2/kh5ukLsCNEjLScFHdNUbbnepwRr1feJL5kBE49U+7ak8tN5N7R9WQeXinHowr6ow= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582583026; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8VBDdJ2XXe8vgr+0Pu3Ei4ErsKpoLGqHBt+iFGkJN3g=; b=ZmA6xbY6CqHPg88jfI22LR3HvZfDyRXkrUjqj1fqrcOItZnsNrtomeUUuMynLuWMtBaZoc87qAIHqnQEaO73lruuyozOf38a4I38XUhTRvfxsbAeqqRTRf76U2bRXhSM34D20vDTW5pR0jz8eISJzsyl+mh1XVwR+c/PxhXuiHE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158258302633353.05766469152627; Mon, 24 Feb 2020 14:23:46 -0800 (PST) Received: from localhost ([::1]:45166 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6M8d-0005db-Sp for importer@patchew.org; Mon, 24 Feb 2020 17:23:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37700) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6M7c-00042V-8p for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:41 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j6M7a-0005ka-Kx for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:40 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:41222) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j6M7a-0005k1-F3 for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:38 -0500 Received: by mail-pf1-x444.google.com with SMTP id j9so6066832pfa.8 for ; Mon, 24 Feb 2020 14:22:38 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id o6sm13897097pgg.37.2020.02.24.14.22.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 14:22:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8VBDdJ2XXe8vgr+0Pu3Ei4ErsKpoLGqHBt+iFGkJN3g=; b=w4z1kwQPk/JnG8w6+Gzb05842L5NXu3+w8WpW7vUfNqbqCMHrdqbpeYCQcgMnHQSJL w/eeRExZx6WeEVRuZUOMNoy2nBfCkUbBkGSyUOlC2RU9EvebswVAAQJVFXESkXgl9jfp LhVZs8CDzaQsjN/Wsy00R9Mg5uWmsSstW3lgPWAkjG6aL97/KG+caAXy1Wgh8ghLjjOD NcKRIiddA5BmQxl7Qjg4Lr3sl0pEbFhGFFvNn+8t0tOUV7G2qu1P8uzs33Pm9sWwp7rl cOu58Qv+gdNwnx6DkWFcYrJaPgZTqM9LBfr8rjd39+dykYGt02PEjR3RjykOTVsOn/WB coaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8VBDdJ2XXe8vgr+0Pu3Ei4ErsKpoLGqHBt+iFGkJN3g=; b=Q91KNZNP7PgZi3K5MjgNIE9M4UU1IsuA7BdxevVHrgwX6cgL+Tr8s1FRUsmCaFdJJA kVXSCUuHdCJqkKxfWVzJIJiBLNpZKU9ptWwiaEeVVhmLumqnvr2wy34Q6y8BYYzAV7nj +iEW+WSHb+AGg/nr8QnZ6YiRCJZRRahD+O6u6fiAsY6FtfDn8CDn35Ceq8IA0TYkXx2p 2nzTBdZO+qHVlzE74ki8VxcFg2CIMe4Z1dMcm/HIXRQRfrWWntaBu+T7q1oyDCTeQMHr Mdqc4mGxcIP2Em9GrSjZUIeYu+tiJXdkC8R+5DL72HK0CL9MN4RF1ZK3uITZN8oY6Ldp 8PxQ== X-Gm-Message-State: APjAAAVd3dIux1Qf75H4GWybHO/4lvptCT/JTYDfXUKPt/nNcO8iXQWD J1UFYhoQ+H60sg8YPG8gCz08XbjdpQo= X-Google-Smtp-Source: APXvYqz1eBvHybCPueVJTAC+W/5x6Gv2IKC1OMU1dlYTAQrWqbYKshB6SjoBmELU187830899hKDfw== X-Received: by 2002:a63:48f:: with SMTP id 137mr8382543pge.245.1582582957128; Mon, 24 Feb 2020 14:22:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 02/17] target/arm: Rename isar_feature_aa32_fpdp_v2 Date: Mon, 24 Feb 2020 14:22:17 -0800 Message-Id: <20200224222232.13807-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224222232.13807-1-richard.henderson@linaro.org> References: <20200224222232.13807-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The old name, isar_feature_aa32_fpdp, does not reflect that the test includes VFPv2. We will introduce another feature tests for VFPv3. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- target/arm/cpu.h | 4 ++-- target/arm/translate-vfp.inc.c | 40 +++++++++++++++++----------------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a128d48d40..1e6eac0cd2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3470,9 +3470,9 @@ static inline bool isar_feature_aa32_fpshvec(const AR= MISARegisters *id) return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; } =20 -static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id) +static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) { - /* Return true if CPU supports double precision floating point */ + /* Return true if CPU supports double precision floating point, VFPv2 = */ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; } =20 diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index ba46e2557a..e94876c30c 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -206,7 +206,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -339,7 +339,7 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMA= XNM *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -425,7 +425,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -488,7 +488,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1313,7 +1313,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpD= PFn *fn, return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1462,7 +1462,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpD= PFn *fn, int vd, int vm) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1827,7 +1827,7 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp = *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1926,7 +1926,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VM= OV_imm_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2070,7 +2070,7 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_d= p *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2143,7 +2143,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_V= CVT_f64_f16 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2209,7 +2209,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_V= CVT_f16_f64 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2269,7 +2269,7 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRIN= TR_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2330,7 +2330,7 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRIN= TZ_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2389,7 +2389,7 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRIN= TX_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2417,7 +2417,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_s= p *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2445,7 +2445,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_d= p *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2499,7 +2499,7 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VC= VT_int_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2539,7 +2539,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2632,7 +2632,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VC= VT_fix_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2728,7 +2728,7 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VC= VT_dp_int *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 --=20 2.20.1 From nobody Sun May 19 07:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id o6sm13897097pgg.37.2020.02.24.14.22.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 14:22:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+KPvmzpCR5seSYv8kHpAw1AZPr6kKDFij7TNxO0T5iM=; b=Uqbxg0jSTQpcnURf4xEmKosWe03wCLnDnGlU62zj/rU1xQnYsUL6vQG0jaC9wVQPXK WtQff6VthTSvakTFz3/W48U2KAmz1ecxTW2YtTKKJcpUBA5mFUF66a+hScksICwFjzFp 6Jx+BTSAHh5bSaUNHhiG+8my02XfdjFc9oxNwoPRWYeAuVVrEvZwX4AvVmIPGtSwtE/V GiMAskG/CbY5Y4X2h09T25GrenbWLQwWBergpjA/5zPM8bhnIbpRmbe/OcqIYL6bu469 PE00pxAprU2rjHmVybQtqoMaC9amatDPxORqbb3//kIu0dbLah9VUG7vdo6iOM8n1ECW il7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+KPvmzpCR5seSYv8kHpAw1AZPr6kKDFij7TNxO0T5iM=; b=tcjG2SEzxHT/aIEhNs+iUSHZFXYFnbuWyYGGxgE+yUtEAhPe9iB+qipYfUK2hkHdOL jM+DshqIbWhzu/rrYsLY3G8UUW0CWwKiVzhKKWvllIckp+N4zaC9qHzD0b5lhmKAzMd0 WbZqA0sUnbb7j0Lj2PSpqbTnYayypNfbZQXsQu1/1LIo5Hy1W71c4M4rp3kYnDSMYSN5 qtDjaP7+IRLJriSzwM1IgVt3v92CSM4hNNAKEcme1IQNZScbNxuCUJ77C62h4mOKwxM4 FVAsmXfswlXWC1Cli78HIwHkU/H8mx+u9MprKbAKcvwNLl2PxJ9Qh4oK9iKaybh2n+l7 a19w== X-Gm-Message-State: APjAAAXhWkFPer01NmA8BIdWo7AObRBoV2QkCZ1z8SaczI/l8hen1T5C DbpzT44rMMjKqXOAdpHfn4Ju0Daj+8k= X-Google-Smtp-Source: APXvYqwYmDDa1kiSLy6Lyv/nLy8yB9hev2ZoIks/fwYW5rdpiub2h4RP07XawZgGNCJLO2Wtk1eA0A== X-Received: by 2002:aa7:8ad9:: with SMTP id b25mr53268382pfd.70.1582582958411; Mon, 24 Feb 2020 14:22:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 03/17] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} Date: Mon, 24 Feb 2020 14:22:18 -0800 Message-Id: <20200224222232.13807-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224222232.13807-1-richard.henderson@linaro.org> References: <20200224222232.13807-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" We will shortly use these to test for VFPv2 and VFPv3 in different situations. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1e6eac0cd2..f7a90f512e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3470,12 +3470,30 @@ static inline bool isar_feature_aa32_fpshvec(const = ARMISARegisters *id) return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; } =20 +static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) +{ + /* Return true if CPU supports single precision floating point, VFPv2 = */ + return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; +} + +static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) +{ + /* Return true if CPU supports single precision floating point, VFPv3 = */ + return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >=3D 2; +} + static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) { /* Return true if CPU supports double precision floating point, VFPv2 = */ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; } =20 +static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) +{ + /* Return true if CPU supports double precision floating point, VFPv3 = */ + return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >=3D 2; +} + /* * We always set the FP and SIMD FP16 fields to indicate identical * levels of support (assuming SIMD is implemented at all), so --=20 2.20.1 From nobody Sun May 19 07:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582583571; cv=none; d=zohomail.com; s=zohoarc; b=kfVZRw5ovtie7k0VB5pzaTh/U4ZAXK+kPOHEm/j5YXJBvhNihmst5m93XTTDZOSaigQqHiEfUdKWpOfFxK2Z1qZw7XTyrVkUVDhBdnUKqWK8sbrcimh7hqgUd7JPFXFk7PWZId1GSPrW74Wl9elYz1lfVQxlEK8SNpz1fdEPEfI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582583571; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fkzyGWRSXdTJhJxOryRfsTh15ycVqgk6twtD/0ShqhM=; b=HyVR98o6pNZV5Mjm2XUpybALokd5saJbkXnm6jEixa2oI55PSGk33QG4NOD4hMtudFsQF6exAneqNtURhSGxDTlFPxuW3EE3CIM9KCC/futpifp5aJxq/timnDScyR2XvBJou+V0T6lzAPK1QmkF/ULUwk8Lj1edESwFeQYCW0k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582583571732351.4561470062562; Mon, 24 Feb 2020 14:32:51 -0800 (PST) Received: from localhost ([::1]:45468 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6MHS-0004rg-KD for importer@patchew.org; Mon, 24 Feb 2020 17:32:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37756) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6M7e-00046A-D9 for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j6M7d-0005o0-6C for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:42 -0500 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]:55947) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j6M7d-0005nN-0s for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:41 -0500 Received: by mail-pj1-x1042.google.com with SMTP id d5so353532pjz.5 for ; Mon, 24 Feb 2020 14:22:40 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id o6sm13897097pgg.37.2020.02.24.14.22.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 14:22:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fkzyGWRSXdTJhJxOryRfsTh15ycVqgk6twtD/0ShqhM=; b=ZIiZp6BQh+GleQv7Rca9wbyU29s8BiX2n4uTR5x20mHeKhHbeebuX10GFqD2eluxOF tRazJJiFtlhw4byypMlQrIcFmTcvKFGF2V9TFs8emCHyF8K4lb41bSseWDu/pdLIx0qr 9iAMcK5Wpqmblmz8rsO42bucwfaAHrueDlm40r3zyLML/nqAGtJncI6yfbmERfJFCRSO osetWS7UntZ3ANyaQ+XlcLNfvhDUQUPihLW19yKr1ohMyu6QXl14GkFchAr4bsy186/F zBu8bro/sGqV5ExjHQ5IKSgWw84psiP8dOw4Ycwn5imVJthVM/XZREnvTzghKm/1BleQ KFMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fkzyGWRSXdTJhJxOryRfsTh15ycVqgk6twtD/0ShqhM=; b=CIuvpRQKMWRE0PKZOa9dkOWSZNzMp/13Wh0d16f5KM4Mptb62EWqOVIWhLUuT2mN/6 V7esvuahbLKnSg/obcKe2AOvcYxEkg0qrXapAdhbJnQMNXt+rLvn9QfGneMVXNP+ezAm QK8+AqQ0cEvj1TgMFF0yxGKmyXrI34m3ma6L3MPUHkwExlNHNM2SOIvyVW7aDX0TPMWh JEztQA0o8SHazareTmZjOuYDX5wrn1qz1T9wdYZA9l8jZlp/Bo0eOZeBOLB5efAMjT5Y tCEbcxG3VVMCkUxl+HnHblXuN/kDFAiBtiRUaOM4ctLoZtBXzPCaKIEDwRQMyJwEQuQp ReYw== X-Gm-Message-State: APjAAAVEe/5kLPsNRqy/TzRJMnjUJGe9cru/6JAgT0tCQAwUwaF/uKhw xfqVA0Wrq3FTeK/YtHEXNnlr1+lKJYE= X-Google-Smtp-Source: APXvYqxcBYmHnV+0TierSwaC8cJ2YfYouTi62Gz51hiq27WOJSqS+3lwE5ZjG8EBQUEBbUThYudVww== X-Received: by 2002:a17:90b:14a:: with SMTP id em10mr1479681pjb.4.1582582959513; Mon, 24 Feb 2020 14:22:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 04/17] target/arm: Add isar_feature_aa64_fp_simd, isar_feature_aa32_vfp Date: Mon, 24 Feb 2020 14:22:19 -0800 Message-Id: <20200224222232.13807-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224222232.13807-1-richard.henderson@linaro.org> References: <20200224222232.13807-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1042 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We cannot easily create "any" functions for these, because the ID_AA64PFR0 fields for FP and SIMD signal "enabled" with zero. Which means that an aarch32-only cpu will return incorrect results when testing the aarch64 registers. To use these, we must either have context or additionally test vs ARM_FEATURE_AARCH64. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 11 +++++++++++ target/arm/cpu.c | 9 ++++++--- target/arm/machine.c | 5 +++-- 3 files changed, 20 insertions(+), 5 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f7a90f512e..b94d2a5ace 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3494,6 +3494,11 @@ static inline bool isar_feature_aa32_fpdp_v3(const A= RMISARegisters *id) return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >=3D 2; } =20 +static inline bool isar_feature_aa32_vfp(const ARMISARegisters *id) +{ + return isar_feature_aa32_fpsp_v2(id) || isar_feature_aa32_fpdp_v2(id); +} + /* * We always set the FP and SIMD FP16 fields to indicate identical * levels of support (assuming SIMD is implemented at all), so @@ -3696,6 +3701,12 @@ static inline bool isar_feature_aa64_dcpodp(const AR= MISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, DPB) >=3D 2; } =20 +static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) +{ + /* We always set the AdvSIMD and FP fields identically. */ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) !=3D 0xf; +} + static inline bool isar_feature_aa64_fp16(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically wrt FP16. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index be4c2a1253..5be4c25809 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1260,7 +1260,9 @@ void arm_cpu_post_init(Object *obj) * KVM does not currently allow us to lie to the guest about its * ID/feature registers, so the guest always sees what the host has. */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) + ? cpu_isar_feature(aa64_fp_simd, cpu) + : cpu_isar_feature(aa32_vfp, cpu)) { cpu->has_vfp =3D true; if (!kvm_enabled()) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_propert= y); @@ -1636,8 +1638,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * We rely on no XScale CPU having VFP so we can use the same bits in = the * TB flags field for VECSTRIDE and XSCALE_CPAR. */ - assert(!(arm_feature(env, ARM_FEATURE_VFP) && - arm_feature(env, ARM_FEATURE_XSCALE))); + assert(arm_feature(&cpu->env, ARM_FEATURE_AARCH64) || + !cpu_isar_feature(aa32_vfp_simd, cpu) || + !arm_feature(env, ARM_FEATURE_XSCALE)); =20 if (arm_feature(env, ARM_FEATURE_V7) && !arm_feature(env, ARM_FEATURE_M) && diff --git a/target/arm/machine.c b/target/arm/machine.c index 241890ac8c..c5a2114f51 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -9,9 +9,10 @@ static bool vfp_needed(void *opaque) { ARMCPU *cpu =3D opaque; - CPUARMState *env =3D &cpu->env; =20 - return arm_feature(env, ARM_FEATURE_VFP); + return (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) + ? cpu_isar_feature(aa64_fp_simd, cpu) + : cpu_isar_feature(aa32_vfp_simd, cpu)); } =20 static int get_fpscr(QEMUFile *f, void *opaque, size_t size, --=20 2.20.1 From nobody Sun May 19 07:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582583668; cv=none; d=zohomail.com; s=zohoarc; b=j6nAnDoJ1vXa48mlnyI/fgv01NtkUsKwHMpS/E6k1aiVbQ0M1kuhUckpS1dLzVMIMl6aSx0osSvGAK8rWY0NKZUVxiD9wqAFA6+6i3QMDahlcLrZqfZMsFlyTv/76U8G3dq6A8RGT7pOxF6i4p7/KXzQK4FVBCxePzc1nKmBOxM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582583668; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LpDXkMJymCkBigdAeSGEBRetKSjrJSWM6nnEjxNkcOs=; b=N1UTHpXOegAOK8T0YJnRln/xJyI/d6bdCcpYEAe+OXGYL/dfPURQtxq9yhwygBlXjOIlmsec+8ts6WHRpRav/fFqWtBq1j+ZIVO8vcU3xzgtRp8eNZKcl1PoL/hYg4HteqXWiKAdcVAsQUh3PbnWuiuU7AJL1DwYUmVa2VfluTg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582583668630212.0240486690376; Mon, 24 Feb 2020 14:34:28 -0800 (PST) Received: from localhost ([::1]:45500 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6MJ1-0007eV-HG for importer@patchew.org; Mon, 24 Feb 2020 17:34:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37780) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6M7f-00048Y-Es for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j6M7e-0005oj-Cw for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:43 -0500 Received: from mail-pf1-x444.google.com ([2607:f8b0:4864:20::444]:45684) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j6M7e-0005oE-72 for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:42 -0500 Received: by mail-pf1-x444.google.com with SMTP id 2so6053207pfg.12 for ; Mon, 24 Feb 2020 14:22:42 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id o6sm13897097pgg.37.2020.02.24.14.22.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 14:22:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LpDXkMJymCkBigdAeSGEBRetKSjrJSWM6nnEjxNkcOs=; b=qLd16HzsDhSXKCYXkXTlKuDt3c3IGFTybZKTVNQZ0oLUH6Q+wFmc3ojgqTmTBF+lga reJBMEOc3d0HGrcJWT+5pwn2YuKZCj7XZZFktyRYUhs1t4j4rUnLOdTd279+hI3k80bV 7RThRAywKqCbT/aTKrIhDoNm2C6MZf+TOEC3UhL1Ol0t3Vm3pWHsjiEbXyRmCZ2ra/Pa 2G6G2HWCRPzSaPEW79O9mQAyX6IG9oQ5EQKhoYUlE1K4dTiQ3dSsZxZT9esq71c5YkvW r+wS9B8Givx3o6jzFYJt8CABwk4oq0ENTfg9MiHRnkRh0xNyLIWCYVvIcODDOxRQPdyO GFhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LpDXkMJymCkBigdAeSGEBRetKSjrJSWM6nnEjxNkcOs=; b=HCeAlyaA3NXMvIwIalmKDYQK7jzQxcG0/AfGqydIWq6mrlK4EfF0DWNMHOiPapTLct 4cZnSOlxPyFjSibiqbIiyMxw4VO7DHnCxmtuvzP7TlVE3UZkrval56VPVGcTx3M5xjAi 1V+2HsGgOvm6UA84gUqJjWK/snSY1F7PpSYkucaw1ARnSkSe0a/5taL7XxTzV1LcfetF r2YAXwjyAjlZTMQD0nUbbP/0XoJ9DtFJ76JgYw8N9DzDyakck8ks7Fw8z5CKkIylLsHn vY5t1NqffO8wnAufKzAIbk5D80VT/cADrkRjNXNueKWI/JHzVEzMEevdYd+7EzYMoHWj l2/Q== X-Gm-Message-State: APjAAAXrF8sJuT2co9hAjS9tCeW9ITARIK5z/sm3CqIBaEPatYL+yoUy iNNxDmvRwuFQzRyZqYkUsgVNgPzJoKM= X-Google-Smtp-Source: APXvYqxUqTghpaDeKoQr9pJhTaH+ZpirDQn9KSLY7+11maLTmtJwJ7cVBJL4eLRqPA3iOo1dWn+RpQ== X-Received: by 2002:a63:2842:: with SMTP id o63mr56554627pgo.317.1582582960842; Mon, 24 Feb 2020 14:22:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 05/17] target/arm: Improve ID_AA64PFR0 FP/SIMD validation Date: Mon, 24 Feb 2020 14:22:20 -0800 Message-Id: <20200224222232.13807-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224222232.13807-1-richard.henderson@linaro.org> References: <20200224222232.13807-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" When sanity checking id_aa64pfr0, use the raw FP and SIMD fields, because the values must match. Delay the test until we've finished modifying the id_aa64pfr0 register. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 23 ++++++++++++----------- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5be4c25809..f10f34b655 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1427,17 +1427,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) return; } =20 - if (arm_feature(env, ARM_FEATURE_AARCH64) && - cpu->has_vfp !=3D cpu->has_neon) { - /* - * This is an architectural requirement for AArch64; AArch32 is - * more flexible and permits VFP-no-Neon and Neon-no-VFP. - */ - error_setg(errp, - "AArch64 CPUs must have both VFP and Neon or neither"); - return; - } - if (!cpu->has_vfp) { uint64_t t; uint32_t u; @@ -1537,6 +1526,18 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) cpu->isar.mvfr0 =3D u; } =20 + if (arm_feature(env, ARM_FEATURE_AARCH64) && + FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, FP) !=3D + FIELD_EX64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, ADVSIMD)) { + /* + * This is an architectural requirement for AArch64. Not only + * both vfp and advsimd or neither, but further both must + * support fp16 or neither. + */ + error_setg(errp, "AArch64 CPUs must match VFP and NEON"); + return; + } + if (arm_feature(env, ARM_FEATURE_M) && !cpu->has_dsp) { uint32_t u; =20 --=20 2.20.1 From nobody Sun May 19 07:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582583179; cv=none; d=zohomail.com; s=zohoarc; b=GNozbrj5XNUETuVI4s0l0o+M69nqd2PJXPo5Ri4qoTs5gQRHjRH3n2ve0jCCdGLqvGOKiMO9BGJR34OXnrUcBnfwVDBnjCBQW+/Xx9Vei//KtAHrSZII3CufuJ/O2YMb3yfAiCVKo4EyXheZ77bP7yjRF9iJNHBmGwB7NJcuBrU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582583179; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=04w4nAykREQYlFaDlCPkF+ClHIRvIg4T3qLIcZORCLQ=; b=NcrHsgZ9XFZ7Rj4BOGWuimiBcgXi9kS9gH7J3l4cv9nPX95Ls/3hbtLNlC5UpgRbFTJ9q78U1ngCEvMEf8HHcW3bexTd246ZdKwTOvXCUVwXHuLmBt48WEBxQT9o9k6Xf4IZOky7Ztun9fpoVJufnjhyLrkQ4/otw06ZqCjYKvs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582583179897940.6501447648376; Mon, 24 Feb 2020 14:26:19 -0800 (PST) Received: from localhost ([::1]:45264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6MB8-0002b8-MM for importer@patchew.org; Mon, 24 Feb 2020 17:26:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37813) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6M7h-0004FX-QY for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j6M7g-0005q7-2O for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:45 -0500 Received: from mail-pg1-x543.google.com ([2607:f8b0:4864:20::543]:34555) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j6M7f-0005pV-Qw for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:44 -0500 Received: by mail-pg1-x543.google.com with SMTP id j4so5853440pgi.1 for ; Mon, 24 Feb 2020 14:22:43 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id o6sm13897097pgg.37.2020.02.24.14.22.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 14:22:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=04w4nAykREQYlFaDlCPkF+ClHIRvIg4T3qLIcZORCLQ=; b=RESOnh7ZVqABL9e9EkhNypENrNTmIKFmCDKjHRkcvufJlnIaC9RFyKDoEJFf1Smggp ZHSp1nb9lEGqnGBLq73Y9irDfXnuXHdtMPad+XEFGkD4utjPp3p+Co1jO5R37pkxmhmY 1n2d2LjG7T/OGZA9V2uOoy6YC/RJLnH1kbxK8dU9UtV4rSsyANp6vNN4oEW64CdttH07 MyIZwJbXfwT0pMB1M+uOd5dUVgFelzZBvOAMkyk7+bk0pSHvDbHE7y0lW3Gf7O7F2cbi MEGUhJT+kUlf0pCrO6X4bLOegZ+tHoUoO0424X1zVf7iqMrrEMvhhckceleTAZmOItfS ZFGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=04w4nAykREQYlFaDlCPkF+ClHIRvIg4T3qLIcZORCLQ=; b=Uwj/q6BQPRIEttvUzaJgPSvn193ULyVgtN2itYuTY9/7FeXfzwr77zzQb5UPBNdXao yBsumYCi3pN6TCf3HOlvekR9gOZXjntdaE0RQ9xeLcXUxbVzuf6tE/v449ZYQwWn0gb1 OBwE8NUg16GqpTFgHMCDANriqwGFPL5vS7goNdr8tH/toEK7oYXRTt6hcXjg6zftRyn/ qQEP5ERYE/ZUt9bQh8UC3zMCI4qJqjSzonZHkC5KJ+oYBXMFIuua6Ao2XbeWRwlXjthG c40e3rwBzSlMXbG9jVRVxHLMvnQBt0SMSMAUuUu3pHfJPdp87zaKP2tPChFqIFwqP7ch DzdQ== X-Gm-Message-State: APjAAAVAYTzlDprM9c/dtm/t3Q7K7Ga8MewrJ4DBLan7irqLWHM5WQtG usVbj7da6Mo0y+jzrcsRov4RnCYPR2U= X-Google-Smtp-Source: APXvYqxKy6234epOsW9E8YZ1XRGBdazrx2Qb1QMsg5KAAe/ZZ+zEX7myG2O9gp0PyO+Sulp0peJMWQ== X-Received: by 2002:a65:65c8:: with SMTP id y8mr25943548pgv.36.1582582962103; Mon, 24 Feb 2020 14:22:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 06/17] target/arm: Perform fpdp_v2 check first Date: Mon, 24 Feb 2020 14:22:21 -0800 Message-Id: <20200224222232.13807-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224222232.13807-1-richard.henderson@linaro.org> References: <20200224222232.13807-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 140 +++++++++++++++++---------------- 1 file changed, 71 insertions(+), 69 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index e94876c30c..ff30165045 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -200,13 +200,13 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vn | a->vd) & 0x10)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && + ((a->vm | a->vn | a->vd) & 0x10)) { return false; } =20 @@ -333,13 +333,13 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMIN= MAXNM *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vn | a->vd) & 0x10)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && + ((a->vm | a->vn | a->vd) & 0x10)) { return false; } =20 @@ -419,13 +419,13 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vd) & 0x10)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && + ((a->vm | a->vd) & 0x10)) { return false; } =20 @@ -483,12 +483,12 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 @@ -1308,12 +1308,12 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3O= pDPFn *fn, TCGv_i64 f0, f1, fd; TCGv_ptr fpst; =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) { return false; } =20 @@ -1457,12 +1457,12 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2O= pDPFn *fn, int vd, int vm) int veclen =3D s->vec_len; TCGv_i64 f0, fd; =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) { return false; } =20 @@ -1827,7 +1827,9 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp = *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { return false; } =20 @@ -1921,12 +1923,12 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_= VMOV_imm_dp *a) =20 vd =3D a->vd; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) { return false; } =20 @@ -2060,6 +2062,10 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_= dp *a) { TCGv_i64 vd, vm; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + /* Vm/M bits must be zero for the Z variant */ if (a->z && a->vm !=3D 0) { return false; @@ -2070,10 +2076,6 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_= dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2134,6 +2136,10 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_= VCVT_f64_f16 *a) TCGv_i32 tmp; TCGv_i64 vd; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_fp16_dpconv, s)) { return false; } @@ -2143,10 +2149,6 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_= VCVT_f64_f16 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2200,6 +2202,10 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_= VCVT_f16_f64 *a) TCGv_i32 tmp; TCGv_i64 vm; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_fp16_dpconv, s)) { return false; } @@ -2209,10 +2215,6 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_= VCVT_f16_f64 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2260,6 +2262,10 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRI= NTR_dp *a) TCGv_ptr fpst; TCGv_i64 tmp; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_vrint, s)) { return false; } @@ -2269,10 +2275,6 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRI= NTR_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2321,6 +2323,10 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRI= NTZ_dp *a) TCGv_i64 tmp; TCGv_i32 tcg_rmode; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_vrint, s)) { return false; } @@ -2330,10 +2336,6 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRI= NTZ_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2380,6 +2382,10 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRI= NTX_dp *a) TCGv_ptr fpst; TCGv_i64 tmp; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_vrint, s)) { return false; } @@ -2389,10 +2395,6 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRI= NTX_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2412,12 +2414,12 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT= _sp *a) TCGv_i64 vd; TCGv_i32 vm; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; } =20 @@ -2440,12 +2442,12 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT= _dp *a) TCGv_i64 vm; TCGv_i32 vd; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 @@ -2494,12 +2496,12 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_= VCVT_int_dp *a) TCGv_i64 vd; TCGv_ptr fpst; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; } =20 @@ -2530,6 +2532,10 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *= a) TCGv_i32 vd; TCGv_i64 vm; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_jscvt, s)) { return false; } @@ -2539,10 +2545,6 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *= a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2623,6 +2625,10 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_V= CVT_fix_dp *a) TCGv_ptr fpst; int frac_bits; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { return false; } @@ -2632,10 +2638,6 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_V= CVT_fix_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2723,12 +2725,12 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_= VCVT_dp_int *a) TCGv_i64 vm; TCGv_ptr fpst; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 --=20 2.20.1 From nobody Sun May 19 07:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582583142; cv=none; d=zohomail.com; s=zohoarc; b=BFh+yNMwOFdFtrjq6IDWh5HTywRs5aW72E7QbxIspZhToozTbY4VqrpZmI1SeLUfMQPqihJ7zF+QgVFtqjuEbMTr/zu7aoD7YQ9pUbDL4AFAXeDIqlVgu4v4XZbzcT2NroZEDeR2yoyBU2eUiui0OgmC4/9ZwcdAiDIbIUJR3Tc= ARC-Message-Signature: i=1; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id o6sm13897097pgg.37.2020.02.24.14.22.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 14:22:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BR6sc2PsWl2NSv+8xYHc8XwgP3dTmPaC/PPPaHkcT3I=; b=DQ2dparviTdEn1mh9O1lQXFqY3QilS/OGLcCZ+Huii0oWHWSzMo2G6iYtJircXbGPC /gAs6Dz8gir/vzxWET88fVpkmNSKc9+2luOAiZAjF0Ku+ZxAu4d6PYJwpeTPwXFh5sbL WfbVPfeBSClTLbogMwUlHYwdhKFqwxIDs79mlGZwtkLb7rU8oQkS/7vn4aqqy5Bi12jK RMKhCYFJiMk6wKsXBKcc+8aHSsbS5aUVr3WOL1zmUoexLsBHUEDkdmR3/YUp1WnIvznY wHHoF6y1K2n+o4Xn2vd+RYvHv5u7D+lA+gSZexh7+p0KLkcIlT3EpzoqEcoSlJppmiJ5 5TuQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BR6sc2PsWl2NSv+8xYHc8XwgP3dTmPaC/PPPaHkcT3I=; b=Tr10TcxxPt9iQNmKbz+BIhsCB9ReHaaqnRNCYspgRtgEKhvjOp/F28c8gGYv5QmLi4 Rf4t4JqEetsu7oyfBIXiRcpUlKQ9bF9PNSD/cd6yBdxY/RlNCh0Gyd5NcpUNf7fCb04g c/9U9A8jm8WXl0O7l7a7Mp+dGPkXkPlnxMWXNgD57a5M0kek+3QpwntZ5zQXtQsfOVWi btN92ZTsA9t+Rfxlt+qFd0frBRh9FoQvWE3EEius7Nlth9cgk9fMrNLrQ935ix5hLO8R YXSDNZ62dz3Y9aykk4u2KclPdJwJp2YASm+8Lrcn3J5XNDbxM6CxcA8Y7Ps7OwUl784p l6FQ== X-Gm-Message-State: APjAAAWclI+iAr2ASR+UpaI5no/8K9kZz7+f8uU97V0J/4L1Ui5gfSTN VvUQg3Wuq9xABM8Lz4Cp9alVYrmF61I= X-Google-Smtp-Source: APXvYqyb7t5Cgw7jnuo9osC/qJYgdzVjWov5uP2Cf+UeEWNbr6Qr0dKvubbcol54DIhUKT/nRLdClA== X-Received: by 2002:a17:902:8d83:: with SMTP id v3mr52983013plo.282.1582582963580; Mon, 24 Feb 2020 14:22:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 07/17] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Date: Mon, 24 Feb 2020 14:22:22 -0800 Message-Id: <20200224222232.13807-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224222232.13807-1-richard.henderson@linaro.org> References: <20200224222232.13807-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Sort this check to the start of a trans_* function. Merge this with any existing test for fpdp_v2. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index ff30165045..51d46f4302 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -717,7 +717,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_V= MRS *a) * VFPv2 allows access to FPSID from userspace; VFPv3 restricts * all ID registers to privileged access only. */ - if (IS_USER(s) && arm_dc_feature(s, ARM_FEATURE_VFP3)) { + if (IS_USER(s) && dc_isar_feature(aa32_fpsp_v3, s)) { return false; } ignore_vfp_enabled =3D true; @@ -746,7 +746,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_V= MRS *a) case ARM_VFP_FPINST: case ARM_VFP_FPINST2: /* Not present in VFPv3 */ - if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_VFP3)) { + if (IS_USER(s) || dc_isar_feature(aa32_fpsp_v3, s)) { return false; } break; @@ -1873,12 +1873,12 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_= VMOV_imm_sp *a) =20 vd =3D a->vd; =20 - if (!dc_isar_feature(aa32_fpshvec, s) && - (veclen !=3D 0 || s->vec_stride !=3D 0)) { + if (!dc_isar_feature(aa32_fpsp_v3, s)) { return false; } =20 - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { + if (!dc_isar_feature(aa32_fpshvec, s) && + (veclen !=3D 0 || s->vec_stride !=3D 0)) { return false; } =20 @@ -1923,7 +1923,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VM= OV_imm_dp *a) =20 vd =3D a->vd; =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + if (!dc_isar_feature(aa32_fpdp_v3, s)) { return false; } =20 @@ -1937,10 +1937,6 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_V= MOV_imm_dp *a) return false; } =20 - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2565,7 +2561,7 @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VC= VT_fix_sp *a) TCGv_ptr fpst; int frac_bits; =20 - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { + if (!dc_isar_feature(aa32_fpsp_v3, s)) { return false; } =20 @@ -2625,11 +2621,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_V= CVT_fix_dp *a) TCGv_ptr fpst; int frac_bits; =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { + if (!dc_isar_feature(aa32_fpdp_v3, s)) { return false; } =20 --=20 2.20.1 From nobody Sun May 19 07:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582583762; cv=none; d=zohomail.com; s=zohoarc; b=lZMW698l5zhRcyRQxFdo9ZXxJrZbHONDW0bdZdepWdr14L3r+9abcXBN8afK96jcRAX43s9s8CWvCizjZMz/qq+xVvKSUFTXQffpPkGH1JgM878zov0PxyueEbhFXhpLGwMKE6+PvkjN96BmrsRFnNnyqbL/b6VwYQaeE+PUOJQ= ARC-Message-Signature: i=1; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id o6sm13897097pgg.37.2020.02.24.14.22.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 14:22:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nZ29NUYH0rX/kvQeepGmU3q2/jzjoKfkqGWPwiKmojM=; b=xxvrA+ogSQK5y+8pjt/5xu+j9hsVv24loOIm+bdauHtMM2SQWn2Nq3tSXsmW6h4/Rl Fx9QkPuJqgiaNXdzImh97cao6XiPvw5Gf7F9GTDKpcaAav/lVC99oH3SBGFqWFdkpxdV bbVzoN0aRklZwTaO/TEVXdT55mxPY26ZHyc8Xz6xajt0T+8qtUBDEpuL7olNRJMKSKAD R74cgMCYhDAfCtfQ7eH3+BIeEO9xnpazBVEWhLxiWOO6cRFUL2ZebfmV1xxz9kNxyvt8 5sPxVXZBUhqSXqG8+Pry3qLsTquv6lG49B5lBx9JgPSCZEIQ5QL5mBR5Y+Co6f2x5Kx7 lSDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nZ29NUYH0rX/kvQeepGmU3q2/jzjoKfkqGWPwiKmojM=; b=oV3p01GQKvVc2lMbk8EceaMvENam4UY4k8WigIR8UQuozWfUPQ+P4kaZOta5Pb81mG iUABZPGrP3E0TAgyjjTdiziOKC3uybhSdVoGStm440IoTqLjaHi98HOII/8cIx6b3U3u 4Q3t/KvDO39tt0Qe60ysyAR3YGtsHAdbEyIk2Y/feDrrIK5BX0Dz3Ha3vEt/Gu4F0cuQ CJKE8M4O0M4z9UxsYj7OHUe6fQke14UbxTdUv/nLa8QWvjILzLOnvIwgfHMBTm9KDS8p /ovNKEFfk8T08yfSTG4D91iMUUZbRs404j0EFRSpj+boA542KK9k0B6IwBdjL6iRke5Y rNlg== X-Gm-Message-State: APjAAAWnc49pdcWms20jAJC9WcQ8WWj4rXt4tG9i5iVxue8HvGgk7tI7 f2whGle/UsYTNrAekfiN8lKjNtlICGw= X-Google-Smtp-Source: APXvYqyllfHpBWYyI0Ol06uRoeeRdNsHuQBPpn+6TQJByEebhRzNAYL/PZl4oN1SLv4oRqJIpbWGDg== X-Received: by 2002:a17:902:8b85:: with SMTP id ay5mr48009211plb.253.1582582964790; Mon, 24 Feb 2020 14:22:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 08/17] target/arm: Add missing checks for fpsp_v2 Date: Mon, 24 Feb 2020 14:22:23 -0800 Message-Id: <20200224222232.13807-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224222232.13807-1-richard.henderson@linaro.org> References: <20200224222232.13807-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-vfp.inc.c | 78 ++++++++++++++++++++++++++++++---- 1 file changed, 69 insertions(+), 9 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 51d46f4302..f88a95438f 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -555,6 +555,13 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV= _to_gp *a) int pass; uint32_t offset; =20 + /* SIZE =3D=3D 2 is a VFP instruction; otherwise NEON. */ + if (a->size =3D=3D 2 + ? !dc_isar_feature(aa32_fpsp_v2, s) + : !arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { return false; @@ -564,10 +571,6 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV= _to_gp *a) pass =3D extract32(offset, 2, 1); offset =3D extract32(offset, 0, 2) * 8; =20 - if (a->size !=3D 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -614,6 +617,13 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VM= OV_from_gp *a) int pass; uint32_t offset; =20 + /* SIZE =3D=3D 2 is a VFP instruction; otherwise NEON. */ + if (a->size =3D=3D 2 + ? !dc_isar_feature(aa32_fpsp_v2, s) + : !arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { return false; @@ -623,10 +633,6 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VM= OV_from_gp *a) pass =3D extract32(offset, 2, 1); offset =3D extract32(offset, 0, 2) * 8; =20 - if (a->size !=3D 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -700,6 +706,10 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_= VMRS *a) TCGv_i32 tmp; bool ignore_vfp_enabled =3D false; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (arm_dc_feature(s, ARM_FEATURE_M)) { /* * The only M-profile VFP vmrs/vmsr sysreg is FPSCR. @@ -844,6 +854,10 @@ static bool trans_VMOV_single(DisasContext *s, arg_VMO= V_single *a) { TCGv_i32 tmp; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -873,6 +887,10 @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV= _64_sp *a) { TCGv_i32 tmp; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + /* * VMOV between two general-purpose registers and two single precision * floating point registers @@ -908,8 +926,12 @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV= _64_dp *a) =20 /* * VMOV between two general-purpose registers and one double precision - * floating point register + * floating point register. Note that this does not require support + * for double precision arithmetic. */ + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } =20 /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { @@ -946,6 +968,10 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VL= DR_VSTR_sp *a) uint32_t offset; TCGv_i32 addr, tmp; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -977,6 +1003,11 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_V= LDR_VSTR_dp *a) TCGv_i32 addr; TCGv_i64 tmp; =20 + /* Note that this does not require support for double arithmetic. */ + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; @@ -1013,6 +1044,10 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_= VLDM_VSTM_sp *a) TCGv_i32 addr, tmp; int i, n; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + n =3D a->imm; =20 if (n =3D=3D 0 || (a->vd + n) > 32) { @@ -1086,6 +1121,11 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_= VLDM_VSTM_dp *a) TCGv_i64 tmp; int i, n; =20 + /* Note that this does not require support for double arithmetic. */ + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + n =3D a->imm >> 1; =20 if (n =3D=3D 0 || (a->vd + n) > 32 || n > 16) { @@ -1234,6 +1274,10 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3Op= SPFn *fn, TCGv_i32 f0, f1, fd; TCGv_ptr fpst; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_fpshvec, s) && (veclen !=3D 0 || s->vec_stride !=3D 0)) { return false; @@ -1388,6 +1432,10 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2Op= SPFn *fn, int vd, int vm) int veclen =3D s->vec_len; TCGv_i32 f0, fd; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_fpshvec, s) && (veclen !=3D 0 || s->vec_stride !=3D 0)) { return false; @@ -2023,6 +2071,10 @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_= sp *a) { TCGv_i32 vd, vm; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + /* Vm/M bits must be zero for the Z variant */ if (a->z && a->vm !=3D 0) { return false; @@ -2466,6 +2518,10 @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_V= CVT_int_sp *a) TCGv_i32 vm; TCGv_ptr fpst; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2684,6 +2740,10 @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_V= CVT_sp_int *a) TCGv_i32 vm; TCGv_ptr fpst; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } --=20 2.20.1 From nobody Sun May 19 07:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id o6sm13897097pgg.37.2020.02.24.14.22.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 14:22:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ABqg53SHadErlQ1KJw2EVsyG66DudT3m5ptP92s2kV4=; b=ml/LGDeM83+tA/QuI9WQvvsXX+P52t3WEQ5SAtw+bAXUiCz0nN4ReHgPEwUqPnhZsD fvaMa4fOI+ttGPyxkAZ9L1Lmrvf8zS1PcbbxL1VHrWWls1eInuHQnSTvLqjuv3VJ/z6j xEknPQQu8h1NZrIAz9KLGE92mSw1cUXs3TPPo7TxBramSMrtftYEeINKRFenVtvGrtQ3 ag2l6KyYT3IwXljfc13/ciUf7TWjY2fEQfAAmXsfiZFwCaVutE8sSFASLtWEi1hibzgz fXsfpQNt1C1TKFcdttXosEUF7SQv5UM7zM4I4khWEUSsKbbDQSICfBSyAWs4adBpF/uL +Kcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ABqg53SHadErlQ1KJw2EVsyG66DudT3m5ptP92s2kV4=; b=Wl/+dzLAELPNeJDe1FU30Hr+CwxUDVcENljyV7olbxWt1pLTva1OMxQS6ZP7pRx+iU vN26uoyeo6YBPQhZZHCkF5MYxA9U9nMCr0+D7k2kdGbzzZQjKocEu5IDQfCL4HWrsB5X 6wUHqNvTzRKZklvUIPgR1f/28g5X9cxRYJT/ZdwAXYtb/mmUdwLF7L56UfmvO3An6VoL Qsa89UKokj68SgB2UQgq7n3yT1vRgKjch8gIaS5PW6S09GXlw8pEoVPM94Xv7+eBpdTc TrtBBLltvtzG1BmFgR/hv3MZA07wPff5GpPliPG2ExlehQ5O4OVnRHPLCjKly/R/NzFY l0og== X-Gm-Message-State: APjAAAWyKTwrmmEN8reYwRAtUlFLUjvutgNW+iN5E52AgWi3bsaK2Z2j TV1nxdnrabbzZCpRW0v2c+x7pEdMBHM= X-Google-Smtp-Source: APXvYqyRh9lcxlT3hIw4otRhwLAUUnR28xRJVkiTYMMPrOoQnnKhSGxwJ2yPZb3PZakxHREoIjm88Q== X-Received: by 2002:a65:5905:: with SMTP id f5mr17972398pgu.87.1582582966092; Mon, 24 Feb 2020 14:22:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 09/17] target/arm: Replace ARM_FEATURE_VFP4 with isar_feature_aa32_simdfmac Date: Mon, 24 Feb 2020 14:22:24 -0800 Message-Id: <20200224222232.13807-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224222232.13807-1-richard.henderson@linaro.org> References: <20200224222232.13807-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" All remaining tests for VFP4 are for fused multiply-add insns. Since the MVFR1 field is used for both VFP and NEON, move its adjustment from the !has_neon block to the (!has_vfp && !has_neon) block. Test for vfp of the appropraite width alongside the test for simdfmac within translate-vfp.inc.c. Within disas_neon_data_insn, we have already tested for ARM_FEATURE_NEON. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v2: Applied Peter's fixups, plus test fpdp_v2 in trans_VFM_dp. --- target/arm/cpu.h | 12 ++++++++++++ target/arm/cpu.c | 6 +++++- target/arm/translate-vfp.inc.c | 22 ++++++++++++++++++---- target/arm/translate.c | 2 +- 4 files changed, 36 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b94d2a5ace..b29b0eddfc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3514,6 +3514,18 @@ static inline bool isar_feature_aa32_fp16_dpconv(con= st ARMISARegisters *id) return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; } =20 +/* + * Note that this ID register field covers both VFP and Neon FMAC, + * so should usually be tested in combination with some other + * check that confirms the presence of whichever of VFP or Neon is + * relevant, to avoid accidentally enabling a Neon feature on + * a VFP-no-Neon core or vice-versa. + */ +static inline bool isar_feature_aa32_simdfmac(const ARMISARegisters *id) +{ + return FIELD_EX32(id->mvfr1, MVFR1, SIMDFMAC) !=3D 0; +} + static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) { return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 1; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f10f34b655..bdcaa46b8a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1501,7 +1501,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) u =3D FIELD_DP32(u, MVFR1, SIMDINT, 0); u =3D FIELD_DP32(u, MVFR1, SIMDSP, 0); u =3D FIELD_DP32(u, MVFR1, SIMDHP, 0); - u =3D FIELD_DP32(u, MVFR1, SIMDFMAC, 0); cpu->isar.mvfr1 =3D u; =20 u =3D cpu->isar.mvfr2; @@ -1524,6 +1523,11 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) u =3D cpu->isar.mvfr0; u =3D FIELD_DP32(u, MVFR0, SIMDREG, 0); cpu->isar.mvfr0 =3D u; + + /* Despite the name, this field covers both VFP and Neon */ + u =3D cpu->isar.mvfr1; + u =3D FIELD_DP32(u, MVFR1, SIMDFMAC, 0); + cpu->isar.mvfr1 =3D u; } =20 if (arm_feature(env, ARM_FEATURE_AARCH64) && diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index f88a95438f..03ba8d7aac 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1803,11 +1803,18 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_s= p *a) =20 /* * Present in VFPv4 only. + * Note that we can't rely on the SIMDFMAC check alone, because + * in a Neon-no-VFP core that ID register field will be non-zero. + */ + if (!dc_isar_feature(aa32_simdfmac, s) || + !dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + /* * In v7A, UNPREDICTABLE with non-zero vector length/stride; from * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A. */ - if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || - (s->vec_len !=3D 0 || s->vec_stride !=3D 0)) { + if (s->vec_len !=3D 0 || s->vec_stride !=3D 0) { return false; } =20 @@ -1861,11 +1868,18 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_d= p *a) =20 /* * Present in VFPv4 only. + * Note that we can't rely on the SIMDFMAC check alone, because + * in a Neon-no-VFP core that ID register field will be non-zero. + */ + if (!dc_isar_feature(aa32_simdfmac, s) || + !dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + /* * In v7A, UNPREDICTABLE with non-zero vector length/stride; from * v8A, must UNDEF. We choose to UNDEF for both v7A and v8A. */ - if (!arm_dc_feature(s, ARM_FEATURE_VFP4) || - (s->vec_len !=3D 0 || s->vec_stride !=3D 0)) { + if (s->vec_len !=3D 0 || s->vec_stride !=3D 0) { return false; } =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 79880adaad..0489e0cdaa 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5150,7 +5150,7 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) } break; case NEON_3R_VFM_VQRDMLSH: - if (!arm_dc_feature(s, ARM_FEATURE_VFP4)) { + if (!dc_isar_feature(aa32_simdfmac, s)) { return 1; } break; --=20 2.20.1 From nobody Sun May 19 07:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582583244; cv=none; d=zohomail.com; s=zohoarc; b=XAqOyrAV1iGrUB56Z3ZxzrWRZKP/hCQ3n2RB8YPDK2KRFE5TQCEKTk/h1hJdY3yLLUFPm8Pdjj4/lFMChMHB5oOR10GjMs4s0H21rD6gJ22MpnykDB7ttdZjoFuUo+RAgMMHAVkVaLL944LWu77bqaGXW+JYr+XGu14sKCnEPTs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582583244; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aSn4NAeocUzSgV/L7ik2kDrtmTdvw88vbNjqxC4Yo9c=; b=mAjNIgNKGBtOZ/6dNnm9qRuE1/P7tHEiMsEE5H3kZkDiG6Y2iu9TzkHBD9I4zkTsjCifMmWSa4XVIegusUe8zzC5DGkAp6Oc7S0OuNaSyOOJFt7BpnSGYigg8AK5xgF6tMumh/usDKIDOK1TNUkAwKQxiynqzaQKaBOfCDgHO0I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582583244224247.1277815141342; Mon, 24 Feb 2020 14:27:24 -0800 (PST) Received: from localhost ([::1]:45288 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6MCB-000457-6N for importer@patchew.org; Mon, 24 Feb 2020 17:27:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37896) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6M7l-0004Q9-Lw for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j6M7k-0005sz-MD for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:49 -0500 Received: from mail-pf1-x442.google.com ([2607:f8b0:4864:20::442]:38331) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j6M7k-0005sg-HJ for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:48 -0500 Received: by mail-pf1-x442.google.com with SMTP id x185so6073421pfc.5 for ; Mon, 24 Feb 2020 14:22:48 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id o6sm13897097pgg.37.2020.02.24.14.22.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 14:22:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aSn4NAeocUzSgV/L7ik2kDrtmTdvw88vbNjqxC4Yo9c=; b=TBKc1TFH1MMrxxLoVXabVlAV3gqrsgo51CyXapcsrKPErDkzNFao8O+HimXPIXMkg6 mz460C2vxEDWs9gdokRZxbg+5mwHXlh8tGuh8ohO1U/AHeSH1K5Qa3iNTv6FVXtr9ulb ExI0aQ9IQj7nx9KiV6NUvd1+fNDPffQCj9XHkqQGO/On7bQ7BUnKf2TqqTqjWju8ygEo kUV9+XNmz3AyRxW+ZgZrU1qa8Yh/p9ldWDH+rS11GGfCwYGJT9ZI9X/QlrK/Gmaw05aN DRifucgRRgm473OC7VXWhcPBKSWWCcZDqqNd7hZYxBdPatYud8GxbeK56sy6EESVZ5bi sbnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aSn4NAeocUzSgV/L7ik2kDrtmTdvw88vbNjqxC4Yo9c=; b=Cw4Gsr1xlkn+8f3bBOK0qqzb6s7pNWLpwGEs13tJbNkz7CkacenyIJigwye9Ag6eNU 27gxPx+CCjMsk5uvNChQrCEJetnDtS/0ZYXqeeM/iL4VC1b9qxR3NeoFRi+HcxLjS5L0 eXMlgFymN73ylV9U5BROfPNY4dqnMewz5oh7InNVVM6G3Hc3yCBeveuuCGBCSuqW8CfV jn68mRL9CTQvOqlhxIeXOMfu6ej7Zw+/YgP1MMgZITahnghGXXwiP3/KuaKWR8enY6Te v1Hk1JtytKyPYnNJQBIDpBYJP+sfd7RsxHeHqjUcAFEiIv3puZyqBLPh6YLZQGzOu393 MjIQ== X-Gm-Message-State: APjAAAWSh/YxXlTDdbquS1k05xQ4VYcDG5Gr/5PVsMbjZd3E7XdL2FCc XL0EjRNBdO2vmgk/sef6w0sevQw44SY= X-Google-Smtp-Source: APXvYqzswr/NezFIN+VwxT9I1xoc99qaGijQEVD33SRi5OhHggPXoSPGGYAD9w/Qa7lZ3hyx+tcwqw== X-Received: by 2002:a62:1594:: with SMTP id 142mr53296303pfv.18.1582582967322; Mon, 24 Feb 2020 14:22:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 10/17] target/arm: Remove ARM_FEATURE_VFP check from disas_vfp_insn Date: Mon, 24 Feb 2020 14:22:25 -0800 Message-Id: <20200224222232.13807-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224222232.13807-1-richard.henderson@linaro.org> References: <20200224222232.13807-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We now have proper ISA checks within each trans_* function. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 0489e0cdaa..893911fca7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2652,10 +2652,6 @@ static void gen_neon_dup_high16(TCGv_i32 var) */ static int disas_vfp_insn(DisasContext *s, uint32_t insn) { - if (!arm_dc_feature(s, ARM_FEATURE_VFP)) { - return 1; - } - /* * If the decodetree decoder handles this insn it will always * emit code to either execute the insn or generate an appropriate --=20 2.20.1 From nobody Sun May 19 07:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582583264; cv=none; d=zohomail.com; s=zohoarc; b=cd9nBiNUJQKY5f0qNJMGHjL153eo2LAgiZUFyCE3Cllihp6RQ2Jq1tkfokF4x16ENZlMWcqVysA9yRkkYoPLCMPN05d7gylj33T9ITcDShAxiaBhrhVfZIC8X5wBRRlvLfRcf75qfhClGMfiOLom7xqwayqp/xaRJtpkoSryOUE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582583264; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/XrE+Up+cXUxsM0gL0c1JdFdbzGsxHOx44lIg6PgF9w=; b=WQRn6znoTC6ghpnYhB+A/QNzJwQRO70djEIE6XA8IY9o7MWWR4ZKbbWuaFbPwGk8xdyitPzpQF1S09iVkz2z5Vw5tMAdciMQjJWyMy9uXqrpueGdpAI02akaMVsOcWXqvAmoMvRhhKaL/tezfjMgAZE7q3y5eJAm/TJJ+S2DIZU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582583264151570.435582660573; Mon, 24 Feb 2020 14:27:44 -0800 (PST) Received: from localhost ([::1]:45300 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6MCV-0004fy-1K for importer@patchew.org; Mon, 24 Feb 2020 17:27:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37932) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6M7n-0004UJ-DB for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:52 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j6M7m-0005u6-5l for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:51 -0500 Received: from mail-pg1-x544.google.com ([2607:f8b0:4864:20::544]:41734) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j6M7m-0005tc-0M for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:50 -0500 Received: by mail-pg1-x544.google.com with SMTP id 70so5836646pgf.8 for ; Mon, 24 Feb 2020 14:22:49 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id o6sm13897097pgg.37.2020.02.24.14.22.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 14:22:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/XrE+Up+cXUxsM0gL0c1JdFdbzGsxHOx44lIg6PgF9w=; b=DqnWzbNxh8Dfu17ddDQn6T1OQZu7vWr0VryhkU2LOZ3wVTZveXG9VwFPACvyX+kotp luzQ7dsUURqJH7TyJ2FN3f2GeTRWagyzbhLScn88M+tTqxsOWaK1MtYglgqD5fcuMBXL lBt+Hfd8auzVoPlx62lOZK7HHNhECi3LWw+Wy75KwWRpex/bbKjlr6fWsG4im72D+yB0 Oi3hAUYfD/rG3jVK5glITd5G7LkywlFAiLTU8jPPyr6bGmRTVFEGUsyRkhlXzzyADx72 WBguXTUcEQFICZfq7KdmKtEE3hi8ZmfcU4lQDvo50Io5/5mI4LD/Nemrt/kbN5JfR3KP zgUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/XrE+Up+cXUxsM0gL0c1JdFdbzGsxHOx44lIg6PgF9w=; b=HXuWHqOZ81acdgnMavu5KOeRrlnoLq90b33O80OZvghhX57baKDBFX7kkbkwi/6ne0 NKM8heEzrAXs66eCWNYp/eI6TJlmLyC6J4k+1rPj/86dEN/LO7QJZh7LSosNymWUdB7P I/yX3LgZiRLyiKF23M8Wrs+1VYkxRl0SLEhIGzYmKtaE541wmaD2zY09i+i4TKadzUrI PJcHaM13tUYAsbxaxTwWq++cBy5xXthOEaX3c7ZLuiPJd7CPB86aj9Sm30ibhmFnfnew cwwoyNwKA5wDDBved6JskxrPsOlCiWc2OvqicyoPD5XTDGVK/jsIm0gPrGOtXZP8JayJ OWlw== X-Gm-Message-State: APjAAAUqTsewjQUPgFQ5UfRcPN5qgpiW/n2K8yJturKROL0fGCINzvLr dzrCDU5VWsgiQvy2+LU1L+7T0+nj3nE= X-Google-Smtp-Source: APXvYqwzigogDb0xYGr+ha/qjHvEmu6xH57rE2Zt3rLm8aMavqCSobdy0kx2nj40FYvNsBKIopuEpQ== X-Received: by 2002:a62:7b93:: with SMTP id w141mr55183624pfc.226.1582582968607; Mon, 24 Feb 2020 14:22:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 11/17] target/arm: Move VLLDM and VLSTM to vfp.decode Date: Mon, 24 Feb 2020 14:22:26 -0800 Message-Id: <20200224222232.13807-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224222232.13807-1-richard.henderson@linaro.org> References: <20200224222232.13807-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Now that we no longer have an early check for ARM_FEATURE_VFP, we can use the proper ISA check in trans_VLLDM_VLSTM. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v2: Fix !secure (pmm) --- target/arm/vfp.decode | 2 ++ target/arm/translate-vfp.inc.c | 39 +++++++++++++++++++++++++ target/arm/translate.c | 53 ++++++---------------------------- 3 files changed, 50 insertions(+), 44 deletions(-) diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index a67b3f29ee..592fe9e1e4 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -242,3 +242,5 @@ VCVT_sp_int ---- 1110 1.11 110 s:1 .... 1010 rz:1 1.0 = .... \ vd=3D%vd_sp vm=3D%vm_sp VCVT_dp_int ---- 1110 1.11 110 s:1 .... 1011 rz:1 1.0 .... \ vd=3D%vd_sp vm=3D%vm_dp + +VLLDM_VLSTM 1110 1100 001 l:1 rn:4 0000 1010 0000 0000 diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 03ba8d7aac..1964af3ea5 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -2828,3 +2828,42 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_V= CVT_dp_int *a) tcg_temp_free_ptr(fpst); return true; } + +/* + * Decode VLLDM and VLSTM are nonstandard because: + * * if there is no FPU then these insns must NOP in + * Secure state and UNDEF in Nonsecure state + * * if there is an FPU then these insns do not have + * the usual behaviour that vfp_access_check() provides of + * being controlled by CPACR/NSACR enable bits or the + * lazy-stacking logic. + */ +static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a) +{ + TCGv_i32 fptr; + + if (!arm_dc_feature(s, ARM_FEATURE_M) || + !arm_dc_feature(s, ARM_FEATURE_V8)) { + return false; + } + /* If not secure, UNDEF. */ + if (!s->v8m_secure) { + return false; + } + /* If no fpu, NOP. */ + if (!dc_isar_feature(aa32_vfp, s)) { + return true; + } + + fptr =3D load_reg(s, a->rn); + if (a->l) { + gen_helper_v7m_vlldm(cpu_env, fptr); + } else { + gen_helper_v7m_vlstm(cpu_env, fptr); + } + tcg_temp_free_i32(fptr); + + /* End the TB, because we have updated FP control bits */ + s->base.is_jmp =3D DISAS_UPDATE; + return true; +} diff --git a/target/arm/translate.c b/target/arm/translate.c index 893911fca7..5b7cad1ea2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10962,53 +10962,18 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) goto illegal_op; /* op0 =3D 0b11 : unallocated */ } =20 - /* - * Decode VLLDM and VLSTM first: these are nonstandard because: - * * if there is no FPU then these insns must NOP in - * Secure state and UNDEF in Nonsecure state - * * if there is an FPU then these insns do not have - * the usual behaviour that disas_vfp_insn() provides of - * being controlled by CPACR/NSACR enable bits or the - * lazy-stacking logic. - */ - if (arm_dc_feature(s, ARM_FEATURE_V8) && - (insn & 0xffa00f00) =3D=3D 0xec200a00) { - /* 0b1110_1100_0x1x_xxxx_xxxx_1010_xxxx_xxxx - * - VLLDM, VLSTM - * We choose to UNDEF if the RAZ bits are non-zero. - */ - if (!s->v8m_secure || (insn & 0x0040f0ff)) { + if (disas_vfp_insn(s, insn)) { + if (((insn >> 8) & 0xe) =3D=3D 10 && + dc_isar_feature(aa32_fpsp_v2, s)) { + /* FP, and the CPU supports it */ goto illegal_op; + } else { + /* All other insns: NOCP */ + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), + default_exception_el(s)); } - - if (arm_dc_feature(s, ARM_FEATURE_VFP)) { - uint32_t rn =3D (insn >> 16) & 0xf; - TCGv_i32 fptr =3D load_reg(s, rn); - - if (extract32(insn, 20, 1)) { - gen_helper_v7m_vlldm(cpu_env, fptr); - } else { - gen_helper_v7m_vlstm(cpu_env, fptr); - } - tcg_temp_free_i32(fptr); - - /* End the TB, because we have updated FP control bits= */ - s->base.is_jmp =3D DISAS_UPDATE; - } - break; } - if (arm_dc_feature(s, ARM_FEATURE_VFP) && - ((insn >> 8) & 0xe) =3D=3D 10) { - /* FP, and the CPU supports it */ - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } - break; - } - - /* All other insns: NOCP */ - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, syn_uncategorized= (), - default_exception_el(s)); break; } if ((insn & 0xfe000a00) =3D=3D 0xfc000800 --=20 2.20.1 From nobody Sun May 19 07:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id o6sm13897097pgg.37.2020.02.24.14.22.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 14:22:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Jm8KlY79fmi10gEwUaheKwxsBU3LYmbPeN5QBjFnnb0=; b=tF5EoHy5mkqDGJ11etcAOiB0Np57GLPUdwsPK1yz19pH0koGH/STl2Yc73VDAWUgAh NdMaFiBTz/m0AgPc41k0z+WeYCY7EoYDLsq+ttMBFy95yDu0iyl8EBY+nQ1AiBYyuWPB owt6cWmAv/x+1NU12HAuE+eaMv6RydEtWKiTi95pALW1Q3zEBPY9kkL/hJVBZHNE6Jd5 5FlAuAYCr+VouSgI+8lUb6FZCo8DP4zjcZ7w59QZBng0cUjQun7RUdcCEMOPMbLx1A9v YtnMTi3yiQTJXWJT/T2VF0kWoPmUKxPlqwL3bm4YM5b2ewvHkTf/a2N++NnCmt721GlC TVUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Jm8KlY79fmi10gEwUaheKwxsBU3LYmbPeN5QBjFnnb0=; b=RxmscznJrQEcYEYPaSag40yF7v8JP2v4dEdZr8xlHLxLyxaM6DwxgAzydS9I1zzWm8 zWcP16/ESR0NDPi2x7zCWfjsqesBhz8rnc+MsTG4fJZPJD1zFiZd1+BKMCfhjeT1d9q6 ms9hphNby7gCylFqwojUeLiwgyrT2Hq6BUjyacZAEquET7Al4d4nD8N4UjHsW37k4rKo iEGPOMs2Ca1XQCBrULObMx6yu/VCFFg+cnLFV9rjrk6O+q+UqG4gPNW78Ic2FPvuQY2a i4kUD9xVCZsg62fvWnzyixM9zlgP9rqym3uhjdlHThGdmVib/XDsGsVsl7R3OiWijn1T U1Mg== X-Gm-Message-State: APjAAAX0Bvh8kQS/LushH/M4sBIDwIveCsLuXf0PRXB0tTaLxJAC8Dfr J2eziG7PKH9NBtVi4YpuGoPT8wrYQ2s= X-Google-Smtp-Source: APXvYqzXHK7wmq7szzmDa9BJUqt40iM7rniCQefQiXXJlK6vHVoA+Wec/8IM+dH34W3/iSFAOBzKOw== X-Received: by 2002:a62:ab06:: with SMTP id p6mr29829193pff.52.1582582969821; Mon, 24 Feb 2020 14:22:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 12/17] target/arm: Move the vfp decodetree calls next to the base isa Date: Mon, 24 Feb 2020 14:22:27 -0800 Message-Id: <20200224222232.13807-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224222232.13807-1-richard.henderson@linaro.org> References: <20200224222232.13807-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Have the calls adjacent as an intermediate step toward actually merging the decodes. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v2: Fix fallthrough in disas_arm_insn vs vfp insns. --- target/arm/translate.c | 83 +++++++++++++++--------------------------- 1 file changed, 29 insertions(+), 54 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 5b7cad1ea2..6259064ea7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2646,31 +2646,6 @@ static void gen_neon_dup_high16(TCGv_i32 var) tcg_temp_free_i32(tmp); } =20 -/* - * Disassemble a VFP instruction. Returns nonzero if an error occurred - * (ie. an undefined instruction). - */ -static int disas_vfp_insn(DisasContext *s, uint32_t insn) -{ - /* - * If the decodetree decoder handles this insn it will always - * emit code to either execute the insn or generate an appropriate - * exception; so we don't need to ever return non-zero to tell - * the calling code to emit an UNDEF exception. - */ - if (extract32(insn, 28, 4) =3D=3D 0xf) { - if (disas_vfp_uncond(s, insn)) { - return 0; - } - } else { - if (disas_vfp(s, insn)) { - return 0; - } - } - /* If the decodetree decoder didn't handle this insn, it must be UNDEF= */ - return 1; -} - static inline bool use_goto_tb(DisasContext *s, target_ulong dest) { #ifndef CONFIG_USER_ONLY @@ -10778,7 +10753,9 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) ARCH(5); =20 /* Unconditional instructions. */ - if (disas_a32_uncond(s, insn)) { + /* TODO: Perhaps merge these into one decodetree output file. */ + if (disas_a32_uncond(s, insn) || + disas_vfp_uncond(s, insn)) { return; } /* fall back to legacy decoder */ @@ -10805,13 +10782,6 @@ static void disas_arm_insn(DisasContext *s, unsign= ed int insn) } return; } - if ((insn & 0x0f000e10) =3D=3D 0x0e000a00) { - /* VFP. */ - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } - return; - } if ((insn & 0x0e000f00) =3D=3D 0x0c000100) { if (arm_dc_feature(s, ARM_FEATURE_IWMMXT)) { /* iWMMXt register transfer. */ @@ -10842,7 +10812,9 @@ static void disas_arm_insn(DisasContext *s, unsigne= d int insn) arm_skip_unless(s, cond); } =20 - if (disas_a32(s, insn)) { + /* TODO: Perhaps merge these into one decodetree output file. */ + if (disas_a32(s, insn) || + disas_vfp(s, insn)) { return; } /* fall back to legacy decoder */ @@ -10852,11 +10824,10 @@ static void disas_arm_insn(DisasContext *s, unsig= ned int insn) case 0xd: case 0xe: if (((insn >> 8) & 0xe) =3D=3D 10) { - /* VFP. */ - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } - } else if (disas_coproc_insn(s, insn)) { + /* VFP, but failed disas_vfp. */ + goto illegal_op; + } + if (disas_coproc_insn(s, insn)) { /* Coprocessor. */ goto illegal_op; } @@ -10945,7 +10916,14 @@ static void disas_thumb2_insn(DisasContext *s, uin= t32_t insn) ARCH(6T2); } =20 - if (disas_t32(s, insn)) { + /* + * TODO: Perhaps merge these into one decodetree output file. + * Note disas_vfp is written for a32 with cond field in the + * top nibble. The t32 encoding requires 0xe in the top nibble. + */ + if (disas_t32(s, insn) || + disas_vfp_uncond(s, insn) || + ((insn >> 28) =3D=3D 0xe && disas_vfp(s, insn))) { return; } /* fall back to legacy decoder */ @@ -10962,17 +10940,15 @@ static void disas_thumb2_insn(DisasContext *s, ui= nt32_t insn) goto illegal_op; /* op0 =3D 0b11 : unallocated */ } =20 - if (disas_vfp_insn(s, insn)) { - if (((insn >> 8) & 0xe) =3D=3D 10 && - dc_isar_feature(aa32_fpsp_v2, s)) { - /* FP, and the CPU supports it */ - goto illegal_op; - } else { - /* All other insns: NOCP */ - gen_exception_insn(s, s->pc_curr, EXCP_NOCP, - syn_uncategorized(), - default_exception_el(s)); - } + if (((insn >> 8) & 0xe) =3D=3D 10 && + dc_isar_feature(aa32_fpsp_v2, s)) { + /* FP, and the CPU supports it */ + goto illegal_op; + } else { + /* All other insns: NOCP */ + gen_exception_insn(s, s->pc_curr, EXCP_NOCP, + syn_uncategorized(), + default_exception_el(s)); } break; } @@ -10995,9 +10971,8 @@ static void disas_thumb2_insn(DisasContext *s, uint= 32_t insn) goto illegal_op; } } else if (((insn >> 8) & 0xe) =3D=3D 10) { - if (disas_vfp_insn(s, insn)) { - goto illegal_op; - } + /* VFP, but failed disas_vfp. */ + goto illegal_op; } else { if (insn & (1 << 28)) goto illegal_op; --=20 2.20.1 From nobody Sun May 19 07:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582583326; cv=none; d=zohomail.com; s=zohoarc; b=K4bxwEHM0+V2moCWGiz+iiOcvqPAIEnOb+2A8IjU1bowYtLX9Xt22xDfrhvXHfV6P5VUD9CD9a95+PRvqQsZOGHMGlRmAKpxCw9uazGO5EFF+/zN16NjJnWlMVw/QrwahcjLoxXc+QCIupVvTN8jYmtO9FzWRJuMZND9Igwykk0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582583326; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+oOoLUU3WLw+5ICoiVu4+Hc3ZhB0R58hfDF27U8damo=; b=OIQGMU2YtG3kLa5cZWt9z6qtK78nyGfLfCGzV642Ij/lLKosYEJC1dOfRQrFicvHzgubcRjN4eHX9GHSt3T8D73LMw33P3jIBcluisN/nMUyixL642jvEznvt+Z5tmmpfVLMZjuwEJpp8ihGZIH5UNltzsXLknvOfzibMJHlmwU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582583326993177.43322603813215; Mon, 24 Feb 2020 14:28:46 -0800 (PST) Received: from localhost ([::1]:45348 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6MDV-0006T6-Gk for importer@patchew.org; Mon, 24 Feb 2020 17:28:45 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37983) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6M7q-0004cD-Dj for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:55 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j6M7p-0005wD-9i for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:54 -0500 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:42366) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j6M7p-0005va-4s for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:53 -0500 Received: by mail-pf1-x441.google.com with SMTP id 4so6063337pfz.9 for ; Mon, 24 Feb 2020 14:22:53 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id o6sm13897097pgg.37.2020.02.24.14.22.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 14:22:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+oOoLUU3WLw+5ICoiVu4+Hc3ZhB0R58hfDF27U8damo=; b=rdl7P8Hq3/Kg6rc5J+JkXLQCkrD0N+nW18ABtWYzqGWWkBGsh7eEjsudKWGDZ7ZfEY wZoQL1mW+Hc49keUzSaVOAlix7bgnO1oLscek8OrwZ32UHD6WQoIgb+ZdMIm1eXyYzbU UAa4rWrVsgHqo601t0T5xz00ihQS1EL0lCeJgC/jyJAQzcLyattgoA717oZhwROmD7Q4 tTDjkP/nIgC5ApOYGOu7JhW7323wE4rWCpGlZylwqmLrMdlWxl28SNhzcfjyff7dOvcj wMLhEU7rGOCfm1JNTy7p8quWT4edfyC1/VPbxboWZUjgZUqv4wxOIuM1XYNTe/FSWHV/ OkkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+oOoLUU3WLw+5ICoiVu4+Hc3ZhB0R58hfDF27U8damo=; b=mL0YQ1wRfHxjtG0m3dJwT/d5fONL/kNsC0MhxS/VyzLZ6+SLz9SpiwhQJcRjtVfjQB OOSZJEVSQwDBI/KS0gG5h5T89BOwNqYcg+Nj7PLZydUM0CPeM3a74RNegQ2HdEl/Hcja exmqRr4vNodd/wh5Hssb7vLGLFmLCKxP5AMBb6tnyHPLop4PzeqkHGApjf7mumb+Hvt3 RFWntUut5Al4gOD3SzYhjzdsa2Ri5iuPxDnk9IG2PGKoNj/7m9R7Iuta0gdtjvmO7sHz w95QyC4XdjqzgGYFCY73QSPBNUmWzdNMjWDriJXhkoRVjosIkgBfOACfEGamLWmP28JL N1Dg== X-Gm-Message-State: APjAAAWIAewxJFMWEphoVfdPhZsI+D0c90XqGaayUtk8Tp3+GT1ymBoS dgis1ti52NvgTEuUeDcnL7o5QRROvgI= X-Google-Smtp-Source: APXvYqzZlR4s42/tRY8RTpc3Kj66ewkh3S4EAA9jDI9FfwXMLG+N+Dg/zSpmePMT7WjdmNwysXi2cw== X-Received: by 2002:a62:1dca:: with SMTP id d193mr54769709pfd.140.1582582971891; Mon, 24 Feb 2020 14:22:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 13/17] linux-user/arm: Replace ARM_FEATURE_VFP* tests for HWCAP Date: Mon, 24 Feb 2020 14:22:28 -0800 Message-Id: <20200224222232.13807-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224222232.13807-1-richard.henderson@linaro.org> References: <20200224222232.13807-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Use isar feature tests instead of feature bit tests. Although none of QEMUs current cpus have VFPv3 without D32, replace the large comment explaining why with one line that sets ARM_HWCAP_ARM_VFPv3D16 under the correct conditions. Mirror the test sequence used in the linux kernel. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v2: Use isar_feature_aa32_vfp. --- linux-user/elfload.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index b1a895f24c..86cda127b7 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -468,22 +468,25 @@ static uint32_t get_elf_hwcap(void) =20 /* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */ GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); - GET_FEATURE(ARM_FEATURE_VFP, ARM_HWCAP_ARM_VFP); GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); - GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); - GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4); + GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE); GET_FEATURE_ID(aa32_arm_div, ARM_HWCAP_ARM_IDIVA); GET_FEATURE_ID(aa32_thumb_div, ARM_HWCAP_ARM_IDIVT); - /* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.= c. - * Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of - * ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated - * to our VFP_FP16 feature bit. - */ - GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPD32); - GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE); + GET_FEATURE_ID(aa32_vfp, ARM_HWCAP_ARM_VFP); + + if (cpu_isar_feature(aa32_fpsp_v3, cpu) || + cpu_isar_feature(aa32_fpdp_v3, cpu)) { + hwcaps |=3D ARM_HWCAP_ARM_VFPv3; + if (cpu_isar_feature(aa32_simd_r32, cpu)) { + hwcaps |=3D ARM_HWCAP_ARM_VFPD32; + } else { + hwcaps |=3D ARM_HWCAP_ARM_VFPv3D16; + } + } + GET_FEATURE_ID(aa32_simdfmac, ARM_HWCAP_ARM_VFPv4); =20 return hwcaps; } --=20 2.20.1 From nobody Sun May 19 07:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582583397; cv=none; d=zohomail.com; s=zohoarc; b=Fb2GbcEBFQDNcvDc43//NxGEMMerh1njuqlrHZXBr+Yz3UcgqKzD5whgpe/AGeStMDj9F1xJCl6Twh4H+i97I3MMQcGZa8XghWWARa8xEV0iIEJu9jZXTf/EWUAdDJMmF2W9TCIa87Rq07MAXxrF6oKZegtj5hPY/qeBihSPoVs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582583397; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Ic31+5+7BISn+IpIxJxTLFKxAz0Jem6L/fKBKMDWBDA=; b=hurtnJuJFP4LQts+zBhbO/6uDr1ckY4pVVon8hA3yBvk8r1xAVZr9F+6ijccuqhqLcNnKX0Y+NZEd5WwRTh76uFsK6VxdX5PGLhgQcb2oVsGD7krIQAu75xFIhDiuBOQgra8rPnfoMz87JdRIQUzhFC7xddh/3ObX/r1C/wzKKM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158258339743425.391256029856322; Mon, 24 Feb 2020 14:29:57 -0800 (PST) Received: from localhost ([::1]:45378 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6MEe-00008H-7t for importer@patchew.org; Mon, 24 Feb 2020 17:29:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38037) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6M7t-0004jt-9t for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j6M7r-0005xV-Cy for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:57 -0500 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:36894) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j6M7r-0005x6-5e for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:55 -0500 Received: by mail-pl1-x641.google.com with SMTP id q4so491752pls.4 for ; Mon, 24 Feb 2020 14:22:55 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id o6sm13897097pgg.37.2020.02.24.14.22.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 14:22:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ic31+5+7BISn+IpIxJxTLFKxAz0Jem6L/fKBKMDWBDA=; b=gcnxit0i8C2xmL/KuIbp4zzhY4HYBK8VuEwDghoHNUe0dzly8T3kbpPLrk/LlUiesK AqXabWKVEzIofCEpmhqNLbb1OoPDt54zsKF2nK0PbMc9a4S9kwLfnkrFCP7tW6A8I1hx kBMzE8MXWh+mPB/KwUDgItGrS4LHhsuiQX3Qr7iD6cewilGFC0M4GgyqQOrtjU/8lm6U SIvRktjx2isE3QVcOMn7syT8KAoAhBGv3Sm5RRBu0UYOKDYd8HstjyEndghnsymI5TVg HIlsQHXR0ljhmYo/0sZ1ahIqkkzShOJq1nshNc2XHmXlvpmRSm1NO9gNMp8LRRjHweL5 Cq7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ic31+5+7BISn+IpIxJxTLFKxAz0Jem6L/fKBKMDWBDA=; b=o4u3Zc7C6R8BtL9uVEnheH7RhXDhV2+GBGoi/tnrmN6SFqAKNYoSIHdOsdcPziT1/Z FnL/hI91B4WQ81VTOozunZMLCTujNGyZl2rfVF8tC4+2FeJUdWi/U8Zb3RzSfIat7tdL QvOXS/0mHaFyuWfS3I9hSFW5Td0D8k3KbhD5y1lCfNSjbf2lC39+fJJrxOAFGsAjvalT bw5Ze+V8FbSHk8ppNn6pzXamF2b752fpJNSCezWHdkvLjT/snjhJgB0NpxKuMyqyZ/dg Wcfuo0lPeRfhN1cHj2LfoF21O+sWAob/brHOl/fK+lkUn2PF+Wi/iZ/dKLG9oMc7ZLC+ q1dw== X-Gm-Message-State: APjAAAVWxsUYdmweD576cggKQ95izqzKXIwkgKNA7kkNnqhNk7ay9PJA XnIev0nIVVmtj4CDXnswfl702gagU7U= X-Google-Smtp-Source: APXvYqzxiOpK63Znt1RdOuYK8EPbkmdoKQMmUdxu57V7BWwFHTKAnAyzMXQarUHOZqSPAn5BD24uTw== X-Received: by 2002:a17:90a:654a:: with SMTP id f10mr1473976pjs.50.1582582972978; Mon, 24 Feb 2020 14:22:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 14/17] target/arm: Remove ARM_FEATURE_VFP* Date: Mon, 24 Feb 2020 14:22:29 -0800 Message-Id: <20200224222232.13807-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224222232.13807-1-richard.henderson@linaro.org> References: <20200224222232.13807-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We have converted all tests against these features to ISAR tests. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 3 --- target/arm/cpu.c | 25 ------------------------- target/arm/cpu64.c | 3 --- target/arm/kvm32.c | 5 ----- target/arm/kvm64.c | 1 - 5 files changed, 37 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b29b0eddfc..05aa9711cd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1880,7 +1880,6 @@ QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <= =3D R_V7M_CSSELR_INDEX_MASK); * mapping in linux-user/elfload.c:get_elf_hwcap(). */ enum arm_features { - ARM_FEATURE_VFP, ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */ ARM_FEATURE_XSCALE, /* Intel XScale extensions. */ ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */ @@ -1889,7 +1888,6 @@ enum arm_features { ARM_FEATURE_V7, ARM_FEATURE_THUMB2, ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */ - ARM_FEATURE_VFP3, ARM_FEATURE_NEON, ARM_FEATURE_M, /* Microcontroller profile. */ ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */ @@ -1900,7 +1898,6 @@ enum arm_features { ARM_FEATURE_V5, ARM_FEATURE_STRONGARM, ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */ - ARM_FEATURE_VFP4, /* VFPv4 (implies that NEON is v2) */ ARM_FEATURE_GENERIC_TIMER, ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */ ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=3D15 */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index bdcaa46b8a..ebff98cb36 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1208,13 +1208,6 @@ void arm_cpu_post_init(Object *obj) if (arm_feature(&cpu->env, ARM_FEATURE_M)) { set_feature(&cpu->env, ARM_FEATURE_PMSA); } - /* Similarly for the VFP feature bits */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP4)) { - set_feature(&cpu->env, ARM_FEATURE_VFP3); - } - if (arm_feature(&cpu->env, ARM_FEATURE_VFP3)) { - set_feature(&cpu->env, ARM_FEATURE_VFP); - } =20 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) || arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) { @@ -1431,10 +1424,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) uint64_t t; uint32_t u; =20 - unset_feature(env, ARM_FEATURE_VFP); - unset_feature(env, ARM_FEATURE_VFP3); - unset_feature(env, ARM_FEATURE_VFP4); - t =3D cpu->isar.id_aa64isar1; t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 0); cpu->isar.id_aa64isar1 =3D t; @@ -1866,7 +1855,6 @@ static void arm926_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,arm926"; set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); cpu->midr =3D 0x41069265; @@ -1907,7 +1895,6 @@ static void arm1026_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,arm1026"; set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_AUXCR); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); @@ -1955,7 +1942,6 @@ static void arm1136_r2_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,arm1136"; set_feature(&cpu->env, ARM_FEATURE_V6); - set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); @@ -1987,7 +1973,6 @@ static void arm1136_initfn(Object *obj) cpu->dtb_compatible =3D "arm,arm1136"; set_feature(&cpu->env, ARM_FEATURE_V6K); set_feature(&cpu->env, ARM_FEATURE_V6); - set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); @@ -2018,7 +2003,6 @@ static void arm1176_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,arm1176"; set_feature(&cpu->env, ARM_FEATURE_V6K); - set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_VAPA); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); @@ -2051,7 +2035,6 @@ static void arm11mpcore_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,arm11mpcore"; set_feature(&cpu->env, ARM_FEATURE_V6K); - set_feature(&cpu->env, ARM_FEATURE_VFP); set_feature(&cpu->env, ARM_FEATURE_VAPA); set_feature(&cpu->env, ARM_FEATURE_MPIDR); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); @@ -2117,7 +2100,6 @@ static void cortex_m4_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M); set_feature(&cpu->env, ARM_FEATURE_M_MAIN); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - set_feature(&cpu->env, ARM_FEATURE_VFP4); cpu->midr =3D 0x410fc240; /* r0p0 */ cpu->pmsav7_dregion =3D 8; cpu->isar.mvfr0 =3D 0x10110021; @@ -2148,7 +2130,6 @@ static void cortex_m7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M); set_feature(&cpu->env, ARM_FEATURE_M_MAIN); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - set_feature(&cpu->env, ARM_FEATURE_VFP4); cpu->midr =3D 0x411fc272; /* r1p2 */ cpu->pmsav7_dregion =3D 8; cpu->isar.mvfr0 =3D 0x10110221; @@ -2180,7 +2161,6 @@ static void cortex_m33_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_M_MAIN); set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - set_feature(&cpu->env, ARM_FEATURE_VFP4); cpu->midr =3D 0x410fd213; /* r0p3 */ cpu->pmsav7_dregion =3D 16; cpu->sau_sregion =3D 8; @@ -2264,7 +2244,6 @@ static void cortex_r5f_initfn(Object *obj) ARMCPU *cpu =3D ARM_CPU(obj); =20 cortex_r5_initfn(obj); - set_feature(&cpu->env, ARM_FEATURE_VFP3); cpu->isar.mvfr0 =3D 0x10110221; cpu->isar.mvfr1 =3D 0x00000011; } @@ -2283,7 +2262,6 @@ static void cortex_a8_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a8"; set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); @@ -2351,7 +2329,6 @@ static void cortex_a9_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a9"; set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_VFP3); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_EL3); @@ -2416,7 +2393,6 @@ static void cortex_a7_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a7"; set_feature(&cpu->env, ARM_FEATURE_V7VE); - set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); @@ -2462,7 +2438,6 @@ static void cortex_a15_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a15"; set_feature(&cpu->env, ARM_FEATURE_V7VE); - set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0929401a4d..5cda580231 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -102,7 +102,6 @@ static void aarch64_a57_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a57"; set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_AARCH64); @@ -156,7 +155,6 @@ static void aarch64_a53_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a53"; set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_AARCH64); @@ -210,7 +208,6 @@ static void aarch64_a72_initfn(Object *obj) =20 cpu->dtb_compatible =3D "arm,cortex-a72"; set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_VFP4); set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); set_feature(&cpu->env, ARM_FEATURE_AARCH64); diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 7981ae3bc4..f703c4fcad 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -147,7 +147,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) * bits, but a few must be tested. */ set_feature(&features, ARM_FEATURE_V7VE); - set_feature(&features, ARM_FEATURE_VFP3); set_feature(&features, ARM_FEATURE_GENERIC_TIMER); =20 if (extract32(id_pfr0, 12, 4) =3D=3D 1) { @@ -156,10 +155,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) if (extract32(ahcf->isar.mvfr1, 12, 4) =3D=3D 1) { set_feature(&features, ARM_FEATURE_NEON); } - if (extract32(ahcf->isar.mvfr1, 28, 4) =3D=3D 1) { - /* FMAC support implies VFPv4 */ - set_feature(&features, ARM_FEATURE_VFP4); - } =20 ahcf->features =3D features; =20 diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 0ad96c3500..93ba1448da 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -649,7 +649,6 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) * feature bits. */ set_feature(&features, ARM_FEATURE_V8); - set_feature(&features, ARM_FEATURE_VFP4); set_feature(&features, ARM_FEATURE_NEON); set_feature(&features, ARM_FEATURE_AARCH64); set_feature(&features, ARM_FEATURE_PMU); --=20 2.20.1 From nobody Sun May 19 07:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582583537; cv=none; d=zohomail.com; s=zohoarc; b=TcYhY075xXmguCkuzX65xWw7BpaiZY0uCRyCSF4TybSQyfcfZdtSjIOLadgAiIHAjNR0osekqKi0KJXMC1hCx1ndqJBVuAj4VLwFWkzzcwzvOzLzuWUxrm/oPg27bKaPgoSN3b39qZyPr0dUF35S9MFWUWdK1txpX1t+SH78gZs= ARC-Message-Signature: i=1; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id o6sm13897097pgg.37.2020.02.24.14.22.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 14:22:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UjJ9iZKHSouFYZlDrlpMHjdteZRncNwvhF4XGeCLWsY=; b=v6587C+nZ28pjxxCIAVJ4LI3tsgys+6pFrwhEJSb6vYV7gLZeXAHDEwUXdZe2TDkyE C4xNY32wTN5M9/i1N6MjlN+LXLR6QVt5hxks8T2YiHDinvyG3RhHHRYCcEydSbrlHUWS KNJ83G5bGZxIsu0Nq4VEGK2y4MzEwoMm2Y1TYCgfKRhw0hsPq4RMPouuL1WiEwrOaB1T mftxYmIDk0X1gxYVvu4IKeAQaIPUc8Vt8smiYXBZN7hUvyxCKtpidMZ239zaLcafk9xM PJdFAIfoW3BrHak2XsL3tSc7yGx5yeOtG7bvrmovAJI1ci8Ohvo6T2hoCrt3aCOoJKU7 PVPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UjJ9iZKHSouFYZlDrlpMHjdteZRncNwvhF4XGeCLWsY=; b=kqk4+8Ckgm386ILRCIOXKSxcf0l3G4X29pmUfhiBqB6qmePWnL2V7V4bJcNOi7Hjkm svSfJFQbelpE5Z0hRdQStD7tHHsuHHqdAPycvYobSWyIY6XgcTBCwgE5HCj9q7EheSQY EirArhYFfCEkhc83q2OaZV68GJ1IB8EB5G5Ki4xROiMxKQCE1BKWeALQ0TVpjUgMcXSx 7zvKixtGrb2vkCInHnSmyR8/RMQKx59Luv/DTX3NK6+Mj7TKYTFsVuJAyWy1alHkLk+c u3kxGfDB9pbDyEHH0SzyxwKKEeTQvvwO8KqxpsJSvYQ/6j/uZXS+Yqgrl1bF+eLYqui+ iURQ== X-Gm-Message-State: APjAAAV3uP8MX2NGWEhoL2HJphjW+CxeGcBZ3PODfFfe9dGmJAIN2uX0 GnEXlTGfzVBy6faxWosDwWmQazqDbks= X-Google-Smtp-Source: APXvYqyjY63fn3H9ciiZhl3vypKBSQZJ3UW48VZXvMc60nj1kvaiM1tZmmLUFPCbYKtAfolb2vFsiw== X-Received: by 2002:a17:90a:db0f:: with SMTP id g15mr1404254pjv.40.1582582974177; Mon, 24 Feb 2020 14:22:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 15/17] target/arm: Add formats for some vfp 2 and 3-register insns Date: Mon, 24 Feb 2020 14:22:30 -0800 Message-Id: <20200224222232.13807-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224222232.13807-1-richard.henderson@linaro.org> References: <20200224222232.13807-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Those vfp instructions without extra opcode fields can share a common @format for brevity. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/vfp.decode | 134 ++++++++++++++++-------------------------- 1 file changed, 52 insertions(+), 82 deletions(-) diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 592fe9e1e4..4f294f88be 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -46,6 +46,14 @@ =20 %vmov_imm 16:4 0:4 =20 +@vfp_dnm_s ................................ vm=3D%vm_sp vn=3D%vn_sp vd= =3D%vd_sp +@vfp_dnm_d ................................ vm=3D%vm_dp vn=3D%vn_dp vd= =3D%vd_dp + +@vfp_dm_ss ................................ vm=3D%vm_sp vd=3D%vd_sp +@vfp_dm_dd ................................ vm=3D%vm_dp vd=3D%vd_dp +@vfp_dm_ds ................................ vm=3D%vm_sp vd=3D%vd_dp +@vfp_dm_sd ................................ vm=3D%vm_dp vd=3D%vd_sp + # VMOV scalar to general-purpose register; note that this does # include some Neon cases. VMOV_to_gp ---- 1110 u:1 1. 1 .... rt:4 1011 ... 1 0000 \ @@ -66,20 +74,15 @@ VDUP ---- 1110 1 b:1 q:1 0 .... rt:4 1011 . 0 e= :1 1 0000 \ vn=3D%vn_dp =20 VMSR_VMRS ---- 1110 111 l:1 reg:4 rt:4 1010 0001 0000 -VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 \ - vn=3D%vn_sp +VMOV_single ---- 1110 000 l:1 .... rt:4 1010 . 001 0000 vn=3D%vn_sp =20 -VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... \ - vm=3D%vm_sp -VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... \ - vm=3D%vm_dp +VMOV_64_sp ---- 1100 010 op:1 rt2:4 rt:4 1010 00.1 .... vm=3D%vm_sp +VMOV_64_dp ---- 1100 010 op:1 rt2:4 rt:4 1011 00.1 .... vm=3D%vm_dp =20 # Note that the half-precision variants of VLDR and VSTR are # not part of this decodetree at all because they have bits [9:8] =3D=3D 0= b01 -VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 \ - vd=3D%vd_sp -VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 \ - vd=3D%vd_dp +VLDR_VSTR_sp ---- 1101 u:1 .0 l:1 rn:4 .... 1010 imm:8 vd=3D%vd_sp +VLDR_VSTR_dp ---- 1101 u:1 .0 l:1 rn:4 .... 1011 imm:8 vd=3D%vd_dp =20 # We split the load/store multiple up into two patterns to avoid # overlap with other insns in the "Advanced SIMD load/store and 64-bit mov= e" @@ -100,50 +103,32 @@ VLDM_VSTM_dp ---- 1101 0.1 l:1 rn:4 .... 1011 imm:8 \ vd=3D%vd_dp p=3D1 u=3D0 w=3D1 =20 # 3-register VFP data-processing; bits [23,21:20,6] identify the operation. -VMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VMLA_sp ---- 1110 0.00 .... .... 1010 .0.0 .... @vfp_dnm_s +VMLA_dp ---- 1110 0.00 .... .... 1011 .0.0 .... @vfp_dnm_d =20 -VMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VMLS_sp ---- 1110 0.00 .... .... 1010 .1.0 .... @vfp_dnm_s +VMLS_dp ---- 1110 0.00 .... .... 1011 .1.0 .... @vfp_dnm_d =20 -VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VNMLS_sp ---- 1110 0.01 .... .... 1010 .0.0 .... @vfp_dnm_s +VNMLS_dp ---- 1110 0.01 .... .... 1011 .0.0 .... @vfp_dnm_d =20 -VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VNMLA_sp ---- 1110 0.01 .... .... 1010 .1.0 .... @vfp_dnm_s +VNMLA_dp ---- 1110 0.01 .... .... 1011 .1.0 .... @vfp_dnm_d =20 -VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VMUL_sp ---- 1110 0.10 .... .... 1010 .0.0 .... @vfp_dnm_s +VMUL_dp ---- 1110 0.10 .... .... 1011 .0.0 .... @vfp_dnm_d =20 -VNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VNMUL_sp ---- 1110 0.10 .... .... 1010 .1.0 .... @vfp_dnm_s +VNMUL_dp ---- 1110 0.10 .... .... 1011 .1.0 .... @vfp_dnm_d =20 -VADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VADD_sp ---- 1110 0.11 .... .... 1010 .0.0 .... @vfp_dnm_s +VADD_dp ---- 1110 0.11 .... .... 1011 .0.0 .... @vfp_dnm_d =20 -VSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VSUB_sp ---- 1110 0.11 .... .... 1010 .1.0 .... @vfp_dnm_s +VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... @vfp_dnm_d =20 -VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp -VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp +VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s +VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d =20 VFM_sp ---- 1110 1.01 .... .... 1010 . o2:1 . 0 .... \ vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp o1=3D1 @@ -159,25 +144,17 @@ VMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \ VMOV_imm_dp ---- 1110 1.11 .... .... 1011 0000 .... \ vd=3D%vd_dp imm=3D%vmov_imm =20 -VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... \ - vd=3D%vd_sp vm=3D%vm_sp -VMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... \ - vd=3D%vd_dp vm=3D%vm_dp +VMOV_reg_sp ---- 1110 1.11 0000 .... 1010 01.0 .... @vfp_dm_ss +VMOV_reg_dp ---- 1110 1.11 0000 .... 1011 01.0 .... @vfp_dm_dd =20 -VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... \ - vd=3D%vd_sp vm=3D%vm_sp -VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... \ - vd=3D%vd_dp vm=3D%vm_dp +VABS_sp ---- 1110 1.11 0000 .... 1010 11.0 .... @vfp_dm_ss +VABS_dp ---- 1110 1.11 0000 .... 1011 11.0 .... @vfp_dm_dd =20 -VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... \ - vd=3D%vd_sp vm=3D%vm_sp -VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... \ - vd=3D%vd_dp vm=3D%vm_dp +VNEG_sp ---- 1110 1.11 0001 .... 1010 01.0 .... @vfp_dm_ss +VNEG_dp ---- 1110 1.11 0001 .... 1011 01.0 .... @vfp_dm_dd =20 -VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... \ - vd=3D%vd_sp vm=3D%vm_sp -VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... \ - vd=3D%vd_dp vm=3D%vm_dp +VSQRT_sp ---- 1110 1.11 0001 .... 1010 11.0 .... @vfp_dm_ss +VSQRT_dp ---- 1110 1.11 0001 .... 1011 11.0 .... @vfp_dm_dd =20 VCMP_sp ---- 1110 1.11 010 z:1 .... 1010 e:1 1.0 .... \ vd=3D%vd_sp vm=3D%vm_sp @@ -190,32 +167,26 @@ VCVT_f32_f16 ---- 1110 1.11 0010 .... 1010 t:1 1.0 ..= .. \ VCVT_f64_f16 ---- 1110 1.11 0010 .... 1011 t:1 1.0 .... \ vd=3D%vd_dp vm=3D%vm_sp =20 -# VCVTB and VCVTT to f16: Vd format is always vd_sp; Vm format depends on = size bit +# VCVTB and VCVTT to f16: Vd format is always vd_sp; +# Vm format depends on size bit VCVT_f16_f32 ---- 1110 1.11 0011 .... 1010 t:1 1.0 .... \ vd=3D%vd_sp vm=3D%vm_sp VCVT_f16_f64 ---- 1110 1.11 0011 .... 1011 t:1 1.0 .... \ vd=3D%vd_sp vm=3D%vm_dp =20 -VRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... \ - vd=3D%vd_sp vm=3D%vm_sp -VRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... \ - vd=3D%vd_dp vm=3D%vm_dp +VRINTR_sp ---- 1110 1.11 0110 .... 1010 01.0 .... @vfp_dm_ss +VRINTR_dp ---- 1110 1.11 0110 .... 1011 01.0 .... @vfp_dm_dd =20 -VRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... \ - vd=3D%vd_sp vm=3D%vm_sp -VRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... \ - vd=3D%vd_dp vm=3D%vm_dp +VRINTZ_sp ---- 1110 1.11 0110 .... 1010 11.0 .... @vfp_dm_ss +VRINTZ_dp ---- 1110 1.11 0110 .... 1011 11.0 .... @vfp_dm_dd =20 -VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... \ - vd=3D%vd_sp vm=3D%vm_sp -VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... \ - vd=3D%vd_dp vm=3D%vm_dp +VRINTX_sp ---- 1110 1.11 0111 .... 1010 01.0 .... @vfp_dm_ss +VRINTX_dp ---- 1110 1.11 0111 .... 1011 01.0 .... @vfp_dm_dd =20 -# VCVT between single and double: Vm precision depends on size; Vd is its = reverse -VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... \ - vd=3D%vd_dp vm=3D%vm_sp -VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... \ - vd=3D%vd_sp vm=3D%vm_dp +# VCVT between single and double: +# Vm precision depends on size; Vd is its reverse +VCVT_sp ---- 1110 1.11 0111 .... 1010 11.0 .... @vfp_dm_ds +VCVT_dp ---- 1110 1.11 0111 .... 1011 11.0 .... @vfp_dm_sd =20 # VCVT from integer to floating point: Vm always single; Vd depends on size VCVT_int_sp ---- 1110 1.11 1000 .... 1010 s:1 1.0 .... \ @@ -224,8 +195,7 @@ VCVT_int_dp ---- 1110 1.11 1000 .... 1011 s:1 1.0 ....= \ vd=3D%vd_dp vm=3D%vm_sp =20 # VJCVT is always dp to sp -VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... \ - vd=3D%vd_sp vm=3D%vm_dp +VJCVT ---- 1110 1.11 1001 .... 1011 11.0 .... @vfp_dm_sd =20 # VCVT between floating-point and fixed-point. The immediate value # is in the same format as a Vm single-precision register number. --=20 2.20.1 From nobody Sun May 19 07:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582583374; cv=none; d=zohomail.com; s=zohoarc; b=JiHul27wtpTxdEN3/jrH72seLOfkfoLKyRc9iRlGWCo6qg9Jjo1w3ltu+lNQ0DWTZRRwmx2zBUOMDg6Dlh2SsL7aDvhQ/5slz6wJFWeWPTxkXI8VlGzXUfwLr8cTbyPrCuJPgnf103BgDJsrbDAihpaRLKMC7QyvW0x1Pu0eBh8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582583374; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=N2dqLxgdt7qGgHLw+VE7Z3TBav3OjyXi4mGQvjqJ7no=; b=F/w2NI+OV2g45tlKoOlMiOxkdmQcub5em1u+EcHqEeBOFSFrtrekeRNkJkzcOxdp7E8A91U5tIQsKxe0G/7jwtyEqetvekW9+VMCg5LZ/7br5kUox/4i1iSh/rDNvPP4ppdQUcuKvk+6WwDALtsLFOyzQvU/vGI7GPg8iEdUr8Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582583374642415.2861634977211; Mon, 24 Feb 2020 14:29:34 -0800 (PST) Received: from localhost ([::1]:45368 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6MEH-0008El-AN for importer@patchew.org; Mon, 24 Feb 2020 17:29:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38059) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6M7u-0004lz-6c for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:59 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j6M7s-0005yf-Uu for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:58 -0500 Received: from mail-pj1-x1041.google.com ([2607:f8b0:4864:20::1041]:34224) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j6M7s-0005yJ-PI for qemu-devel@nongnu.org; Mon, 24 Feb 2020 17:22:56 -0500 Received: by mail-pj1-x1041.google.com with SMTP id f2so320041pjq.1 for ; Mon, 24 Feb 2020 14:22:56 -0800 (PST) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id o6sm13897097pgg.37.2020.02.24.14.22.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 14:22:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=N2dqLxgdt7qGgHLw+VE7Z3TBav3OjyXi4mGQvjqJ7no=; b=dHF8Q9QAoA5L8xBMfhYW2OB4bDW1HYNPABGNrIYqYAG9fRvqaMdPbdjSCfeElQEpQy PwCiAAwsvjKtQ+3h0B0tP+eINa904zjIyQS61S53tcPJzYG34vjzfhgXPiveG9siUzGG DsK1Wz1XoSVZVWxXU+WOkbMXiOb4L0wmW8XestPSjCD4mNMxNQZPR4Xt2VKp1wtzYiPV NpQhAqncAKVGABN3DLqYIXbcAF0yGrb8pRON8JDmBnXFSxAvAST+BAetVXmttlwLsF0T oraing11oa0ncQMSbXq5/27Y1/jYfHP+Xl15hvb2h4zU3i9/RdL7V0Pe2N+Y9fgdnSeZ 5KDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N2dqLxgdt7qGgHLw+VE7Z3TBav3OjyXi4mGQvjqJ7no=; b=hmXhnCQsxw7h8zeybwEpZqZaJX3fQFmVyRq5aYKeM1WDP+5IFQ6UA008updt2/rsC/ 01NythYBOzd1GeFQKgbi5UWv+3uUTxlU1KqR1GIWWHhQGg1qCaSXVTOc0l1mOiK7cEWa tqsDSw+T9J021L+uYzYsd6IeJUWzitPFTIi2jbPbpP2OF165xXCCUVpTaNgvnLK5rYSk F85vhY/ENtyR0pXbvPtFTiiNTUkQuC5xUSmmU1srllm0kwOjh1tn3rfN8qveFy1I5CUz wiYwZutfWMDH9HW2Gzqm+c62xnDJJiz1hvnzoop1hMjcj4g6UkETtX7Vrd9M7MIe9yrw FwJw== X-Gm-Message-State: APjAAAV1q4vWsxlJc4wGtvrUfmW6MGzb84nRYIxUVE/H7FBsCofO5vo7 gM/IeHxhdOlYbAtvfnqXXaR1GPt+wEk= X-Google-Smtp-Source: APXvYqwQHolY16JPMYvm/XiQA0Pb4sHKf6Eu1WC73tpmslS7U5qCI/Wmd0hTmX8z0urWh5LgJKgvXw== X-Received: by 2002:a17:90a:36af:: with SMTP id t44mr1414093pjb.25.1582582975279; Mon, 24 Feb 2020 14:22:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 16/17] target/arm: Split VFM decode Date: Mon, 24 Feb 2020 14:22:31 -0800 Message-Id: <20200224222232.13807-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224222232.13807-1-richard.henderson@linaro.org> References: <20200224222232.13807-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Passing the raw o1 and o2 fields from the manual is less instructive than it might be. Do the full decode and let the trans_* functions pass in booleans to a helper. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/vfp.decode | 17 +++++------ target/arm/translate-vfp.inc.c | 52 ++++++++++++++++++++++++++++++---- 2 files changed, 55 insertions(+), 14 deletions(-) diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode index 4f294f88be..5fd70f975a 100644 --- a/target/arm/vfp.decode +++ b/target/arm/vfp.decode @@ -130,14 +130,15 @@ VSUB_dp ---- 1110 0.11 .... .... 1011 .1.0 .... = @vfp_dnm_d VDIV_sp ---- 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s VDIV_dp ---- 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d =20 -VFM_sp ---- 1110 1.01 .... .... 1010 . o2:1 . 0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp o1=3D1 -VFM_dp ---- 1110 1.01 .... .... 1011 . o2:1 . 0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp o1=3D1 -VFM_sp ---- 1110 1.10 .... .... 1010 . o2:1 . 0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp o1=3D2 -VFM_dp ---- 1110 1.10 .... .... 1011 . o2:1 . 0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp o1=3D2 +VFMA_sp ---- 1110 1.10 .... .... 1010 .0. 0 .... @vfp_dnm_s +VFMS_sp ---- 1110 1.10 .... .... 1010 .1. 0 .... @vfp_dnm_s +VFNMA_sp ---- 1110 1.01 .... .... 1010 .0. 0 .... @vfp_dnm_s +VFNMS_sp ---- 1110 1.01 .... .... 1010 .1. 0 .... @vfp_dnm_s + +VFMA_dp ---- 1110 1.10 .... .... 1011 .0.0 .... @vfp_dnm_d +VFMS_dp ---- 1110 1.10 .... .... 1011 .1.0 .... @vfp_dnm_d +VFNMA_dp ---- 1110 1.01 .... .... 1011 .0.0 .... @vfp_dnm_d +VFNMS_dp ---- 1110 1.01 .... .... 1011 .1.0 .... @vfp_dnm_d =20 VMOV_imm_sp ---- 1110 1.11 .... .... 1010 0000 .... \ vd=3D%vd_sp imm=3D%vmov_imm diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 1964af3ea5..41aa67c133 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -1784,7 +1784,7 @@ static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_d= p *a) return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, fals= e); } =20 -static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a) +static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool ne= g_d) { /* * VFNMA : fd =3D muladd(-fd, fn, fm) @@ -1828,12 +1828,12 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_s= p *a) =20 neon_load_reg32(vn, a->vn); neon_load_reg32(vm, a->vm); - if (a->o2) { + if (neg_n) { /* VFNMS, VFMS */ gen_helper_vfp_negs(vn, vn); } neon_load_reg32(vd, a->vd); - if (a->o1 & 1) { + if (neg_d) { /* VFNMA, VFNMS */ gen_helper_vfp_negs(vd, vd); } @@ -1849,7 +1849,27 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp= *a) return true; } =20 -static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp *a) +static bool trans_VFMA_sp(DisasContext *s, arg_VFMA_sp *a) +{ + return do_vfm_sp(s, a, false, false); +} + +static bool trans_VFMS_sp(DisasContext *s, arg_VFMS_sp *a) +{ + return do_vfm_sp(s, a, true, false); +} + +static bool trans_VFNMA_sp(DisasContext *s, arg_VFNMA_sp *a) +{ + return do_vfm_sp(s, a, false, true); +} + +static bool trans_VFNMS_sp(DisasContext *s, arg_VFNMS_sp *a) +{ + return do_vfm_sp(s, a, true, true); +} + +static bool do_vfm_dp(DisasContext *s, arg_VFMA_dp *a, bool neg_n, bool ne= g_d) { /* * VFNMA : fd =3D muladd(-fd, fn, fm) @@ -1905,12 +1925,12 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_d= p *a) =20 neon_load_reg64(vn, a->vn); neon_load_reg64(vm, a->vm); - if (a->o2) { + if (neg_n) { /* VFNMS, VFMS */ gen_helper_vfp_negd(vn, vn); } neon_load_reg64(vd, a->vd); - if (a->o1 & 1) { + if (neg_d) { /* VFNMA, VFNMS */ gen_helper_vfp_negd(vd, vd); } @@ -1926,6 +1946,26 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp= *a) return true; } =20 +static bool trans_VFMA_dp(DisasContext *s, arg_VFMA_dp *a) +{ + return do_vfm_dp(s, a, false, false); +} + +static bool trans_VFMS_dp(DisasContext *s, arg_VFMS_dp *a) +{ + return do_vfm_dp(s, a, true, false); +} + +static bool trans_VFNMA_dp(DisasContext *s, arg_VFNMA_dp *a) +{ + return do_vfm_dp(s, a, false, true); +} + +static bool trans_VFNMS_dp(DisasContext *s, arg_VFNMS_dp *a) +{ + return do_vfm_dp(s, a, true, true); +} + static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a) { uint32_t delta_d =3D 0; --=20 2.20.1 From nobody Sun May 19 07:16:25 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582583446; cv=none; d=zohomail.com; s=zohoarc; b=IS4c1ed8lwnbr7/LrpvsuPurhpmTk9ZTwa06HiW8qC/ctqAVJGaZ+0mnoGD+ZD7CLxlhZLMltz9M7OZSG3Iqh22sOxES64MDKLb8QfydBK1iuY1+zbtzwnyaXkAdtmUKk+hCoZlvYxhGgGQOfdi9S17ZsHM7xZr0QY4qstRolgk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582583446; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id o6sm13897097pgg.37.2020.02.24.14.22.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 14:22:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NtGab2HLNp8uF7NgRHRNjel2MNsIDKcBiKBTctaOBVU=; b=iQKbjljPuxbGNNgKNsXt6A8vQsPZeMQ6t0A/1omR+FMYdp6gH6ymirmemstaOOBQ2i mSvR53Eeo717IJ30DBt4YVBmg2w/S5gRZ0kWUImGOyPp2z14cXRjxIF0hELBUuFkFVae jdr0vLr2hLkwbkX9nqcahPOQbXLBCXwV472O1Ux7Ad71QDgfNUeCkkxBSTq/v1kkhskQ t/gAY366vjLW4cwxfY+tbPLekF15AG4h95KJtSL8cl6k3CXY+HDEkun6xIqYSVU6jMlz ohrvbBrYTOmpyU/a6BCvL0mPBKU7xat2KxWeDb2QEJlUdPNfz3ybK6NewtrreHlgjnzD M1RA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NtGab2HLNp8uF7NgRHRNjel2MNsIDKcBiKBTctaOBVU=; b=HYVtA3F7NbLwHnQIDkZJOn7OHCzoa707UiCj90W5P3fdRrkP+EYZWNfKJVVXqZIu5s 79ERUpzYq305LeLGuxHX1XBF040YePbNgvfX2ucvZMtfigLim57fXAlre+DaA3wS4DES 0MF6hhfVyEJH9wdbZyXgShxWZ7kvI+ZVhVLxnuRTSte2mk9CkNcuFoamqUm0QVyZ086Y O6n5dQxOcdfgeUvHH4efOiZOCYNklXXo2OtxugoMSRtPW4XIaKjVTHGxGdrYAW92VqH1 96gReBTcmNTiijNt75938JlFGaDYl7e+DQ6lGJ3SzgWXigG0UHkA+Ctgajsa4Fnu/5QM cg9Q== X-Gm-Message-State: APjAAAXR8LuzUV11dMJa8clTZwtXf47/w78kWSKr+EqYvCzjMxZwEEsE M7CMRkAN8JISHyXPO4xe6/YyjseoGc0= X-Google-Smtp-Source: APXvYqxw8xSNAVXhhe7+++PHWyTKRhtODp2XznOM40aRaBleWX/iwjgsSmKH3tRyJZfU2lqTtBSdxQ== X-Received: by 2002:a63:3085:: with SMTP id w127mr16713345pgw.176.1582582976686; Mon, 24 Feb 2020 14:22:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 17/17] target/arm: Split VMINMAXNM decode Date: Mon, 24 Feb 2020 14:22:32 -0800 Message-Id: <20200224222232.13807-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224222232.13807-1-richard.henderson@linaro.org> References: <20200224222232.13807-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Passing the raw op field from the manual is less instructive than it might be. Do the full decode and use the existing helpers to perform the expansion. Since these are v8 insns, VECLEN+VECSTRIDE are already RES0. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/vfp-uncond.decode | 12 ++-- target/arm/translate-vfp.inc.c | 109 +++++++++++---------------------- 2 files changed, 44 insertions(+), 77 deletions(-) diff --git a/target/arm/vfp-uncond.decode b/target/arm/vfp-uncond.decode index 5af1f2ee66..34ca164266 100644 --- a/target/arm/vfp-uncond.decode +++ b/target/arm/vfp-uncond.decode @@ -41,15 +41,19 @@ %vd_dp 22:1 12:4 %vd_sp 12:4 22:1 =20 +@vfp_dnm_s ................................ vm=3D%vm_sp vn=3D%vn_sp vd= =3D%vd_sp +@vfp_dnm_d ................................ vm=3D%vm_dp vn=3D%vn_dp vd= =3D%vd_dp + VSEL 1111 1110 0. cc:2 .... .... 1010 .0.0 .... \ vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp dp=3D0 VSEL 1111 1110 0. cc:2 .... .... 1011 .0.0 .... \ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp dp=3D1 =20 -VMINMAXNM 1111 1110 1.00 .... .... 1010 . op:1 .0 .... \ - vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_sp dp=3D0 -VMINMAXNM 1111 1110 1.00 .... .... 1011 . op:1 .0 .... \ - vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp dp=3D1 +VMAXNM_sp 1111 1110 1.00 .... .... 1010 .0.0 .... @vfp_dnm_s +VMINNM_sp 1111 1110 1.00 .... .... 1010 .1.0 .... @vfp_dnm_s + +VMAXNM_dp 1111 1110 1.00 .... .... 1011 .0.0 .... @vfp_dnm_d +VMINNM_dp 1111 1110 1.00 .... .... 1011 .1.0 .... @vfp_dnm_d =20 VRINT 1111 1110 1.11 10 rm:2 .... 1010 01.0 .... \ vm=3D%vm_sp vd=3D%vd_sp dp=3D0 diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 41aa67c133..b087bbd812 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -322,79 +322,6 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) return true; } =20 -static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a) -{ - uint32_t rd, rn, rm; - bool dp =3D a->dp; - bool vmin =3D a->op; - TCGv_ptr fpst; - - if (!dc_isar_feature(aa32_vminmaxnm, s)) { - return false; - } - - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vn | a->vd) & 0x10)) { - return false; - } - - rd =3D a->vd; - rn =3D a->vn; - rm =3D a->vm; - - if (!vfp_access_check(s)) { - return true; - } - - fpst =3D get_fpstatus_ptr(0); - - if (dp) { - TCGv_i64 frn, frm, dest; - - frn =3D tcg_temp_new_i64(); - frm =3D tcg_temp_new_i64(); - dest =3D tcg_temp_new_i64(); - - neon_load_reg64(frn, rn); - neon_load_reg64(frm, rm); - if (vmin) { - gen_helper_vfp_minnumd(dest, frn, frm, fpst); - } else { - gen_helper_vfp_maxnumd(dest, frn, frm, fpst); - } - neon_store_reg64(dest, rd); - tcg_temp_free_i64(frn); - tcg_temp_free_i64(frm); - tcg_temp_free_i64(dest); - } else { - TCGv_i32 frn, frm, dest; - - frn =3D tcg_temp_new_i32(); - frm =3D tcg_temp_new_i32(); - dest =3D tcg_temp_new_i32(); - - neon_load_reg32(frn, rn); - neon_load_reg32(frm, rm); - if (vmin) { - gen_helper_vfp_minnums(dest, frn, frm, fpst); - } else { - gen_helper_vfp_maxnums(dest, frn, frm, fpst); - } - neon_store_reg32(dest, rd); - tcg_temp_free_i32(frn); - tcg_temp_free_i32(frm); - tcg_temp_free_i32(dest); - } - - tcg_temp_free_ptr(fpst); - return true; -} - /* * Table for converting the most common AArch32 encoding of * rounding mode to arm_fprounding order (which matches the @@ -1784,6 +1711,42 @@ static bool trans_VDIV_dp(DisasContext *s, arg_VDIV_= dp *a) return do_vfp_3op_dp(s, gen_helper_vfp_divd, a->vd, a->vn, a->vm, fals= e); } =20 +static bool trans_VMINNM_sp(DisasContext *s, arg_VMINNM_sp *a) +{ + if (!dc_isar_feature(aa32_vminmaxnm, s)) { + return false; + } + return do_vfp_3op_sp(s, gen_helper_vfp_minnums, + a->vd, a->vn, a->vm, false); +} + +static bool trans_VMAXNM_sp(DisasContext *s, arg_VMAXNM_sp *a) +{ + if (!dc_isar_feature(aa32_vminmaxnm, s)) { + return false; + } + return do_vfp_3op_sp(s, gen_helper_vfp_maxnums, + a->vd, a->vn, a->vm, false); +} + +static bool trans_VMINNM_dp(DisasContext *s, arg_VMINNM_dp *a) +{ + if (!dc_isar_feature(aa32_vminmaxnm, s)) { + return false; + } + return do_vfp_3op_dp(s, gen_helper_vfp_minnumd, + a->vd, a->vn, a->vm, false); +} + +static bool trans_VMAXNM_dp(DisasContext *s, arg_VMAXNM_dp *a) +{ + if (!dc_isar_feature(aa32_vminmaxnm, s)) { + return false; + } + return do_vfp_3op_dp(s, gen_helper_vfp_maxnumd, + a->vd, a->vn, a->vm, false); +} + static bool do_vfm_sp(DisasContext *s, arg_VFMA_sp *a, bool neg_n, bool ne= g_d) { /* --=20 2.20.1