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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b10sm60652wmj.48.2020.02.24.09.28.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 09:28:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xt89LcM9ze1qIRUu4N9M7G6GazhAHzUjaeGNd8hA1Qw=; b=CsiggA9y1aMksChk9cGaaPM3PIN6a+nQmBT0VBtbes4aKoRlUdrVO48kbysSyhlY1D QEhA6nf0tJmmr0E+fENB2YPSYx9R3gNeupdlIqh6FSRY2Hc/TGuktSoQuZmdEXc63PJa vbpaaPqy390mRPs7rutiU/tRVRmX7NsftJaZon2vUR+cbzyQ5W9eebFILM0nF1ZrLPlq TR2T7X+XnyDiCCanMApIrhau7GAMS8ou5MhH1dF8iSLtosUhCsmtf43CK58sxUs62/fR uXVrVdOsg7UbZeIO6QEEwI0sL1dkQtLC/lz3RR8YcF2LZreMrFNdEOYcSUM6BGsTG27X +1Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xt89LcM9ze1qIRUu4N9M7G6GazhAHzUjaeGNd8hA1Qw=; b=IdPAqP8SkN/yzj4hcDIsO6+K1zAPcFbusrDWeSbUofWa90lxFzkI8+vk4CriSGgqte NJqSi2tsYCBBjN5rLAC91JQhFSAxZc+VPeDysPda0co61SgGdmwmEf7mIY6JDbot+eDB ZliU7nl9w5xc2wg2YDqLYNVQesCwKBAE146ZhcQ4nh/F3KCOqhibrNo5PoiQiy0dODzn J44bDCes9RdlVlBmkzMBI4wmEnk48NWXpIXZG9pgtA65xTojGMJY/GE2/3dgmr1OfIee qMXH5BsMZdHywBqbqzlTR+KsOvVwo8EPllKlhIsld7UzmD3VK7IjkxHSf02ghSjvMNVS Wf7Q== X-Gm-Message-State: APjAAAXsKs5hELoQHyiFq7X65yLyQ5T5bP9T048wKX3XyrhJPRoTVNpM wBbBv2zT7+MW7ngHHVZORYVCkA== X-Google-Smtp-Source: APXvYqyIdItPwoz5nhQt3qI4qaJp3/NEC6S4Y8nIFq6+XvibBELOynudPQCRMkwZSRugB8nnJoPNUQ== X-Received: by 2002:adf:f1d0:: with SMTP id z16mr66106225wro.209.1582565329629; Mon, 24 Feb 2020 09:28:49 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/3] target/arm: Fix wrong use of FIELD_EX32 on ID_AA64DFR0 Date: Mon, 24 Feb 2020 17:28:44 +0000 Message-Id: <20200224172846.13053-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224172846.13053-1-peter.maydell@linaro.org> References: <20200224172846.13053-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::436 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We missed an instance of using FIELD_EX32 on a 64-bit ID register, in isar_feature_aa64_pmu_8_4(). Fix it. Signed-off-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 65171cb30ee..b647d8df916 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3723,8 +3723,8 @@ static inline bool isar_feature_aa64_pmu_8_1(const AR= MISARegisters *id) =20 static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) { - return FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 5 && - FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 5 && + FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 /* --=20 2.20.1 From nobody Thu Nov 13 19:24:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582565477; cv=none; d=zohomail.com; s=zohoarc; b=LZmvSC648WqYW4W48z5xhUUAJ+7ioJtr+PqIbrh/EXQi1q42S7FUGm4m26z/k2spPhVY62hFhpxdfptBo9nzmEofjSHtUVDGbSjBY2+eBrveAV+VQQ916WGggqyb9HtQZWft68RLRfmPI/HJNCCtDXWxOQ5Ccipztkmbaoj8x3g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582565477; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DK7oKAzyJ4Djvafrz6mvkwM3Ek9AWufxp8NykRFUZZE=; b=cOGI91lyd2lrn4ZOXVNr5PdU+Xie1QsmCoixF2pn1ROH/Az173+qPRp0dgDR4SGFn5G98BwYzIu6Dd3MJBDZKH03Gq9xG/bvh0G9dRadwNwhO+wIKOi3zcdkSoBkLJVme3uPuZwoKFxIGC464G6C4UmA8AWa9HNfB4VmhYMQaeA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582565477166170.48911433535977; Mon, 24 Feb 2020 09:31:17 -0800 (PST) Received: from localhost ([::1]:40064 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6HZb-0001nj-Ty for importer@patchew.org; Mon, 24 Feb 2020 12:31:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:50826) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6HXJ-00076D-4P for qemu-devel@nongnu.org; Mon, 24 Feb 2020 12:28:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j6HXI-0001UD-0a for qemu-devel@nongnu.org; Mon, 24 Feb 2020 12:28:53 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:40308) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j6HXH-0001TS-QD for qemu-devel@nongnu.org; Mon, 24 Feb 2020 12:28:51 -0500 Received: by mail-wr1-x444.google.com with SMTP id t3so11355548wru.7 for ; Mon, 24 Feb 2020 09:28:51 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id b10sm60652wmj.48.2020.02.24.09.28.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 09:28:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DK7oKAzyJ4Djvafrz6mvkwM3Ek9AWufxp8NykRFUZZE=; b=Vp6/CIG9WifltWxxPSpbAgFXijs/FbF98l3TjNzT8K6J7geUMOmeLTCeh86aQG2kUh Nn3iHqdFOna1HaP1EO9uKn1eqQ/ULiJ9FtF2PowuqJLJYVVLiAxJ+6K7CxN5SEvDRZJm o/Ml/hZkwFg3G8TrctrR0XbK7fpxGzpi2nKvZhAdGpxdkj3KuW3ALl6MK8420ujNeP5P Hx+LD4gzJ/1pIEzlZt3picTvqDtEfOVJl4Ncdn+F1W9xm3B8M/+BHukYDeoCWRNWkq2g QW595VLum6mq9hPnQlgv9X7D5S79nhieTuQ3G8LV35W3aLn2hLVB3ViOQ2DNc3SM9sZX i2uA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DK7oKAzyJ4Djvafrz6mvkwM3Ek9AWufxp8NykRFUZZE=; b=HMIe7ybZr2SeFv9JHKUmbdLSzmxsOePnerVtsI2iOStgSpdCeOQJs4jkMBjc5lYK2s V0ZKpAT+92gvM6P+w/i6vrjCeKsbvdTIXDcAEdOQ4jf8hTpZd8P44TFsB3Q/zKS+e7yz Enx8XVltFcROs9JNNTq9K5ivGhD70ci8jbOL5QOcxojThtwMC1qiCCwm9pKRL6C6gz3t S61QwB1yifV+0Tx0lgqKdR3rT+KAurjhbFACqoA/i0IrdMnrrVkOZZ4h8zfch4AmCr7s 4q4nbwe9EbQxkwu6wBvCN8hYo471ScsrAdmGlLZvUHcFUGSZCgofIXQ0mAPQqPzkrQ3/ 8avA== X-Gm-Message-State: APjAAAXexTTzEjtikhzxvwOGeecXOSP+JwJo6FJo/3Kk/Rfp9ImRAnU5 sIh+K/BIqX7nWjEK9GS+dKSApw== X-Google-Smtp-Source: APXvYqxz2HwnU/WdgSwzWRB9K8aWUKPWVBnVsRYw2616MjbXpupWdxL1HCNH8jsO5JgeuMrdPighMg== X-Received: by 2002:a05:6000:1251:: with SMTP id j17mr71572254wrx.210.1582565330856; Mon, 24 Feb 2020 09:28:50 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/3] target/arm: Implement v8.3-RCPC Date: Mon, 24 Feb 2020 17:28:45 +0000 Message-Id: <20200224172846.13053-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224172846.13053-1-peter.maydell@linaro.org> References: <20200224172846.13053-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The v8.3-RCPC extension implements three new load instructions which provide slightly weaker consistency guarantees than the existing load-acquire operations. For QEMU we choose to simply implement them with a full LDAQ barrier. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 5 +++++ linux-user/elfload.c | 1 + target/arm/cpu64.c | 1 + target/arm/translate-a64.c | 24 ++++++++++++++++++++++++ 4 files changed, 31 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b647d8df916..59b467a44bf 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3727,6 +3727,11 @@ static inline bool isar_feature_aa64_pmu_8_4(const A= RMISARegisters *id) FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 +static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) !=3D 0; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index b1a895f24ce..a0ffbc8861d 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -658,6 +658,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP); + GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC); =20 return hwcaps; } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 0929401a4dd..59b7c574e35 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -657,6 +657,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 1); /* ARMv8.3-RCPC */ cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64pfr0; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 596bf4cf734..7a066fb7cb2 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3142,6 +3142,8 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, int rs =3D extract32(insn, 16, 5); int rn =3D extract32(insn, 5, 5); int o3_opc =3D extract32(insn, 12, 4); + bool r =3D extract32(insn, 22, 1); + bool a =3D extract32(insn, 23, 1); TCGv_i64 tcg_rs, clean_addr; AtomicThreeOpFn *fn; =20 @@ -3177,6 +3179,13 @@ static void disas_ldst_atomic(DisasContext *s, uint3= 2_t insn, case 010: /* SWP */ fn =3D tcg_gen_atomic_xchg_i64; break; + case 014: /* LDAPR, LDAPRH, LDAPRB */ + if (!dc_isar_feature(aa64_rcpc_8_3, s) || + rs !=3D 31 || a !=3D 1 || r !=3D 0) { + unallocated_encoding(s); + return; + } + break; default: unallocated_encoding(s); return; @@ -3186,6 +3195,21 @@ static void disas_ldst_atomic(DisasContext *s, uint3= 2_t insn, gen_check_sp_alignment(s); } clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + + if (o3_opc =3D=3D 014) { + /* + * LDAPR* are a special case because they are a simple load, not a + * fetch-and-do-something op. + * The architectural consistency requirements here are weaker than + * full load-acquire (we only need "load-acquire processor consist= ent"), + * but we choose to implement them as full LDAQ. + */ + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, + true, rt, disas_ldst_compute_iss_sf(size, false, 0), tru= e); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + return; + } + tcg_rs =3D read_cpu_reg(s, rs, true); =20 if (o3_opc =3D=3D 1) { /* LDCLR */ --=20 2.20.1 From nobody Thu Nov 13 19:24:55 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582565509; cv=none; d=zohomail.com; s=zohoarc; b=djjva3xdiwHfbLHWds1q6hFkHH66nyl27buLG6wiPrYDgTVTntoa3m6gGI+3FeKFZUXLiBUoGVk3jc9Ul2Uj8MMp0Mdc2xY1Y1kVZqIl5Oc6GAv5sPXPTHSjYXE8TefEUA2+uq1rc6YoWpYrGp7tUxFlVG+reSx9WIoDc8oMqqo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id b10sm60652wmj.48.2020.02.24.09.28.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Feb 2020 09:28:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=92NgpQrkiwXdLR6m9f4lwlJDB0/iL3FAcGfJeJ1OSeE=; b=eRGTvVPOKpadiRddVdAc/39vwvj6JekugnDNMGfclSgPzh/JORPl5pVLqlUGde/zW/ 1foac1DRdTahagmA/lsdLjhrYeGOvRjMuBSd99o9rFcKxI4zbiQUTvAoDzqvbpTwHygr lYto+cLhlMWRw+eKXazRcpRLiPJ/vXiNK3Q1aaic79KUOyQYt2Mb/iF5LEJB2QucBHEs xv0aPBXmm2PZqNGKmbwKvrOrcL8JCoNsjz9Iu9qBcySVnRfHTxqHVAq6WK0s9s236efZ vgVj06dlNZGrZG+bdURdOb5RsVWl8sy+kU4Hd/sn+vVsO+L6JEe7vMTWZs3YrBz4Stlq 14Bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=92NgpQrkiwXdLR6m9f4lwlJDB0/iL3FAcGfJeJ1OSeE=; b=mJygJMJlyUm9Yaqi73t2MpY2v6ulQGng//9Oa1/ERLV+WN+OHd5JktMtPdVn35cMqL LC6Vn22qL3G8Sj0pMNPrqs41R4y6KFScv8pRbptBJ+YgHCjPY6X1H2uqbOQa4sC7qM2d doQHIwi/0BhlzUydRse6P6Yfpsem9Nu9WTEysIy/+LlVyXa9nKzaOQUlEBAhaadSKcxI T5RiVM7gWxp09sawGIbqoIfrLMp/mYvxz5NZiQvDpsEXt2iTZR1zI2vI1iM5iPcv99/D ctNWtS9d8Hi+VWp/m9aIP+CKCeW9XoIJQlt+Gkv8T6s0IdzCDgq9vQvtQ/wC/SqvcsiY QO+w== X-Gm-Message-State: APjAAAWHrmXzQFbi9mH6W0JKS7MrhFMUoHra7ik+BCYE2XOIi9k/LGI8 TiDl6gH+0TwBI3JNCIcrsw/hJw== X-Google-Smtp-Source: APXvYqydGn7bgVRxuppmvoieZldTdgGlGSbqIYMNArR+SW59/eWWLZDezokGHToEnV6VOuTI9xWizg== X-Received: by 2002:a5d:4750:: with SMTP id o16mr67016309wrs.91.1582565332099; Mon, 24 Feb 2020 09:28:52 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/3] target/arm: Implement v8.4-RCPC Date: Mon, 24 Feb 2020 17:28:46 +0000 Message-Id: <20200224172846.13053-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200224172846.13053-1-peter.maydell@linaro.org> References: <20200224172846.13053-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The v8.4-RCPC extension implements some new instructions: * LDAPUR, LDAPURB, LDAPURH, LDAPRSB, LDAPRSH, LDAPRSW * STLUR, STLURB, STLURH These are all in a new subgroup of encodings that sits below the top-level "Loads and Stores" group in the Arm ARM. The STLUR* instructions have standard store-release semantics; the LDAPUR* have Load-AcquirePC semantics, but (as with LDAPR*) we choose to implement them as the slightly stronger Load-Acquire. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 5 +++ linux-user/elfload.c | 1 + target/arm/cpu64.c | 2 +- target/arm/translate-a64.c | 90 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 97 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 59b467a44bf..3ce453f1e01 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3732,6 +3732,11 @@ static inline bool isar_feature_aa64_rcpc_8_3(const = ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) !=3D 0; } =20 +static inline bool isar_feature_aa64_rcpc_8_4(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) >=3D 2; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index a0ffbc8861d..94ec3dcab8f 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -659,6 +659,7 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP); GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC); + GET_FEATURE_ID(aa64_rcpc_8_4, ARM_HWCAP_A64_ILRCPC); =20 return hwcaps; } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 59b7c574e35..6aace57e4e2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -657,7 +657,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 1); /* ARMv8.3-RCPC */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64pfr0; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7a066fb7cb2..579180af0a9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -3283,6 +3283,88 @@ static void disas_ldst_pac(DisasContext *s, uint32_t= insn, } } =20 +/* + * LDAPR/STLR (unscaled immediate) + * + * 31 30 24 22 21 12 10 5 0 + * +------+-------------+-----+---+--------+-----+----+-----+ + * | size | 0 1 1 0 0 1 | opc | 0 | imm9 | 0 0 | Rn | Rt | + * +------+-------------+-----+---+--------+-----+----+-----+ + * + * Rt: source or destination register + * Rn: base register + * imm9: unscaled immediate offset + * opc: 00: STLUR*, 01/10/11: various LDAPUR* + * size: size of load/store + */ +static void disas_ldst_ldapr_stlr(DisasContext *s, uint32_t insn) +{ + int rt =3D extract32(insn, 0, 5); + int rn =3D extract32(insn, 5, 5); + int offset =3D sextract32(insn, 12, 9); + int opc =3D extract32(insn, 22, 2); + int size =3D extract32(insn, 30, 2); + TCGv_i64 clean_addr, dirty_addr; + bool is_store =3D false; + bool is_signed =3D false; + bool extend =3D false; + bool iss_sf; + + if (!dc_isar_feature(aa64_rcpc_8_4, s)) { + unallocated_encoding(s); + return; + } + + switch (opc) { + case 0: /* STLURB */ + is_store =3D true; + break; + case 1: /* LDAPUR* */ + break; + case 2: /* LDAPURS* 64-bit variant */ + if (size =3D=3D 3) { + unallocated_encoding(s); + return; + } + is_signed =3D true; + break; + case 3: /* LDAPURS* 32-bit variant */ + if (size > 1) { + unallocated_encoding(s); + return; + } + is_signed =3D true; + extend =3D true; /* zero-extend 32->64 after signed load */ + break; + default: + g_assert_not_reached(); + } + + iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); + + if (rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + + dirty_addr =3D read_cpu_reg_sp(s, rn, 1); + tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); + clean_addr =3D clean_data_tbi(s, dirty_addr); + + if (is_store) { + /* Store-Release semantics */ + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); + do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, iss_sf, t= rue); + } else { + /* + * Load-AcquirePC semantics; we implement as the slightly more + * restrictive Load-Acquire. + */ + do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, is_signed, extend, + true, rt, iss_sf, true); + tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); + } +} + /* Load/store register (all forms) */ static void disas_ldst_reg(DisasContext *s, uint32_t insn) { @@ -3634,6 +3716,14 @@ static void disas_ldst(DisasContext *s, uint32_t ins= n) case 0x0d: /* AdvSIMD load/store single structure */ disas_ldst_single_struct(s, insn); break; + case 0x19: /* LDAPR/STLR (unscaled immediate) */ + if (extract32(insn, 10, 2) !=3D 0 || + extract32(insn, 21, 1) !=3D 0) { + unallocated_encoding(s); + break; + } + disas_ldst_ldapr_stlr(s, insn); + break; default: unallocated_encoding(s); break; --=20 2.20.1