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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=MIWznLdnWE1pFMfHWxMiE6FxWKUgvMpAlD3wW7jfjds=; b=is/PFaW8zGweogkPvLVDAlK23Sq+QlNGBClHztcIvNP/nwuxVe1PJDMHuqLXXB+Bai ur1hX3zM8jm4Lv79tHysw78gzr8vt/lrhh9yrbVWCtbIpu44hLczkGv64ssk1/9osPj1 oQjz4Wg5Ysg2qTt0RVbV0JpVgq1O0k1t9k0xluME8s0Alb4Xc9m6U9NNkAfd90SsNgKP kSeWxFFikZwLnBA5sBTWfRpn56vL3uaQqJUsOP7Tgz8NL7Kn70Jmd+x4eFU5WEN4kinL yu69krCbBZmm+FoEt3EQQ+yY5f1ogfqVqtAJPO9B4b3YsUN8oAxTeXawyssi255EDflU l3/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MIWznLdnWE1pFMfHWxMiE6FxWKUgvMpAlD3wW7jfjds=; b=MobHtLO6gl2Xz+3iMO0CjjbNvfwXPreGmfwzYQp9LuWgHLsd2IsKCW9sbCvIefle6G fFnIy4COYGhY+xpKS9sUz1TJJ1mIx+CN0PFxcTcQxgjdBTRZarj+tQq1U4L4TrkajTAf d9dWxyWa7IiJLf1jXzbiWGUkENzQqLY/51mn6uQVQZiaEJpO8LnoqD8oRPbGRc2yg41K tLK9YXBipyPGrTWc2Ru86Ltn7Z3F26uuFggrlBYRd4Z9ZL55w+k7Feyupg3Ur7zr/G6X y53vgpGdcw/TgewrVeBvKF6X9MPEh0Myc7dfIInOczQgpd7rwN1GCBrnEaydrxQVQptw r4BA== X-Gm-Message-State: APjAAAUM/DLaXyKeUBAjK/RFHPj0CacoeTgUi3Brg+UGscqXKlBest6Z +MsyeNNNW2lX5Y2KIY6YPAK/UvvqsJ1BwQ== X-Google-Smtp-Source: APXvYqyjWXtgfwSpxOjyHl4sJfhL37PvL/N4KL60vpe57In8ttnzC6wigYBj/zibd9TK1yu10+61Lg== X-Received: by 2002:a1c:7712:: with SMTP id t18mr3982364wmi.32.1582290521168; Fri, 21 Feb 2020 05:08:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 48/52] target/arm: Rename isar_feature_aa32_fpdp_v2 Date: Fri, 21 Feb 2020 13:07:36 +0000 Message-Id: <20200221130740.7583-49-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson The old name, isar_feature_aa32_fpdp, does not reflect that the test includes VFPv2. We will introduce further feature tests for VFPv3. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200214181547.21408-7-richard.henderson@linaro.org [PMM: fixed grammar in commit message] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 4 ++-- target/arm/translate-vfp.inc.c | 40 +++++++++++++++++----------------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5a62586dd29..1e2aae276bf 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3467,9 +3467,9 @@ static inline bool isar_feature_aa32_fpshvec(const AR= MISARegisters *id) return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; } =20 -static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id) +static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) { - /* Return true if CPU supports double precision floating point */ + /* Return true if CPU supports double precision floating point, VFPv2 = */ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; } =20 diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index ba46e2557a1..e94876c30ca 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -206,7 +206,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -339,7 +339,7 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMA= XNM *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -425,7 +425,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -488,7 +488,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1313,7 +1313,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpD= PFn *fn, return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1462,7 +1462,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpD= PFn *fn, int vd, int vm) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1827,7 +1827,7 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp = *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1926,7 +1926,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VM= OV_imm_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2070,7 +2070,7 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_d= p *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2143,7 +2143,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_V= CVT_f64_f16 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2209,7 +2209,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_V= CVT_f16_f64 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2269,7 +2269,7 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRIN= TR_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2330,7 +2330,7 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRIN= TZ_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2389,7 +2389,7 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRIN= TX_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2417,7 +2417,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_s= p *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2445,7 +2445,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_d= p *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2499,7 +2499,7 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VC= VT_int_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2539,7 +2539,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2632,7 +2632,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VC= VT_fix_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2728,7 +2728,7 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VC= VT_dp_int *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 --=20 2.20.1