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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XOZCmV/LRRvs4SHMu0PR/HJGYRQoHyJpDUcGa+N8A1M=; b=isA+TSRJrhE5N3Gn0g1afjqJK1oVlwqvlAvqwOje/33xFzxM7ffnwMLivtkYUglIHH g29jhUnUqsxSsM39tBfE90jyhWj/WlpIMzrZKl5f3g3EnAWt9Xj/a9xp+KGsM7hFzIpx FQPJ1EV1iz0pcJkSPisRLkI/UgK7knwhnlOX1DiRPLXN9ggkYOBOvuQeGORdOvYyREKv 2qu/+yAd3BeMp7VwmRxSin2wIzpqNei+y6dW1Rn098tDMmu41rpHVqXrgmv3L8EiiBXE SS4CTmFbUpu9894Zhi5aFD/6AwNyxfgulP8e/hSea0eevLFc5qHhKaRV/39eaeu2A12I wWdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XOZCmV/LRRvs4SHMu0PR/HJGYRQoHyJpDUcGa+N8A1M=; b=eU0/OwnWEspL0ZMVZKkYPUFeUhYDGKhF0oikfICRhOUUuxpiuukxENe0ObVSz+M9D1 Wbc8KHqj6p019m5y58xJU1hlVuEvC3xno9ZQK2QojmOPd9Tf6xDHL2vcRUX8UFVNNEsG 93tmTsqVq6kypGSoxgJCCnrz5w2pxtVcCs+RjJDRWtF6690LHFPyf7/axPQWCoQV7WWN KT8ex5X/mSogZd3jtv6CcFDmGi+qmtXAxossYOO0oN0rRZiDJr6Oi1PgyCTLm9Z89RaF EpV0A1ff/QGA2a3m2gEwXDqJ6d+rc0tC62Cp88qEPVAA5hVmRQPhlEXMZzwpYnPeaaTq ASww== X-Gm-Message-State: APjAAAVjOOEbq8EopgGNH+usk/pixY/uFjnG3ZYJ1rlA2WslmjecR/H7 dyDnZoJq5lg4JlOURo28ErMUKVY+2QuDmQ== X-Google-Smtp-Source: APXvYqx9kRK75/VCGAm/UsL8eY4aF860uIm5SFFKgnRzwFcESiyzGluw7BPNpDLCPuiIufDVJE+M6g== X-Received: by 2002:a1c:2089:: with SMTP id g131mr3621569wmg.63.1582290519919; Fri, 21 Feb 2020 05:08:39 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 47/52] target/arm: Add isar_feature_aa32_simd_r16 Date: Fri, 21 Feb 2020 13:07:35 +0000 Message-Id: <20200221130740.7583-48-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32b X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use this in the places that were checking ARM_FEATURE_VFP, and are obviously testing for the existance of the register set as opposed to testing for some particular instruction extension. Signed-off-by: Richard Henderson Message-id: 20200214181547.21408-6-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 6 ++++++ hw/intc/armv7m_nvic.c | 20 ++++++++++---------- linux-user/arm/signal.c | 4 ++-- target/arm/arch_dump.c | 11 ++++++----- target/arm/cpu.c | 8 ++++---- target/arm/helper.c | 4 ++-- target/arm/m_helper.c | 11 ++++++----- target/arm/machine.c | 3 +-- 8 files changed, 37 insertions(+), 30 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 65171cb30ee..5a62586dd29 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3450,6 +3450,12 @@ static inline bool isar_feature_aa32_fp16_arith(cons= t ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) =3D=3D 1; } =20 +static inline bool isar_feature_aa32_simd_r16(const ARMISARegisters *id) +{ + /* Return true if D0-D15 are implemented */ + return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; +} + static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) { /* Return true if D16-D31 are implemented */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 22a43e49847..78cde4ed237 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1262,12 +1262,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) case 0xd84: /* CSSELR */ return cpu->env.v7m.csselr[attrs.secure]; case 0xd88: /* CPACR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_simd_r16, cpu)) { return 0; } return cpu->env.v7m.cpacr[attrs.secure]; case 0xd8c: /* NSACR */ - if (!attrs.secure || !arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!attrs.secure || !cpu_isar_feature(aa32_simd_r16, cpu)) { return 0; } return cpu->env.v7m.nsacr; @@ -1417,7 +1417,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) } return cpu->env.v7m.sfar; case 0xf34: /* FPCCR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_simd_r16, cpu)) { return 0; } if (attrs.secure) { @@ -1444,12 +1444,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) return value; } case 0xf38: /* FPCAR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_simd_r16, cpu)) { return 0; } return cpu->env.v7m.fpcar[attrs.secure]; case 0xf3c: /* FPDSCR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_simd_r16, cpu)) { return 0; } return cpu->env.v7m.fpdscr[attrs.secure]; @@ -1711,13 +1711,13 @@ static void nvic_writel(NVICState *s, uint32_t offs= et, uint32_t value, } break; case 0xd88: /* CPACR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, cpu)) { /* We implement only the Floating Point extension's CP10/CP11 = */ cpu->env.v7m.cpacr[attrs.secure] =3D value & (0xf << 20); } break; case 0xd8c: /* NSACR */ - if (attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (attrs.secure && cpu_isar_feature(aa32_simd_r16, cpu)) { /* We implement only the Floating Point extension's CP10/CP11 = */ cpu->env.v7m.nsacr =3D value & (3 << 10); } @@ -1951,7 +1951,7 @@ static void nvic_writel(NVICState *s, uint32_t offset= , uint32_t value, break; } case 0xf34: /* FPCCR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, cpu)) { /* Not all bits here are banked. */ uint32_t fpccr_s; =20 @@ -2005,13 +2005,13 @@ static void nvic_writel(NVICState *s, uint32_t offs= et, uint32_t value, } break; case 0xf38: /* FPCAR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, cpu)) { value &=3D ~7; cpu->env.v7m.fpcar[attrs.secure] =3D value; } break; case 0xf3c: /* FPDSCR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, cpu)) { value &=3D 0x07c00000; cpu->env.v7m.fpdscr[attrs.secure] =3D value; } diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c index b0e753801b6..2871a7cc21d 100644 --- a/linux-user/arm/signal.c +++ b/linux-user/arm/signal.c @@ -346,7 +346,7 @@ static void setup_sigframe_v2(struct target_ucontext_v2= *uc, setup_sigcontext(&uc->tuc_mcontext, env, set->sig[0]); /* Save coprocessor signal frame. */ regspace =3D uc->tuc_regspace; - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, env_archcpu(env))) { regspace =3D setup_sigframe_v2_vfp(regspace, env); } if (arm_feature(env, ARM_FEATURE_IWMMXT)) { @@ -671,7 +671,7 @@ static int do_sigframe_return_v2(CPUARMState *env, =20 /* Restore coprocessor signal frame */ regspace =3D uc->tuc_regspace; - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, env_archcpu(env))) { regspace =3D restore_sigframe_v2_vfp(env, regspace); if (!regspace) { return 1; diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 2345dec3c2c..a5a4f4e1f8f 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -363,9 +363,11 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, = CPUState *cs, int cpuid, void *opaque) { struct arm_note note; - CPUARMState *env =3D &ARM_CPU(cs)->env; + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; DumpState *s =3D opaque; - int ret, i, fpvalid =3D !!arm_feature(env, ARM_FEATURE_VFP); + int ret, i; + bool fpvalid =3D cpu_isar_feature(aa32_simd_r16, cpu); =20 arm_note_init(¬e, s, "CORE", 5, NT_PRSTATUS, sizeof(note.prstatus)); =20 @@ -444,7 +446,6 @@ int cpu_get_dump_info(ArchDumpInfo *info, ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) { ARMCPU *cpu =3D ARM_CPU(first_cpu); - CPUARMState *env =3D &cpu->env; size_t note_size; =20 if (class =3D=3D ELFCLASS64) { @@ -452,12 +453,12 @@ ssize_t cpu_get_note_size(int class, int machine, int= nr_cpus) note_size +=3D AARCH64_PRFPREG_NOTE_SIZE; #ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_sve, cpu)) { - note_size +=3D AARCH64_SVE_NOTE_SIZE(env); + note_size +=3D AARCH64_SVE_NOTE_SIZE(&cpu->env); } #endif } else { note_size =3D ARM_PRSTATUS_NOTE_SIZE; - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, cpu)) { note_size +=3D ARM_VFP_NOTE_SIZE; } } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2eadf4dcb8b..d5a75c265ac 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -293,7 +293,7 @@ static void arm_cpu_reset(CPUState *s) env->v7m.ccr[M_REG_S] |=3D R_V7M_CCR_UNALIGN_TRP_MASK; } =20 - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, cpu)) { env->v7m.fpccr[M_REG_NS] =3D R_V7M_FPCCR_ASPEN_MASK; env->v7m.fpccr[M_REG_S] =3D R_V7M_FPCCR_ASPEN_MASK | R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; @@ -1011,7 +1011,7 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f,= int flags) int numvfpregs =3D 0; if (cpu_isar_feature(aa32_simd_r32, cpu)) { numvfpregs =3D 32; - } else if (arm_feature(env, ARM_FEATURE_VFP)) { + } else if (cpu_isar_feature(aa32_simd_r16, cpu)) { numvfpregs =3D 16; } for (i =3D 0; i < numvfpregs; i++) { @@ -1260,7 +1260,7 @@ void arm_cpu_post_init(Object *obj) * KVM does not currently allow us to lie to the guest about its * ID/feature registers, so the guest always sees what the host has. */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, cpu)) { cpu->has_vfp =3D true; if (!kvm_enabled()) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_propert= y); @@ -1636,7 +1636,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * We rely on no XScale CPU having VFP so we can use the same bits in = the * TB flags field for VECSTRIDE and XSCALE_CPAR. */ - assert(!(arm_feature(env, ARM_FEATURE_VFP) && + assert(!(cpu_isar_feature(aa32_simd_r16, cpu) && arm_feature(env, ARM_FEATURE_XSCALE))); =20 if (arm_feature(env, ARM_FEATURE_V7) && diff --git a/target/arm/helper.c b/target/arm/helper.c index 79db169e046..402f9ffab9b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -894,7 +894,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. * TRCDIS [28] is RAZ/WI since we do not implement a trace macroce= ll. */ - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, env_archcpu(env))) { /* VFP coprocessor: cp10 & cp11 [23:20] */ mask |=3D (1 << 31) | (1 << 30) | (0xf << 20); =20 @@ -7814,7 +7814,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 35, "arm-vfp3.xml", 0); - } else if (arm_feature(env, ARM_FEATURE_VFP)) { + } else if (cpu_isar_feature(aa32_simd_r16, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 19, "arm-vfp.xml", 0); } diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 33d414a684b..c0249702212 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -738,7 +738,8 @@ static uint32_t v7m_integrity_sig(CPUARMState *env, uin= t32_t lr) */ uint32_t sig =3D 0xfefa125a; =20 - if (!arm_feature(env, ARM_FEATURE_VFP) || (lr & R_V7M_EXCRET_FTYPE_MAS= K)) { + if (!cpu_isar_feature(aa32_simd_r16, env_archcpu(env)) + || (lr & R_V7M_EXCRET_FTYPE_MASK)) { sig |=3D 1; } return sig; @@ -841,7 +842,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t l= r, bool dotailchain, =20 if (dotailchain) { /* Sanitize LR FType and PREFIX bits */ - if (!arm_feature(env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_simd_r16, cpu)) { lr |=3D R_V7M_EXCRET_FTYPE_MASK; } lr =3D deposit32(lr, 24, 8, 0xff); @@ -1373,7 +1374,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) =20 ftype =3D excret & R_V7M_EXCRET_FTYPE_MASK; =20 - if (!arm_feature(env, ARM_FEATURE_VFP) && !ftype) { + if (!ftype && !cpu_isar_feature(aa32_simd_r16, cpu)) { qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception= " "exit PC value 0x%" PRIx32 " is UNPREDICTABLE " "if FPU not present\n", @@ -2450,7 +2451,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskr= eg, uint32_t val) * SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 =3D=3D 0, * RES0 if the FPU is not present, and is stored in the S bank */ - if (arm_feature(env, ARM_FEATURE_VFP) && + if (cpu_isar_feature(aa32_simd_r16, env_archcpu(env)) && extract32(env->v7m.nsacr, 10, 1)) { env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_FPCA_MASK; env->v7m.control[M_REG_S] |=3D val & R_V7M_CONTROL_FPCA_MA= SK; @@ -2565,7 +2566,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskr= eg, uint32_t val) env->v7m.control[env->v7m.secure] &=3D ~R_V7M_CONTROL_NPRIV_MA= SK; env->v7m.control[env->v7m.secure] |=3D val & R_V7M_CONTROL_NPR= IV_MASK; } - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, env_archcpu(env))) { /* * SFPA is RAZ/WI from NS or if no FPU. * FPCA is RO if NSACR.CP10 =3D=3D 0, RES0 if the FPU is not p= resent. diff --git a/target/arm/machine.c b/target/arm/machine.c index 241890ac8cf..7050bde459a 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -9,9 +9,8 @@ static bool vfp_needed(void *opaque) { ARMCPU *cpu =3D opaque; - CPUARMState *env =3D &cpu->env; =20 - return arm_feature(env, ARM_FEATURE_VFP); + return cpu_isar_feature(aa32_simd_r16, cpu); } =20 static int get_fpscr(QEMUFile *f, void *opaque, size_t size, --=20 2.20.1