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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qNihTLJediBrpCJBoB3GKxR0uHRMJ0laKIeFV/sWBeE=; b=MQNFbY16pR61Fbjdgajdp8bn+FGLccb/PkMZWosIdY4SAadvddq0jIdAPHDKdDy+Ql v7Gtlem7iRujBC/wKzSY28U7cYtJ7CbLldih9Zdp1piKVtnLoGO75YbzHoT/CDC5UEbc 0d/oJRFrbKGAxk6E5k9LEOzx5ak8pv5NAZl+/9AxRZJ0c1rma2VUWin2qU/tXrdECyWF QPJYErNG97d4Og9fRDEdIiMgCj2nYOEwAMjuEvncDQU+a7PdunvlGQGrmQEoFegO6BG9 csZkDAl/9w8pnPAh/drWm/0ebXF2SeHQSqFSlFm8OTuqCdsQmgq+dwBOkIyCmFIFVKvF 0Lkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qNihTLJediBrpCJBoB3GKxR0uHRMJ0laKIeFV/sWBeE=; b=FbzFj8ZvdyDCRIbPrzExBs6+vSFNxZt057YIFHWNmgTpKX9gCOXtef+pYzIM5OSBOd WXaVcbQWeHR4cfcKqrBjIwHhqeN00uGIbs191ZDlFUKc7exjYeHLTOWNxDGk2tHCRmAC OK8ZFWqa1VJXlt4zPJhuME6ndsSfY9f03zX+1mcJKGOHBY5PFmh0j5GXz+Mq1AyMv8+B KCMz0IlDZLLfSA9qLcoljKlGVYOcn0Q9taLOd+mmhgy4I6wT/zMEIzyPQay3ptcFy9mB S4uA5TAgCJzXqUEtrULRho+GPjGZYjOqL/lUtX5H0u3AWCHgk63IsJKqg/o+s5GjjY6Q msVw== X-Gm-Message-State: APjAAAUBdOsKmHiDgG4HCmF6jtqHldNm11GinNBTjDSkOCXUlIW9m3ef 7bv24z80F+J1Aq2HbZU/7PrGx9dpkdAWGA== X-Google-Smtp-Source: APXvYqx5egBCnPoTjWD6En80pTQKzB770C5vu20n5DldSuDJ7IhqZB7tabP5lZR0LhOmETT2K4Y1EQ== X-Received: by 2002:a1c:2093:: with SMTP id g141mr3778986wmg.142.1582290518683; Fri, 21 Feb 2020 05:08:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 46/52] target/arm: Set MVFR0.FPSP for ARMv5 cpus Date: Fri, 21 Feb 2020 13:07:34 +0000 Message-Id: <20200221130740.7583-47-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::335 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We are going to convert FEATURE tests to ISAR tests, so FPSP needs to be set for these cpus, like we have already for FPDP. Signed-off-by: Richard Henderson Message-id: 20200214181547.21408-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8085268a539..2eadf4dcb8b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1872,10 +1872,11 @@ static void arm926_initfn(Object *obj) */ cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); /* - * Similarly, we need to set MVFR0 fields to enable double precision - * and short vector support even though ARMv5 doesn't have this regist= er. + * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or + * support even though ARMv5 doesn't have this register. */ cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); } =20 @@ -1914,10 +1915,11 @@ static void arm1026_initfn(Object *obj) */ cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); /* - * Similarly, we need to set MVFR0 fields to enable double precision - * and short vector support even though ARMv5 doesn't have this regist= er. + * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or + * support even though ARMv5 doesn't have this register. */ cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); =20 { --=20 2.20.1