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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=lZW5fWoykryTlZydn2qsBAZbMdQAuH2IlE0NMzkYoxo=; b=UPhK4mvbVdgdJyzUg4GXrcs2LpeYxYqRHQKCInWWnAze3CJJxS694x7smWL6HvKypD xTQ8p1OrOv8lTHSN7i5/v1uFoWP6SKFbdjyFfP4zfL/e5m2hAuLRIuK62uQLrj3Cqj9Q TeTfQ3xjNKDdxR/4I/AL9LcDTZfNgf3tx8lb6GCx8CazZQfu6+Ajz2jQNbvEGmxxSQp+ 4xaElV5ip6C7mp8mFgWR4HAXnzOIiqzTfdAvbI0fLP+00blisEl6HPfWGAJQKAflYD53 V5RPGgDGziF729e7nP0TX7rUtpzslW8mmzjehnKpe0401cGq74RXs66Q9LIG2AYFXnYy MnIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lZW5fWoykryTlZydn2qsBAZbMdQAuH2IlE0NMzkYoxo=; b=rBcK6jFlrbcdykCdV1Mav7p6Ad7ctfYfy6N0tbXgTJWImMPuq61qfm7k1oVvo1isee ot0XiXQeJ0LdYxjarWrDuI+av3URtqAyAlxzWYjLI+ZJYoBW4r3kt/QeWSVmVEFQKswS 62zdabYmUkVeYFC+z/cgn6Fo+zcIit/YbG0od6r67c65AoVaTDhlpsk5s6CVrZSQu09Q jkmD+ND4u12D3j3F4ZAIYAmqDFfn+Ejl3ZCOv1XVsWiwNBHPNexZH8Qo1cnmShV0uwPa 6teZ5T/YVoMYfZydx+pAAjkgFOS3ZLKBHdY61ZK0V6A4f96D8aLmK1GqpD/Vwzl5KmNg NHlg== X-Gm-Message-State: APjAAAW6PG9xlrx8PF/ZeZ1I5yYgy1Feh3EVXCH1esg2iw6ll3MD+bnh 1aecDbaXzUC4M/ztaVm+GJFs2mjrwGolAg== X-Google-Smtp-Source: APXvYqxmY55aOoQB7Shl8XAQLuabCU3devn0W6wItchx7L5yRzXuUq8cRWUC0xeBPupd0NX3TmAxKQ== X-Received: by 2002:a1c:9849:: with SMTP id a70mr3722500wme.76.1582290517687; Fri, 21 Feb 2020 05:08:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 45/52] target/arm: Use isar_feature_aa32_simd_r32 more places Date: Fri, 21 Feb 2020 13:07:33 +0000 Message-Id: <20200221130740.7583-46-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Many uses of ARM_FEATURE_VFP3 are testing for the number of simd registers implemented. Use the proper test vs MVFR0.SIMDReg. Signed-off-by: Richard Henderson Message-id: 20200214181547.21408-4-richard.henderson@linaro.org [PMM: fix typo in commit message] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.c | 9 ++++----- target/arm/helper.c | 13 ++++++------- target/arm/translate.c | 2 +- 3 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9f618e120aa..8085268a539 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1009,11 +1009,10 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *= f, int flags) =20 if (flags & CPU_DUMP_FPU) { int numvfpregs =3D 0; - if (arm_feature(env, ARM_FEATURE_VFP)) { - numvfpregs +=3D 16; - } - if (arm_feature(env, ARM_FEATURE_VFP3)) { - numvfpregs +=3D 16; + if (cpu_isar_feature(aa32_simd_r32, cpu)) { + numvfpregs =3D 32; + } else if (arm_feature(env, ARM_FEATURE_VFP)) { + numvfpregs =3D 16; } for (i =3D 0; i < numvfpregs; i++) { uint64_t v =3D *aa32_vfp_dreg(env, i); diff --git a/target/arm/helper.c b/target/arm/helper.c index 1ac09f387ed..79db169e046 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -50,10 +50,10 @@ static void switch_mode(CPUARMState *env, int mode); =20 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) { - int nregs; + ARMCPU *cpu =3D env_archcpu(env); + int nregs =3D cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; =20 /* VFP data registers are always little-endian. */ - nregs =3D arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; if (reg < nregs) { stq_le_p(buf, *aa32_vfp_dreg(env, reg)); return 8; @@ -78,9 +78,9 @@ static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf= , int reg) =20 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) { - int nregs; + ARMCPU *cpu =3D env_archcpu(env); + int nregs =3D cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; =20 - nregs =3D arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; if (reg < nregs) { *aa32_vfp_dreg(env, reg) =3D ldq_le_p(buf); return 8; @@ -906,8 +906,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, /* VFPv3 and upwards with NEON implement 32 double precision * registers (D0-D31). */ - if (!arm_feature(env, ARM_FEATURE_NEON) || - !arm_feature(env, ARM_FEATURE_VFP3)) { + if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) { /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ value |=3D (1 << 30); } @@ -7812,7 +7811,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) } else if (arm_feature(env, ARM_FEATURE_NEON)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 51, "arm-neon.xml", 0); - } else if (arm_feature(env, ARM_FEATURE_VFP3)) { + } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 35, "arm-vfp3.xml", 0); } else if (arm_feature(env, ARM_FEATURE_VFP)) { diff --git a/target/arm/translate.c b/target/arm/translate.c index ea6e984da65..79880adaad2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2612,7 +2612,7 @@ static int disas_dsp_insn(DisasContext *s, uint32_t i= nsn) #define VFP_SREG(insn, bigbit, smallbit) \ ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1)) #define VFP_DREG(reg, insn, bigbit, smallbit) do { \ - if (arm_dc_feature(s, ARM_FEATURE_VFP3)) { \ + if (dc_isar_feature(aa32_simd_r32, s)) { \ reg =3D (((insn) >> (bigbit)) & 0x0f) \ | (((insn) >> ((smallbit) - 4)) & 0x10); \ } else { \ --=20 2.20.1