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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.07.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:07:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=liKE80VVvI3xFYB7GeLv6rT6WhoDLIG/p/+a4APFNGA=; b=F7cgiyUfqcfdTAau1Et6xpUEu5B3oVvLi9j1vmcHa5Alm0cCsJ2HHfar2fcILyY3zW 06KAXNe2QR++HqH0rYdB5IWG9EaOMsbKPORti0jdigEUPGnG2aRetKWNrumc5+d/Hx/F FLddP0bQIpKc3dEbaGGrubSVEj+XKeLBIolEaU4C6ciuJj1SIeNusJUT7VrqvM+mXIvR sjJLiT1O6Iw/yHHvHipVXv5FqKr/HbLc6+8odktHDqOeFbK+C0PGPcxlHaZYGWIzXKyV APBy3DtBq5gUYtXtBwamyt8CuPcd+1APvV0Bktu8xXBSOhhsQjDr/GLFImuJiYrlIbx3 GRKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=liKE80VVvI3xFYB7GeLv6rT6WhoDLIG/p/+a4APFNGA=; b=V+L0lwhUS16rHr01+/mzwL12KYThiKsMN2c6nIH//TNxLhXw4ZyviB2J8AkGmTXBhc 4q7asY0hnPOHxG67hiPVZTGWne2RZShXZxWDV/4hn+d9Ea1nL38HSg1/hBFEHChI09vW tzzFH5Z9sRYRH50pCViIhpvr2mQ2TewMgwzVEXCHH7APcWYKIs7Kzethg4QrUr1cOshT DTlMbCQCJ5YLJcBr+0z2YGnTYHH17mqdx7kYyFw03G06amxY4yNV4FD8TWh6XWTxM3vq f5DGVGb2fFs3xaJKEW1DYvSgaLbOrel5XF+FDITuD36n2rVjlt/iyNcpQW1uzQF7Yf1s pgFQ== X-Gm-Message-State: APjAAAVu6Kl9RliM1MTp87wOpW5jDEAMi3Nf8U9iG8KeP2aXspxkmZOt gAsXXNU2hovChWpThXSAvqOIXyyx5jBDIg== X-Google-Smtp-Source: APXvYqwLecQJJL9Tiu+o7FhiDRZje5DvZLb/97dMmwnGH8Sr4ccFgTcsGDylLHX71b1klOgWNp9aww== X-Received: by 2002:adf:f084:: with SMTP id n4mr48353401wro.200.1582290465278; Fri, 21 Feb 2020 05:07:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/52] aspeed/scu: Implement chip ID register Date: Fri, 21 Feb 2020 13:06:50 +0000 Message-Id: <20200221130740.7583-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::429 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Joel Stanley This returns a fixed but non-zero value for the chip id. Signed-off-by: Joel Stanley Reviewed-by: Andrew Jeffery Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200121013302.43839-3-joel@jms.id.au Signed-off-by: Peter Maydell --- hw/misc/aspeed_scu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 6cb388330a8..9d7482a9df1 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -77,6 +77,8 @@ #define CPU2_BASE_SEG4 TO_REG(0x110) #define CPU2_BASE_SEG5 TO_REG(0x114) #define CPU2_CACHE_CTRL TO_REG(0x118) +#define CHIP_ID0 TO_REG(0x150) +#define CHIP_ID1 TO_REG(0x154) #define UART_HPLL_CLK TO_REG(0x160) #define PCIE_CTRL TO_REG(0x180) #define BMC_MMIO_CTRL TO_REG(0x184) @@ -115,6 +117,8 @@ #define AST2600_HW_STRAP2_PROT TO_REG(0x518) #define AST2600_RNG_CTRL TO_REG(0x524) #define AST2600_RNG_DATA TO_REG(0x540) +#define AST2600_CHIP_ID0 TO_REG(0x5B0) +#define AST2600_CHIP_ID1 TO_REG(0x5B4) =20 #define AST2600_CLK TO_REG(0x40) =20 @@ -182,6 +186,8 @@ static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_R= EGS] =3D { [CPU2_BASE_SEG1] =3D 0x80000000U, [CPU2_BASE_SEG4] =3D 0x1E600000U, [CPU2_BASE_SEG5] =3D 0xC0000000U, + [CHIP_ID0] =3D 0x1234ABCDU, + [CHIP_ID1] =3D 0x88884444U, [UART_HPLL_CLK] =3D 0x00001903U, [PCIE_CTRL] =3D 0x0000007BU, [BMC_DEV_ID] =3D 0x00002402U @@ -307,6 +313,8 @@ static void aspeed_ast2500_scu_write(void *opaque, hwad= dr offset, case RNG_DATA: case FREE_CNTR4: case FREE_CNTR4_EXT: + case CHIP_ID0: + case CHIP_ID1: qemu_log_mask(LOG_GUEST_ERROR, "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", __func__, offset); @@ -620,6 +628,8 @@ static void aspeed_ast2600_scu_write(void *opaque, hwad= dr offset, case AST2600_RNG_DATA: case AST2600_SILICON_REV: case AST2600_SILICON_REV2: + case AST2600_CHIP_ID0: + case AST2600_CHIP_ID1: /* Add read only registers here */ qemu_log_mask(LOG_GUEST_ERROR, "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", @@ -648,6 +658,9 @@ static const uint32_t ast2600_a0_resets[ASPEED_AST2600_= SCU_NR_REGS] =3D { [AST2600_CLK_STOP_CTRL2] =3D 0xFFF0FFF0, [AST2600_SDRAM_HANDSHAKE] =3D 0x00000040, /* SoC completed DRAM ini= t */ [AST2600_HPLL_PARAM] =3D 0x1000405F, + [AST2600_CHIP_ID0] =3D 0x1234ABCD, + [AST2600_CHIP_ID1] =3D 0x88884444, + }; =20 static void aspeed_ast2600_scu_reset(DeviceState *dev) --=20 2.20.1