From nobody Mon Feb 9 18:00:13 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582291651; cv=none; d=zohomail.com; s=zohoarc; b=KKrOZUKCl40nEf++gXtL7utuKHLRQSj3ZR5lapW7W6ljqFNHkT1ixmYcehv4oFGFVv2/Fun7Oq7quMPJZcJStnAjgYgHeXz6Rnsn7rNMMMd4GMF0NVqG59xzJQYzLxXLnKvhNHtqi1q9F8QnK0W/jbwLMYZ7vTVtx5Ko+J3LzZM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582291651; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5RqW1VFvoNTFM/LOz4YrIKBR0ShqAPTrRui+k6Sqcms=; b=QZUKYivP9okCTNfIOxbTwNF5xetZM/BI8m35BRXM0hFnDUEXqSa6vss8YWW3kxQQ8bUy5Sf5div8lE1Uf2wi3fbg3czPXGg66d3WwHux7D8zHidfxFgvTjtSK6ZwXseG6oV/SSYS/lwq8FBvp8lLoQskO6ZMQpCdWKKm1rW4dck= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582291651299189.89467818915273; Fri, 21 Feb 2020 05:27:31 -0800 (PST) Received: from localhost ([::1]:57638 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58L3-0003oL-V0 for importer@patchew.org; Fri, 21 Feb 2020 08:27:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56791) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582T-0007PF-CX for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582R-00034S-Tg for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:17 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:53955) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582R-00033o-Ma for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:15 -0500 Received: by mail-wm1-x341.google.com with SMTP id s10so1731366wmh.3 for ; Fri, 21 Feb 2020 05:08:15 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=5RqW1VFvoNTFM/LOz4YrIKBR0ShqAPTrRui+k6Sqcms=; b=ls7HslZR2GfKu7fI7DUeZXJDeEd1RD7151UUdOMoFQF/UdqPO/TEqOKmnjdJPmUwqw UxO6UC32OUHl6izG7It7OC5ycILll3iX8fNpr9KHWcrjYZGZSq2Uh2/76EmEoWoq20yG W1veY/oyRrJ1Yo6ZtfDhN6SWTA77vdZTOtg87qjwF5N36r6ViItVizkH+6Zd5m2NhyAF 20E1pCjT9To+hVIosTTPFKpX1LOE6b47yHVEZGaKRw8so1E1VnHQinKPEeRfF7iC7RlC R8f2dHRTeOByGhUSy2adSkjX5EdjNHR1Ta4gKHojR6uHBvDtT9FEc1n3cxgxAGrah1/g h37w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5RqW1VFvoNTFM/LOz4YrIKBR0ShqAPTrRui+k6Sqcms=; b=C0BlUIKlKwyK+YrOzQeGbFR2/7SJSPCitth776KrjW8a2rGD7atWMXP4ncoMuCb6wB n4vHSxukzYUCWSk7d4GsqBGVCLIkE1Zi1v+FdcHofpBDvL2Cnb3UA3yC3T5fYbZR/ofQ IGxQ2m1n40DYP5kiF8iBQxeZcpnAMUl0G5WcGSZa8T7u47AEE/WZIwhW8KMmJ7k7u1Ef ClrBPprQfLUvkxxtm+M0/3ETq1mygzglD2pG/BQZxd1VfoL9//i/+cKiQj9muoFQaGxS 4YApxLQzJkZoRiEEIDdlJkPrFOYIGXygFgLjp8nrDJkrSmW6n3DX59F0HWOjSqewyPTH Q7aA== X-Gm-Message-State: APjAAAUXBymfh4b4h1oJqTt7aNXH2SxiB8XpOh8Z0tVBpkBybq6maPB7 pnAU+g+BnpNNiSndWCUj26evTnRC7+iNKg== X-Google-Smtp-Source: APXvYqwsz52aYKlJoJv+2Ub+TEKPif2djidD/0rVLsW3YNEU6WjwS3u9lP/pOwGqF1TzK+9di3RNmQ== X-Received: by 2002:a7b:c152:: with SMTP id z18mr3789392wmi.70.1582290493256; Fri, 21 Feb 2020 05:08:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/52] target/arm: Read debug-related ID registers from KVM Date: Fri, 21 Feb 2020 13:07:13 +0000 Message-Id: <20200221130740.7583-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Now we have isar_feature test functions that look at fields in the ID_AA64DFR0_EL1 and ID_DFR0 ID registers, add the code that reads these register values from KVM so that the checks behave correctly when we're using KVM. No isar_feature function tests ID_AA64DFR1_EL1 or DBGDIDR yet, but we add it to maintain the invariant that every field in the ARMISARegisters struct is populated for a KVM CPU and can be relied on. This requirement isn't actually written down yet, so add a note to the relevant comment. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200214175116.9164-13-peter.maydell@linaro.org --- target/arm/cpu.h | 5 +++++ target/arm/kvm32.c | 8 ++++++++ target/arm/kvm64.c | 36 ++++++++++++++++++++++++++++++++++++ 3 files changed, 49 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3c996db3e45..e043932fcb1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -853,6 +853,11 @@ struct ARMCPU { * prefix means a constant register. * Some of these registers are split out into a substructure that * is shared with the translators to control the ISA. + * + * Note that if you add an ID register to the ARMISARegisters struct + * you need to also update the 32-bit and 64-bit versions of the + * kvm_arm_get_host_cpu_features() function to correctly populate the + * field by reading the value from the KVM vCPU. */ struct ARMISARegisters { uint32_t id_isar0; diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 3a8b437eef0..bca02553b25 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -97,6 +97,9 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ah= cf) ahcf->isar.id_isar6 =3D 0; } =20 + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, + ARM_CP15_REG32(0, 0, 1, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0); @@ -108,6 +111,11 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) * Fortunately there is not yet anything in there that affects migrati= on. */ =20 + /* + * There is no way to read DBGDIDR, because currently 32-bit KVM + * doesn't implement debug at all. Leave it at zero. + */ + kvm_arm_destroy_scratch_host_vcpu(fdarray); =20 if (err < 0) { diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 3bae9e4a663..e8d7cea74cb 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -541,6 +541,10 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) } else { err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, ARM64_SYS_REG(3, 0, 0, 4, 1)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, + ARM64_SYS_REG(3, 0, 0, 5, 0)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, + ARM64_SYS_REG(3, 0, 0, 5, 1)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, ARM64_SYS_REG(3, 0, 0, 6, 0)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, @@ -559,6 +563,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) * than skipping the reads and leaving 0, as we must avoid * considering the values in every case. */ + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, + ARM64_SYS_REG(3, 0, 0, 1, 2)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, ARM64_SYS_REG(3, 0, 0, 2, 0)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, @@ -580,6 +586,36 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) ARM64_SYS_REG(3, 0, 0, 3, 1)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, ARM64_SYS_REG(3, 0, 0, 3, 2)); + + /* + * DBGDIDR is a bit complicated because the kernel doesn't + * provide an accessor for it in 64-bit mode, which is what this + * scratch VM is in, and there's no architected "64-bit sysreg + * which reads the same as the 32-bit register" the way there is + * for other ID registers. Instead we synthesize a value from the + * AArch64 ID_AA64DFR0, the same way the kernel code in + * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does. + * We only do this if the CPU supports AArch32 at EL1. + */ + if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >=3D 2) { + int wrps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, W= RPS); + int brps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, B= RPS); + int ctx_cmps =3D + FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS); + int version =3D 6; /* ARMv8 debug architecture */ + bool has_el3 =3D + !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3); + uint32_t dbgdidr =3D 0; + + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, BRPS, brps); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, CTX_CMPS, ctx_cmps); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, VERSION, version); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, NSUHD_IMP, has_el3); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, SE_IMP, has_el3); + dbgdidr |=3D (1 << 15); /* RES1 bit */ + ahcf->isar.dbgdidr =3D dbgdidr; + } } =20 sve_supported =3D ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_S= VE) > 0; --=20 2.20.1