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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.07.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:07:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=nzHzFg20+dv2Qj6R5QZ1RVKcfKZ0HBelWmrraQzT7AY=; b=Os/lQ0pxQoLY0DtDVn92hJvBYKr2+5kiTz+XfLeqsCAgKTb7Tz3XM6rcfj2SeFoGQk EujgAyRRy628bC6flc3UYyDSTySFZNgQlOZYoseAsk+2p7ZCaNgGdlAT3eIWRPXFe+u7 QdA1/ASpRxQuZRqwk7jH+JgTwVREI+jrphmiiwP5wAiMm5aUIE485z02WWNqnZiUebtf JjjmAcRe+8fZWjwVu65mwGf5nEX5jRD7g4DhFI3SXaymBVOe9sv+NsKCDdWxqjl3rxmo oj98iOQX3lr+JM8KWYLVh5TCncpeGkS1RqbgGIDjpoQkZAWaCI4i9WzrLNbTf3g6/bsV oykg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nzHzFg20+dv2Qj6R5QZ1RVKcfKZ0HBelWmrraQzT7AY=; b=HizEOG/V/iw8Kui90u5XYVAiQVxHj0Ns7/fSOtIhEOOALmuhqNj9kb0nYxlRa1DeiH LD4dsep7QcegUpXDLgR3h1d9Xsc5VjmZPN0x/MWVpnIuPNlM7TMYhG22qSu4YicnpojW U8a8ejo+f7xtYGPO1oCCdNQ9DD9Zklels5gTomFODQ3um4I/jbB7HeBPlVJykUhMG+Jq 5WW8RYgkp2+Ow33fVHgzZV6Zckxwewa2RQHnL7BoRWda99GGjCiLPkHZ3LhlMqxK6mAM 7RwaqIe9A/KRpFeb0U2zidAX+D9xXy7tubvuGzEdp0mtSq3fymeREzHRcfUgQJly+fTk T95g== X-Gm-Message-State: APjAAAXmqQwQauZFVGqiJg85rhonCFRzJCpVBSubuuqfE98c3BEtDolZ q7/yn8Yku9qF0DMVxVuVUtmcbrlVzo2p9A== X-Google-Smtp-Source: APXvYqwtuPcCf53T9ZsqGTy0Y2x7iviqx8hUf6aY4Tipe+VUPUtTv0c4lD7ool4KKFHpxO5WkpR8KQ== X-Received: by 2002:a1c:20d6:: with SMTP id g205mr3959431wmg.38.1582290463793; Fri, 21 Feb 2020 05:07:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/52] aspeed/scu: Create separate write callbacks Date: Fri, 21 Feb 2020 13:06:49 +0000 Message-Id: <20200221130740.7583-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::331 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Joel Stanley This splits the common write callback into separate ast2400 and ast2500 implementations. This makes it clearer when implementing differing behaviour. Signed-off-by: Joel Stanley Reviewed-by: Andrew Jeffery Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200121013302.43839-2-joel@jms.id.au Signed-off-by: Peter Maydell --- hw/misc/aspeed_scu.c | 80 +++++++++++++++++++++++++++++++------------- 1 file changed, 57 insertions(+), 23 deletions(-) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index ce2f9562d4c..6cb388330a8 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -232,8 +232,47 @@ static uint64_t aspeed_scu_read(void *opaque, hwaddr o= ffset, unsigned size) return s->regs[reg]; } =20 -static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data, - unsigned size) +static void aspeed_ast2400_scu_write(void *opaque, hwaddr offset, + uint64_t data, unsigned size) +{ + AspeedSCUState *s =3D ASPEED_SCU(opaque); + int reg =3D TO_REG(offset); + + if (reg >=3D ASPEED_SCU_NR_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx = "\n", + __func__, offset); + return; + } + + if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 && + !s->regs[PROT_KEY]) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); + } + + trace_aspeed_scu_write(offset, size, data); + + switch (reg) { + case PROT_KEY: + s->regs[reg] =3D (data =3D=3D ASPEED_SCU_PROT_KEY) ? 1 : 0; + return; + case SILICON_REV: + case FREQ_CNTR_EVAL: + case VGA_SCRATCH1 ... VGA_SCRATCH8: + case RNG_DATA: + case FREE_CNTR4: + case FREE_CNTR4_EXT: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + return; + } + + s->regs[reg] =3D data; +} + +static void aspeed_ast2500_scu_write(void *opaque, hwaddr offset, + uint64_t data, unsigned size) { AspeedSCUState *s =3D ASPEED_SCU(opaque); int reg =3D TO_REG(offset); @@ -257,25 +296,11 @@ static void aspeed_scu_write(void *opaque, hwaddr off= set, uint64_t data, case PROT_KEY: s->regs[reg] =3D (data =3D=3D ASPEED_SCU_PROT_KEY) ? 1 : 0; return; - case CLK_SEL: - s->regs[reg] =3D data; - break; case HW_STRAP1: - if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) { - s->regs[HW_STRAP1] |=3D data; - return; - } - /* Jump to assignment below */ - break; + s->regs[HW_STRAP1] |=3D data; + return; case SILICON_REV: - if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) { - s->regs[HW_STRAP1] &=3D ~data; - } else { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Write to read-only offset 0x%" HWADDR_PRIx = "\n", - __func__, offset); - } - /* Avoid assignment below, we've handled everything */ + s->regs[HW_STRAP1] &=3D ~data; return; case FREQ_CNTR_EVAL: case VGA_SCRATCH1 ... VGA_SCRATCH8: @@ -291,9 +316,18 @@ static void aspeed_scu_write(void *opaque, hwaddr offs= et, uint64_t data, s->regs[reg] =3D data; } =20 -static const MemoryRegionOps aspeed_scu_ops =3D { +static const MemoryRegionOps aspeed_ast2400_scu_ops =3D { .read =3D aspeed_scu_read, - .write =3D aspeed_scu_write, + .write =3D aspeed_ast2400_scu_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .valid.unaligned =3D false, +}; + +static const MemoryRegionOps aspeed_ast2500_scu_ops =3D { + .read =3D aspeed_scu_read, + .write =3D aspeed_ast2500_scu_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, @@ -469,7 +503,7 @@ static void aspeed_2400_scu_class_init(ObjectClass *kla= ss, void *data) asc->calc_hpll =3D aspeed_2400_scu_calc_hpll; asc->apb_divider =3D 2; asc->nr_regs =3D ASPEED_SCU_NR_REGS; - asc->ops =3D &aspeed_scu_ops; + asc->ops =3D &aspeed_ast2400_scu_ops; } =20 static const TypeInfo aspeed_2400_scu_info =3D { @@ -489,7 +523,7 @@ static void aspeed_2500_scu_class_init(ObjectClass *kla= ss, void *data) asc->calc_hpll =3D aspeed_2500_scu_calc_hpll; asc->apb_divider =3D 4; asc->nr_regs =3D ASPEED_SCU_NR_REGS; - asc->ops =3D &aspeed_scu_ops; + asc->ops =3D &aspeed_ast2500_scu_ops; } =20 static const TypeInfo aspeed_2500_scu_info =3D { --=20 2.20.1