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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8bdHdi62p5PzPAd0CdOGxqVtsuzmqbR0T0M8VLe4aj4=; b=nNkUe5L7XNgCNJYsr+LNVUTzdRO1VHn2BJnWzNthWjvcRXoWe+vuoNfiPERXua08P6 FMeQoXNLMtVmtl9MvDXlG/rC5b1rFJ8gmwtxdfn1usZXFtWRlfue2JptzLjhMJc8agUG pwTzA6mFCy99xCkB4s8LyifPcdz7tnF9Lx2W3WzQlm8NAhILOfga1cdsJxl2UvBIhlJl Omnn1SVjBkbnbmXq5Iyu+UIPcFGDanJEGFSnoRt0mGrftVvu1xNQ6JbNRL/wcwHJ976y HvXnMl7BFfqbZ7yIHOMOfTO7PblF7OecV668vFuJHqVAxJ8YqMGiowjCuYi8GRU1prnm OwRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8bdHdi62p5PzPAd0CdOGxqVtsuzmqbR0T0M8VLe4aj4=; b=BbDiOI2jMA1teBGsTcJ6MCM2KemHk33brYpCCfoPREpBjPuIBHTSNbQJ3Lr0vhN5DL GPGYckWBnZkBaHPyX22NaJMHG3HOJU5Qfp1mk0fGWaRaVsKWy06Y5/UpZnwCqQNHHCf+ xeCQesSBSQq2N1N9IUnqgeJ+XkhEZatpfKTPG1WdCrYN++gHAxy28Jd1abs9ngWt9ZIJ 8jrVd2USGpjKnSN//DGKlziavFzMVBoS3xjgeVeOzjdOlSetBAYiNAfaOrg3f3GlVBA5 z6N/N0iUe1hg7sLK77fuDv+egW2aHodcEkAy3hB08V8pJaUa02HJ7QMZ9kQzOSbCnXIr XQqA== X-Gm-Message-State: APjAAAU9XXnUye/VXK+cwzhAHjMCncWFqFwJbO9r4/skK21iP04vMzlf lCZBzZ+TBd6oqFoYOARENN0Zq2nd//5L6Q== X-Google-Smtp-Source: APXvYqyZGOp6lCNV6Ciu/5lSYz81JU03rAsqg1vhtfYSjT01XM3m31T7ef469ZRMtUDyTdyWnecZgg== X-Received: by 2002:a5d:4f8a:: with SMTP id d10mr22577212wru.143.1582290484848; Fri, 21 Feb 2020 05:08:04 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/52] target/arm: Factor out PMU register definitions Date: Fri, 21 Feb 2020 13:07:06 +0000 Message-Id: <20200221130740.7583-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Pull the code that defines the various PMU registers out into its own function, matching the pattern we have already for the debug registers. Apart from one style fix to a multi-line comment, this is purely movement of code with no changes to it. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 20200214175116.9164-6-peter.maydell@linaro.org --- target/arm/helper.c | 158 +++++++++++++++++++++++--------------------- 1 file changed, 82 insertions(+), 76 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ab36f33b719..cb2f4d8bbdb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6317,6 +6317,87 @@ static void define_debug_regs(ARMCPU *cpu) } } =20 +static void define_pmu_regs(ARMCPU *cpu) +{ + /* + * v7 performance monitor control register: same implementor + * field as main ID register, and we implement four counters in + * addition to the cycle count register. + */ + unsigned int i, pmcrn =3D 4; + ARMCPRegInfo pmcr =3D { + .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 0, + .access =3D PL0_RW, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcr), + .accessfn =3D pmreg_access, .writefn =3D pmcr_write, + .raw_writefn =3D raw_write, + }; + ARMCPRegInfo pmcr64 =3D { + .name =3D "PMCR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 0, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), + .resetvalue =3D (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT), + .writefn =3D pmcr_write, .raw_writefn =3D raw_write, + }; + define_one_arm_cp_reg(cpu, &pmcr); + define_one_arm_cp_reg(cpu, &pmcr64); + for (i =3D 0; i < pmcrn; i++) { + char *pmevcntr_name =3D g_strdup_printf("PMEVCNTR%d", i); + char *pmevcntr_el0_name =3D g_strdup_printf("PMEVCNTR%d_EL0", i); + char *pmevtyper_name =3D g_strdup_printf("PMEVTYPER%d", i); + char *pmevtyper_el0_name =3D g_strdup_printf("PMEVTYPER%d_EL0", i); + ARMCPRegInfo pmev_regs[] =3D { + { .name =3D pmevcntr_name, .cp =3D 15, .crn =3D 14, + .crm =3D 8 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7, + .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn, + .accessfn =3D pmreg_access }, + { .name =3D pmevcntr_el0_name, .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 8 | (3 & (i = >> 3)), + .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc= ess, + .type =3D ARM_CP_IO, + .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn, + .raw_readfn =3D pmevcntr_rawread, + .raw_writefn =3D pmevcntr_rawwrite }, + { .name =3D pmevtyper_name, .cp =3D 15, .crn =3D 14, + .crm =3D 12 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7, + .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_writefn, + .accessfn =3D pmreg_access }, + { .name =3D pmevtyper_el0_name, .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 12 | (3 & (i= >> 3)), + .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc= ess, + .type =3D ARM_CP_IO, + .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_writefn, + .raw_writefn =3D pmevtyper_rawwrite }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, pmev_regs); + g_free(pmevcntr_name); + g_free(pmevcntr_el0_name); + g_free(pmevtyper_name); + g_free(pmevtyper_el0_name); + } + if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >=3D 4 && + FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf) { + ARMCPRegInfo v81_pmu_regs[] =3D { + { .name =3D "PMCEID2", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 4, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .resetvalue =3D extract64(cpu->pmceid0, 32, 32) }, + { .name =3D "PMCEID3", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 5, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .resetvalue =3D extract64(cpu->pmceid1, 32, 32) }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, v81_pmu_regs); + } +} + /* We don't know until after realize whether there's a GICv3 * attached, and that is what registers the gicv3 sysregs. * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_= EL1 @@ -6859,67 +6940,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, pmovsset_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_V7)) { - /* v7 performance monitor control register: same implementor - * field as main ID register, and we implement four counters in - * addition to the cycle count register. - */ - unsigned int i, pmcrn =3D 4; - ARMCPRegInfo pmcr =3D { - .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 0, - .access =3D PL0_RW, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcr), - .accessfn =3D pmreg_access, .writefn =3D pmcr_write, - .raw_writefn =3D raw_write, - }; - ARMCPRegInfo pmcr64 =3D { - .name =3D "PMCR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 0, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .type =3D ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), - .resetvalue =3D (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHI= FT), - .writefn =3D pmcr_write, .raw_writefn =3D raw_write, - }; - define_one_arm_cp_reg(cpu, &pmcr); - define_one_arm_cp_reg(cpu, &pmcr64); - for (i =3D 0; i < pmcrn; i++) { - char *pmevcntr_name =3D g_strdup_printf("PMEVCNTR%d", i); - char *pmevcntr_el0_name =3D g_strdup_printf("PMEVCNTR%d_EL0", = i); - char *pmevtyper_name =3D g_strdup_printf("PMEVTYPER%d", i); - char *pmevtyper_el0_name =3D g_strdup_printf("PMEVTYPER%d_EL0"= , i); - ARMCPRegInfo pmev_regs[] =3D { - { .name =3D pmevcntr_name, .cp =3D 15, .crn =3D 14, - .crm =3D 8 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & = 7, - .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_write= fn, - .accessfn =3D pmreg_access }, - { .name =3D pmevcntr_el0_name, .state =3D ARM_CP_STATE_AA6= 4, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 8 | (3 &= (i >> 3)), - .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg= _access, - .type =3D ARM_CP_IO, - .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_write= fn, - .raw_readfn =3D pmevcntr_rawread, - .raw_writefn =3D pmevcntr_rawwrite }, - { .name =3D pmevtyper_name, .cp =3D 15, .crn =3D 14, - .crm =3D 12 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i &= 7, - .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_wri= tefn, - .accessfn =3D pmreg_access }, - { .name =3D pmevtyper_el0_name, .state =3D ARM_CP_STATE_AA= 64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 12 | (3 = & (i >> 3)), - .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg= _access, - .type =3D ARM_CP_IO, - .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_wri= tefn, - .raw_writefn =3D pmevtyper_rawwrite }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, pmev_regs); - g_free(pmevcntr_name); - g_free(pmevcntr_el0_name); - g_free(pmevtyper_name); - g_free(pmevtyper_el0_name); - } ARMCPRegInfo clidr =3D { .name =3D "CLIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 1, @@ -6930,24 +6950,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &clidr); define_arm_cp_regs(cpu, v7_cp_reginfo); define_debug_regs(cpu); + define_pmu_regs(cpu); } else { define_arm_cp_regs(cpu, not_v7_cp_reginfo); } - if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >=3D 4 && - FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf) { - ARMCPRegInfo v81_pmu_regs[] =3D { - { .name =3D "PMCEID2", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 4, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .resetvalue =3D extract64(cpu->pmceid0, 32, 32) }, - { .name =3D "PMCEID3", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 5, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .resetvalue =3D extract64(cpu->pmceid1, 32, 32) }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, v81_pmu_regs); - } if (arm_feature(env, ARM_FEATURE_V8)) { /* AArch64 ID registers, which all have impdef reset values. * Note that within the ID register ranges the unused slots --=20 2.20.1