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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.07.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:07:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=erpCrXEQNw7w6CRXISwFOLOWw8r/yT2DPAkNDqPVIP0=; b=R3HMUa6vL5nxmxfQeJP+muczfvK33hmTxKgP5UaSAS8bL1lq9kN6SgaRebzZrxqfZK uMa+tC/VG3tI/8275aCPJCIBQQsEXDztGKBPeMYWMyDfseyrnuS7MU6iieH6xVo+tvZa hT7lqqEkjwh7ITGPwpysZy9cUU/5u/VlsnuYI10zZ6Dcw6T6W6mdwgE+vLDmB2AXieE5 S78x1vRa4oQVRklZQSPj7HQLK3XdWqsY7U6Y/ldNs+H+fBM5WuXuxso+y8JUkE+jduR2 bgsWx399lrxQwicL4fza2RVgJZq1guiLGffHLi5Uf9IWaSfiMrQHJlv6dgjgBzedVDBQ W6yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=erpCrXEQNw7w6CRXISwFOLOWw8r/yT2DPAkNDqPVIP0=; b=hreLDyRST9ZbWIJrmOcuxkbgaWoMYyGcWi+elAawmMEReXgT5HNFi8UaAloqLs37E/ X5v6izAKJUA7iAosd4vjnn64cD8KLP/WXEjb7Ziht/fcv7bBDpDCx/5xmOSVdKModaHn gS8+viT8CfIFpHDIu4ITL/zwAp6+QcjVGP8qmPvdiw0HRgkAu+CoI32t5/dK8oRPBgoR DggdWGpD9vNC0AykEZOb9Xi3ccVucA0gXCRvESDFJl6XBSK8uubBD1euXvBYfaACW5JU ymSu5yaz+kky+iKybYn+bxCAPtq8seM0eXoUntQp47abLdWefRHrXurEZj6ZbsLfRm6A 0f9A== X-Gm-Message-State: APjAAAUwhX2B1ryhOjdhN9ds5cf7+8PAVYi6ysHmlqmz9+vW8vs+4Atz 2NeJXBh+v3jqSVFH5Zp1/LLqYrjl0/Dlpg== X-Google-Smtp-Source: APXvYqzJqbzX6Ge8LL92/QlpEjpxwn41EgfxPThHl7Nz/9H/5Vy9ekP3Xbfa606L+RSCy50AvAu/GA== X-Received: by 2002:a5d:61c2:: with SMTP id q2mr46866816wrv.425.1582290477960; Fri, 21 Feb 2020 05:07:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/52] target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid Date: Fri, 21 Feb 2020 13:07:01 +0000 Message-Id: <20200221130740.7583-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson For the purpose of rebuild_hflags_a64, we do not need to compute all of the va parameters, only tbi. Moreover, we can compute them in a form that is more useful to storing in hflags. This eliminates the need for aa64_va_parameter_both, so fold that in to aa64_va_parameter. The remaining calls to aa64_va_parameter are in get_phys_addr_lpae and in pauth_helper.c. This reduces the total cpu consumption of aa64_va_parameter in a kernel boot plus a kvm guest kernel boot from 3% to 0.5%. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200216194343.21331-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 3 -- target/arm/helper.c | 68 +++++++++++++++++++++++------------------- 2 files changed, 37 insertions(+), 34 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 58c4d707c5d..14328e3f7da 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1127,15 +1127,12 @@ typedef struct ARMVAParameters { unsigned tsz : 8; unsigned select : 1; bool tbi : 1; - bool tbid : 1; bool epd : 1; bool hpd : 1; bool using16k : 1; bool using64k : 1; } ARMVAParameters; =20 -ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx); ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index eec7b01ab35..8d0f6eca27b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10234,12 +10234,34 @@ static uint8_t convert_stage2_attrs(CPUARMState *= env, uint8_t s2attrs) } #endif /* !CONFIG_USER_ONLY */ =20 -ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx) +static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) +{ + if (regime_has_2_ranges(mmu_idx)) { + return extract64(tcr, 37, 2); + } else if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + return 0; /* VTCR_EL2 */ + } else { + return extract32(tcr, 20, 1); + } +} + +static int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx) +{ + if (regime_has_2_ranges(mmu_idx)) { + return extract64(tcr, 51, 2); + } else if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + return 0; /* VTCR_EL2 */ + } else { + return extract32(tcr, 29, 1); + } +} + +ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx, bool data) { uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; - bool tbi, tbid, epd, hpd, using16k, using64k; - int select, tsz; + bool epd, hpd, using16k, using64k; + int select, tsz, tbi; =20 if (!regime_has_2_ranges(mmu_idx)) { select =3D 0; @@ -10248,11 +10270,9 @@ ARMVAParameters aa64_va_parameters_both(CPUARMStat= e *env, uint64_t va, using16k =3D extract32(tcr, 15, 1); if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { /* VTCR_EL2 */ - tbi =3D tbid =3D hpd =3D false; + hpd =3D false; } else { - tbi =3D extract32(tcr, 20, 1); hpd =3D extract32(tcr, 24, 1); - tbid =3D extract32(tcr, 29, 1); } epd =3D false; } else { @@ -10266,28 +10286,30 @@ ARMVAParameters aa64_va_parameters_both(CPUARMSta= te *env, uint64_t va, epd =3D extract32(tcr, 7, 1); using64k =3D extract32(tcr, 14, 1); using16k =3D extract32(tcr, 15, 1); - tbi =3D extract64(tcr, 37, 1); hpd =3D extract64(tcr, 41, 1); - tbid =3D extract64(tcr, 51, 1); } else { int tg =3D extract32(tcr, 30, 2); using16k =3D tg =3D=3D 1; using64k =3D tg =3D=3D 3; tsz =3D extract32(tcr, 16, 6); epd =3D extract32(tcr, 23, 1); - tbi =3D extract64(tcr, 38, 1); hpd =3D extract64(tcr, 42, 1); - tbid =3D extract64(tcr, 52, 1); } } tsz =3D MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ tsz =3D MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ =20 + /* Present TBI as a composite with TBID. */ + tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); + if (!data) { + tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); + } + tbi =3D (tbi >> select) & 1; + return (ARMVAParameters) { .tsz =3D tsz, .select =3D select, .tbi =3D tbi, - .tbid =3D tbid, .epd =3D epd, .hpd =3D hpd, .using16k =3D using16k, @@ -10295,16 +10317,6 @@ ARMVAParameters aa64_va_parameters_both(CPUARMStat= e *env, uint64_t va, }; } =20 -ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx, bool data) -{ - ARMVAParameters ret =3D aa64_va_parameters_both(env, va, mmu_idx); - - /* Present TBI as a composite with TBID. */ - ret.tbi &=3D (data || !ret.tbid); - return ret; -} - #ifndef CONFIG_USER_ONLY static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx) @@ -12134,21 +12146,15 @@ static uint32_t rebuild_hflags_a64(CPUARMState *e= nv, int el, int fp_el, { uint32_t flags =3D rebuild_hflags_aprofile(env); ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); - ARMVAParameters p0 =3D aa64_va_parameters_both(env, 0, stage1); + uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; uint64_t sctlr; int tbii, tbid; =20 flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); =20 /* Get control bits for tagged addresses. */ - if (regime_has_2_ranges(mmu_idx)) { - ARMVAParameters p1 =3D aa64_va_parameters_both(env, -1, stage1); - tbid =3D (p1.tbi << 1) | p0.tbi; - tbii =3D tbid & ~((p1.tbid << 1) | p0.tbid); - } else { - tbid =3D p0.tbi; - tbii =3D tbid & !p0.tbid; - } + tbid =3D aa64_va_parameter_tbi(tcr, mmu_idx); + tbii =3D tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx); =20 flags =3D FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); flags =3D FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); --=20 2.20.1