From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582290535; cv=none; d=zohomail.com; s=zohoarc; b=gav21iT36NFMbu7QUgogI5qbCfjXGoJ/OgG5xWR5rrKWWo2Vz1/qSJ3nTORGsRkSrbY66+wsnMm6z+zvc6YV4momuj0upLI/ZHViVWvV4zSYDmFmSjSe8DH2uvylE3dnnuylGyLIPwV24QMJU1iK8yTHQpgGzVY4H/+iqSbCm6M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582290535; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nzHzFg20+dv2Qj6R5QZ1RVKcfKZ0HBelWmrraQzT7AY=; b=VMT/O7fk8sLjRhBeYseaX83zO6oNc30aHefGugo+EPwpPzIPz0N3FP5FVQXZe9N5a6FN7K5Gxbp3ds63fSXj/9TLffeJ2mxjJqjfrGyYSz9C6IjYVTlkCECjeXtW08JsXazBwupZsW3dy7lbAzLBiPl7Nl1dPdTN1Cj4amOW8B0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582290535440790.8935699358317; Fri, 21 Feb 2020 05:08:55 -0800 (PST) Received: from localhost ([::1]:57048 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j5834-0008AQ-1X for importer@patchew.org; Fri, 21 Feb 2020 08:08:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56393) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j581z-0006Tg-6A for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j581x-0002Rx-W4 for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:47 -0500 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:52264) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j581x-0002RY-P3 for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:45 -0500 Received: by mail-wm1-x331.google.com with SMTP id p9so1734402wmc.2 for ; Fri, 21 Feb 2020 05:07:45 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.07.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:07:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=nzHzFg20+dv2Qj6R5QZ1RVKcfKZ0HBelWmrraQzT7AY=; b=Os/lQ0pxQoLY0DtDVn92hJvBYKr2+5kiTz+XfLeqsCAgKTb7Tz3XM6rcfj2SeFoGQk EujgAyRRy628bC6flc3UYyDSTySFZNgQlOZYoseAsk+2p7ZCaNgGdlAT3eIWRPXFe+u7 QdA1/ASpRxQuZRqwk7jH+JgTwVREI+jrphmiiwP5wAiMm5aUIE485z02WWNqnZiUebtf JjjmAcRe+8fZWjwVu65mwGf5nEX5jRD7g4DhFI3SXaymBVOe9sv+NsKCDdWxqjl3rxmo oj98iOQX3lr+JM8KWYLVh5TCncpeGkS1RqbgGIDjpoQkZAWaCI4i9WzrLNbTf3g6/bsV oykg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nzHzFg20+dv2Qj6R5QZ1RVKcfKZ0HBelWmrraQzT7AY=; b=HizEOG/V/iw8Kui90u5XYVAiQVxHj0Ns7/fSOtIhEOOALmuhqNj9kb0nYxlRa1DeiH LD4dsep7QcegUpXDLgR3h1d9Xsc5VjmZPN0x/MWVpnIuPNlM7TMYhG22qSu4YicnpojW U8a8ejo+f7xtYGPO1oCCdNQ9DD9Zklels5gTomFODQ3um4I/jbB7HeBPlVJykUhMG+Jq 5WW8RYgkp2+Ow33fVHgzZV6Zckxwewa2RQHnL7BoRWda99GGjCiLPkHZ3LhlMqxK6mAM 7RwaqIe9A/KRpFeb0U2zidAX+D9xXy7tubvuGzEdp0mtSq3fymeREzHRcfUgQJly+fTk T95g== X-Gm-Message-State: APjAAAXmqQwQauZFVGqiJg85rhonCFRzJCpVBSubuuqfE98c3BEtDolZ q7/yn8Yku9qF0DMVxVuVUtmcbrlVzo2p9A== X-Google-Smtp-Source: APXvYqwtuPcCf53T9ZsqGTy0Y2x7iviqx8hUf6aY4Tipe+VUPUtTv0c4lD7ool4KKFHpxO5WkpR8KQ== X-Received: by 2002:a1c:20d6:: with SMTP id g205mr3959431wmg.38.1582290463793; Fri, 21 Feb 2020 05:07:43 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/52] aspeed/scu: Create separate write callbacks Date: Fri, 21 Feb 2020 13:06:49 +0000 Message-Id: <20200221130740.7583-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::331 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Joel Stanley This splits the common write callback into separate ast2400 and ast2500 implementations. This makes it clearer when implementing differing behaviour. Signed-off-by: Joel Stanley Reviewed-by: Andrew Jeffery Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200121013302.43839-2-joel@jms.id.au Signed-off-by: Peter Maydell --- hw/misc/aspeed_scu.c | 80 +++++++++++++++++++++++++++++++------------- 1 file changed, 57 insertions(+), 23 deletions(-) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index ce2f9562d4c..6cb388330a8 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -232,8 +232,47 @@ static uint64_t aspeed_scu_read(void *opaque, hwaddr o= ffset, unsigned size) return s->regs[reg]; } =20 -static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data, - unsigned size) +static void aspeed_ast2400_scu_write(void *opaque, hwaddr offset, + uint64_t data, unsigned size) +{ + AspeedSCUState *s =3D ASPEED_SCU(opaque); + int reg =3D TO_REG(offset); + + if (reg >=3D ASPEED_SCU_NR_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx = "\n", + __func__, offset); + return; + } + + if (reg > PROT_KEY && reg < CPU2_BASE_SEG1 && + !s->regs[PROT_KEY]) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: SCU is locked!\n", __func__); + } + + trace_aspeed_scu_write(offset, size, data); + + switch (reg) { + case PROT_KEY: + s->regs[reg] =3D (data =3D=3D ASPEED_SCU_PROT_KEY) ? 1 : 0; + return; + case SILICON_REV: + case FREQ_CNTR_EVAL: + case VGA_SCRATCH1 ... VGA_SCRATCH8: + case RNG_DATA: + case FREE_CNTR4: + case FREE_CNTR4_EXT: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", + __func__, offset); + return; + } + + s->regs[reg] =3D data; +} + +static void aspeed_ast2500_scu_write(void *opaque, hwaddr offset, + uint64_t data, unsigned size) { AspeedSCUState *s =3D ASPEED_SCU(opaque); int reg =3D TO_REG(offset); @@ -257,25 +296,11 @@ static void aspeed_scu_write(void *opaque, hwaddr off= set, uint64_t data, case PROT_KEY: s->regs[reg] =3D (data =3D=3D ASPEED_SCU_PROT_KEY) ? 1 : 0; return; - case CLK_SEL: - s->regs[reg] =3D data; - break; case HW_STRAP1: - if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) { - s->regs[HW_STRAP1] |=3D data; - return; - } - /* Jump to assignment below */ - break; + s->regs[HW_STRAP1] |=3D data; + return; case SILICON_REV: - if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) { - s->regs[HW_STRAP1] &=3D ~data; - } else { - qemu_log_mask(LOG_GUEST_ERROR, - "%s: Write to read-only offset 0x%" HWADDR_PRIx = "\n", - __func__, offset); - } - /* Avoid assignment below, we've handled everything */ + s->regs[HW_STRAP1] &=3D ~data; return; case FREQ_CNTR_EVAL: case VGA_SCRATCH1 ... VGA_SCRATCH8: @@ -291,9 +316,18 @@ static void aspeed_scu_write(void *opaque, hwaddr offs= et, uint64_t data, s->regs[reg] =3D data; } =20 -static const MemoryRegionOps aspeed_scu_ops =3D { +static const MemoryRegionOps aspeed_ast2400_scu_ops =3D { .read =3D aspeed_scu_read, - .write =3D aspeed_scu_write, + .write =3D aspeed_ast2400_scu_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .valid.unaligned =3D false, +}; + +static const MemoryRegionOps aspeed_ast2500_scu_ops =3D { + .read =3D aspeed_scu_read, + .write =3D aspeed_ast2500_scu_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .valid.min_access_size =3D 4, .valid.max_access_size =3D 4, @@ -469,7 +503,7 @@ static void aspeed_2400_scu_class_init(ObjectClass *kla= ss, void *data) asc->calc_hpll =3D aspeed_2400_scu_calc_hpll; asc->apb_divider =3D 2; asc->nr_regs =3D ASPEED_SCU_NR_REGS; - asc->ops =3D &aspeed_scu_ops; + asc->ops =3D &aspeed_ast2400_scu_ops; } =20 static const TypeInfo aspeed_2400_scu_info =3D { @@ -489,7 +523,7 @@ static void aspeed_2500_scu_class_init(ObjectClass *kla= ss, void *data) asc->calc_hpll =3D aspeed_2500_scu_calc_hpll; asc->apb_divider =3D 4; asc->nr_regs =3D ASPEED_SCU_NR_REGS; - asc->ops =3D &aspeed_scu_ops; + asc->ops =3D &aspeed_ast2500_scu_ops; } =20 static const TypeInfo aspeed_2500_scu_info =3D { --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582290655; cv=none; d=zohomail.com; s=zohoarc; b=WOAhC63gNXRIhDrrCLPOcUFCtLMIa5sqCmYuVIulTjZPpIdnsTwI/it+/mfYscNY5+3JmuOXsr+ipjT3oDQRM/eTOBAmX9TVeumcaBOIw2JzHLEQGCWWcA4ZRsZIJGPpfLr/NRTDrT4Mu3A2np1uDpJlgNiehVPje3XfIYHAXQg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582290655; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=liKE80VVvI3xFYB7GeLv6rT6WhoDLIG/p/+a4APFNGA=; b=M1CcVnfLd3fLCp/MmdYGZ/a+uS0kupAv15dXhpU6Oav8E77AY5goXdPvcOClGYPu+pN3Rfgjhf6hieT8iWmF86wnhpKX3Bduf+udvnE+bj13EDK8Y081ztZU8GVVuo26OPUc7OBhmfzKvPm09OU0hFC5mtVc8WnVFzf3d+W+C3Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582290655386948.8787822843263; Fri, 21 Feb 2020 05:10:55 -0800 (PST) Received: from localhost ([::1]:57186 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j5850-0003RX-9T for importer@patchew.org; Fri, 21 Feb 2020 08:10:54 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56406) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j581z-0006Th-Sz for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:48 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j581y-0002Sy-RO for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:47 -0500 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:41725) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j581y-0002S1-LN for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:46 -0500 Received: by mail-wr1-x429.google.com with SMTP id c9so1984161wrw.8 for ; Fri, 21 Feb 2020 05:07:46 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.07.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:07:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=liKE80VVvI3xFYB7GeLv6rT6WhoDLIG/p/+a4APFNGA=; b=F7cgiyUfqcfdTAau1Et6xpUEu5B3oVvLi9j1vmcHa5Alm0cCsJ2HHfar2fcILyY3zW 06KAXNe2QR++HqH0rYdB5IWG9EaOMsbKPORti0jdigEUPGnG2aRetKWNrumc5+d/Hx/F FLddP0bQIpKc3dEbaGGrubSVEj+XKeLBIolEaU4C6ciuJj1SIeNusJUT7VrqvM+mXIvR sjJLiT1O6Iw/yHHvHipVXv5FqKr/HbLc6+8odktHDqOeFbK+C0PGPcxlHaZYGWIzXKyV APBy3DtBq5gUYtXtBwamyt8CuPcd+1APvV0Bktu8xXBSOhhsQjDr/GLFImuJiYrlIbx3 GRKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=liKE80VVvI3xFYB7GeLv6rT6WhoDLIG/p/+a4APFNGA=; b=V+L0lwhUS16rHr01+/mzwL12KYThiKsMN2c6nIH//TNxLhXw4ZyviB2J8AkGmTXBhc 4q7asY0hnPOHxG67hiPVZTGWne2RZShXZxWDV/4hn+d9Ea1nL38HSg1/hBFEHChI09vW tzzFH5Z9sRYRH50pCViIhpvr2mQ2TewMgwzVEXCHH7APcWYKIs7Kzethg4QrUr1cOshT DTlMbCQCJ5YLJcBr+0z2YGnTYHH17mqdx7kYyFw03G06amxY4yNV4FD8TWh6XWTxM3vq f5DGVGb2fFs3xaJKEW1DYvSgaLbOrel5XF+FDITuD36n2rVjlt/iyNcpQW1uzQF7Yf1s pgFQ== X-Gm-Message-State: APjAAAVu6Kl9RliM1MTp87wOpW5jDEAMi3Nf8U9iG8KeP2aXspxkmZOt gAsXXNU2hovChWpThXSAvqOIXyyx5jBDIg== X-Google-Smtp-Source: APXvYqwLecQJJL9Tiu+o7FhiDRZje5DvZLb/97dMmwnGH8Sr4ccFgTcsGDylLHX71b1klOgWNp9aww== X-Received: by 2002:adf:f084:: with SMTP id n4mr48353401wro.200.1582290465278; Fri, 21 Feb 2020 05:07:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/52] aspeed/scu: Implement chip ID register Date: Fri, 21 Feb 2020 13:06:50 +0000 Message-Id: <20200221130740.7583-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::429 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Joel Stanley This returns a fixed but non-zero value for the chip id. Signed-off-by: Joel Stanley Reviewed-by: Andrew Jeffery Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200121013302.43839-3-joel@jms.id.au Signed-off-by: Peter Maydell --- hw/misc/aspeed_scu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 6cb388330a8..9d7482a9df1 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -77,6 +77,8 @@ #define CPU2_BASE_SEG4 TO_REG(0x110) #define CPU2_BASE_SEG5 TO_REG(0x114) #define CPU2_CACHE_CTRL TO_REG(0x118) +#define CHIP_ID0 TO_REG(0x150) +#define CHIP_ID1 TO_REG(0x154) #define UART_HPLL_CLK TO_REG(0x160) #define PCIE_CTRL TO_REG(0x180) #define BMC_MMIO_CTRL TO_REG(0x184) @@ -115,6 +117,8 @@ #define AST2600_HW_STRAP2_PROT TO_REG(0x518) #define AST2600_RNG_CTRL TO_REG(0x524) #define AST2600_RNG_DATA TO_REG(0x540) +#define AST2600_CHIP_ID0 TO_REG(0x5B0) +#define AST2600_CHIP_ID1 TO_REG(0x5B4) =20 #define AST2600_CLK TO_REG(0x40) =20 @@ -182,6 +186,8 @@ static const uint32_t ast2500_a1_resets[ASPEED_SCU_NR_R= EGS] =3D { [CPU2_BASE_SEG1] =3D 0x80000000U, [CPU2_BASE_SEG4] =3D 0x1E600000U, [CPU2_BASE_SEG5] =3D 0xC0000000U, + [CHIP_ID0] =3D 0x1234ABCDU, + [CHIP_ID1] =3D 0x88884444U, [UART_HPLL_CLK] =3D 0x00001903U, [PCIE_CTRL] =3D 0x0000007BU, [BMC_DEV_ID] =3D 0x00002402U @@ -307,6 +313,8 @@ static void aspeed_ast2500_scu_write(void *opaque, hwad= dr offset, case RNG_DATA: case FREE_CNTR4: case FREE_CNTR4_EXT: + case CHIP_ID0: + case CHIP_ID1: qemu_log_mask(LOG_GUEST_ERROR, "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", __func__, offset); @@ -620,6 +628,8 @@ static void aspeed_ast2600_scu_write(void *opaque, hwad= dr offset, case AST2600_RNG_DATA: case AST2600_SILICON_REV: case AST2600_SILICON_REV2: + case AST2600_CHIP_ID0: + case AST2600_CHIP_ID1: /* Add read only registers here */ qemu_log_mask(LOG_GUEST_ERROR, "%s: Write to read-only offset 0x%" HWADDR_PRIx "\n", @@ -648,6 +658,9 @@ static const uint32_t ast2600_a0_resets[ASPEED_AST2600_= SCU_NR_REGS] =3D { [AST2600_CLK_STOP_CTRL2] =3D 0xFFF0FFF0, [AST2600_SDRAM_HANDSHAKE] =3D 0x00000040, /* SoC completed DRAM ini= t */ [AST2600_HPLL_PARAM] =3D 0x1000405F, + [AST2600_CHIP_ID0] =3D 0x1234ABCD, + [AST2600_CHIP_ID1] =3D 0x88884444, + }; =20 static void aspeed_ast2600_scu_reset(DeviceState *dev) --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.07.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:07:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LnZwcALAQoLYwtLg7hngxVlKU2Xi0Rug4qNNkDV9UPk=; b=oi8PnEj8oSnxe9G6eaPjm6z7AAaUB77jlRhs87NTI4MZR9S5mLP1PAvzXEFA58AZic h+dkWtOC58rvvEPpehoJlEBXd6xge+fg84/rkCqwc9XlhKs93kBX22Ddz/Mx/Ei7iHig kmJMzqhRiXvatS72dRpZqVbxne5BDV3GBuImMNyCyb37vli1tM7X4dYx9sC2DpOPzD2+ wqXLvDKsZ9hc+F4ogk/OGzYmYtoXZcFZzPzXSl6ND/GGseZ6DDwHN7l8z2YYtY6J7QSD 34sTetIoRSxm/G6r5f7Yudf4fLOej1HK1DNxAzsrrD2wbV6CQdsi1NphKPWWkgsySP71 zPoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LnZwcALAQoLYwtLg7hngxVlKU2Xi0Rug4qNNkDV9UPk=; b=mZEKf+WxAKXFpraY0Z7qwrCXOBDZOs449IH22/s+RH5rcYlGFtxguYmk1Gww88Vrpu 1MRAmVsXOnuMI56sVSsiZq6BsTMx9VVYLwF6KxeZHGvsn0hAn5yxKZMqRa79D17ccQ8E bAn3IeVXeGAwkNOLfd89TsVvFjLAzGcFhSF+5zbYnAKVyMeka3CTAYL3BVfjzKxe24+N NUedCaW0a2q/Zd3K6gwFF0KSPrxJHHIWQqBTmEejhGFmjljWYaJIwMLSAf1peXZTA9v7 9SUDODs/h3cMtqRgpomFYn5ZUnoAUZXCIg0QmewAFgMEe9iPc1qQSAfMaLU+PofPo1a/ g3DA== X-Gm-Message-State: APjAAAWtsBkj8c+5LaF9G0We5RfhtFSu1RKrwRtfvepPuqk7cX63orSv Xuq5Q57kMAgNURFEltcatjeFY7wydjwbLQ== X-Google-Smtp-Source: APXvYqxoDFtzxcohHAYxsNP/Z6z+V68R3ci6PT+sYafanxsIRT2cqDggdSmEm+aSIyI0iT4R4B8CEw== X-Received: by 2002:a5d:65c6:: with SMTP id e6mr21378938wrw.45.1582290466416; Fri, 21 Feb 2020 05:07:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/52] hw/misc/iotkit-secctl: Fix writing to 'PPC Interrupt Clear' register Date: Fri, 21 Feb 2020 13:06:51 +0000 Message-Id: <20200221130740.7583-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::434 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 Fix warning reported by Clang static code analyzer: CC hw/misc/iotkit-secctl.o hw/misc/iotkit-secctl.c:343:9: warning: Value stored to 'value' is never = read value &=3D 0x00f000f3; ^ ~~~~~~~~~~ Fixes: b3717c23e1c Reported-by: Clang Static Analyzer Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200217132922.24607-1-f4bug@amsat.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/misc/iotkit-secctl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c index 609869821a1..9fdb82056a8 100644 --- a/hw/misc/iotkit-secctl.c +++ b/hw/misc/iotkit-secctl.c @@ -340,7 +340,7 @@ static MemTxResult iotkit_secctl_s_write(void *opaque, = hwaddr addr, qemu_set_irq(s->sec_resp_cfg, s->secrespcfg); break; case A_SECPPCINTCLR: - value &=3D 0x00f000f3; + s->secppcintstat &=3D ~(value & 0x00f000f3); foreach_ppc(s, iotkit_secctl_ppc_update_irq_clear); break; case A_SECPPCINTEN: --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582290654; cv=none; d=zohomail.com; s=zohoarc; b=kWFQ940gnb8bmcaBiZm6m6CNMZepEZiQJRoXAKo/BSkYkdXOlq+7mtkB05kFmkntnlQWRC+tx+rZk198i57fIMXFr6cBmXf19rgdeB9J6SiO0Y9W15DutmS2rs/FbqU4o1ANmD45U90PAwIDdyRFW616mfomosiww9WrMJNOyrI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582290654; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CH19MfiE/v2T7HEX2v6F3oXsrclEX9/NAMZTm7XbSuc=; b=Z1sB6qQImnXFE7BEMuwASbyvuY4ZVsTf1japYzSDyPSWI81MJRmkLLSwiiiqjvwQxpAGrBQj4EutF5ep3MWWt9MksqAqWgZYdM12ApVlCwSqBqIEotH7y5MbB656cMJkGlQpZKNANfhzhQ/lVanaC5BPa18HySQwuDxIz5T3E+I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582290654542131.7375385714788; Fri, 21 Feb 2020 05:10:54 -0800 (PST) Received: from localhost ([::1]:57182 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j584z-0003Lb-Fd for importer@patchew.org; Fri, 21 Feb 2020 08:10:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56435) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j5821-0006UA-TR for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:50 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j5820-0002U7-RX for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:49 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:44155) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j5820-0002Tj-LS for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:48 -0500 Received: by mail-wr1-x444.google.com with SMTP id m16so1974598wrx.11 for ; Fri, 21 Feb 2020 05:07:48 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.07.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:07:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CH19MfiE/v2T7HEX2v6F3oXsrclEX9/NAMZTm7XbSuc=; b=V5rKSUSa3NoY6J0K/3r1WBTfdW58Dc8IJV83TJYgCCtxHcoE1mN1H4QIXLqjxGccR8 ORuJH+ct4/Qaq4FYJx4/aawrDGzHfdFBaPYo37qEj7eulB14/Vv6DErwZnNwYjXbIJxJ Ct5OEXI5EBu5UA+UTZVWdgujbZLQkTul1WXDyxswXKXWGSSM6z/WhYPf5xCscLH1JcZB qg9hMtsCqBmY7FcA0pGeG4InIVs7b/E67fEp1ysiaAmeXAz1Cdj3nZ1bL2eLnMEEbhxD QwrihcR2b1dVaeU/45L3yhZ/74eBrr2o5AonBWMV/NdPj6kxPupz1UlIZ9F1lBT5Krtv oi6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CH19MfiE/v2T7HEX2v6F3oXsrclEX9/NAMZTm7XbSuc=; b=lTlsl8lcjTBkBD/ntptY1sE1FtTs0KzxDnI80wrIuXJRwlt3wLGKUj8Xvb2tt0YcSi eG0bwy+TKdfyG5S4chihtee7qgdC/gAlqPfO4Ccxa+LDCNUcxaH9aVSVvjV2hWYoecRI 4Qe8fDNuPPILcmKODdXpRwgeDofmjDIt5+mXmReTv3xG0nHXgG4Rzs89uSC/Z35R7R+u ZYBovatWYBUsHDlIpmHDVSbSxL/euTZ/ewlt0T8EISXoDf6yzAuEmUo/4fyQuy60CvuS b2edAdqbr1S/0o3KsGrddEupHAHesZwu1GF9SHt8vEP6cJJAAiMJMGhPpKPV4ZxgyFKq d9gg== X-Gm-Message-State: APjAAAVjaWx110htZfK1qufVFZux0YUhxcMew097gw17IR4iaWIk0ESw rG04ivYDJfv0EotNYNKjcmMIok8tOFA/mg== X-Google-Smtp-Source: APXvYqyvalDmHXL4QM+9PdfpDLTvd2MHnEhr7gZCgg0j6H//u8knKln1QRmOf3QJ2sYU+vQCX/dLjQ== X-Received: by 2002:adf:b605:: with SMTP id f5mr46475467wre.383.1582290467353; Fri, 21 Feb 2020 05:07:47 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/52] mainstone: Make providing flash images non-mandatory Date: Fri, 21 Feb 2020 13:06:52 +0000 Message-Id: <20200221130740.7583-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Guenter Roeck Up to now, the mainstone machine only boots if two flash images are provided. This is not really necessary; the machine can boot from initrd or from SD without it. At the same time, having to provide dummy flash images is a nuisance and does not add any real value. Make it optional. Signed-off-by: Guenter Roeck Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200217210824.18513-1-linux@roeck-us.net Signed-off-by: Peter Maydell --- hw/arm/mainstone.c | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c index b01ce3ce08c..6e64dfab506 100644 --- a/hw/arm/mainstone.c +++ b/hw/arm/mainstone.c @@ -138,19 +138,10 @@ static void mainstone_common_init(MemoryRegion *addre= ss_space_mem, /* There are two 32MiB flash devices on the board */ for (i =3D 0; i < 2; i ++) { dinfo =3D drive_get(IF_PFLASH, 0, i); - if (!dinfo) { - if (qtest_enabled()) { - break; - } - error_report("Two flash images must be given with the " - "'pflash' parameter"); - exit(1); - } - if (!pflash_cfi01_register(mainstone_flash_base[i], i ? "mainstone.flash1" : "mainstone.fla= sh0", MAINSTONE_FLASH, - blk_by_legacy_dinfo(dinfo), + dinfo ? blk_by_legacy_dinfo(dinfo) : NU= LL, sector_len, 4, 0, 0, 0, 0, be)) { error_report("Error registering flash memory"); exit(1); --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582290548; cv=none; d=zohomail.com; s=zohoarc; b=Ju0zAAl9MFDlsTIaNKHG+n6v4lrE5wECsOHsHJzcI3yTl5UYwKICyrr3QMyuPA5DefVr9wvXSg35EB7/L8i+gJ2UsO1PW2Tx+OpFr/jSlx5nFhU3nxysW3CQX4PnhtrTRbnzgL7y0048kAS3/v81Yl/AnWbcu3Jyv02E8+fox8I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582290548; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=B9G9wP9yd2t33Xt2CQJ/kBsj3Yd6lYldXl2KRvMY6ks=; b=YCo+YVk/aEEaCpQiOhMDw+mwl2w9vX5/gqQO8b459G+i2iDhCFY18p2Vt3YzkCwBfvO+k+zeL46AHzITvJ9JxPd3Ix+CDtMqVqMhRwOcgAVnPm8HQzf52ovMOWz9mSIVve1pJY2bkM9xXNpOVmABlT7I4pRdq+JDJdX7CCTSo/s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158229054864995.77624640650924; Fri, 21 Feb 2020 05:09:08 -0800 (PST) Received: from localhost ([::1]:57078 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j583H-0008NN-Bi for importer@patchew.org; Fri, 21 Feb 2020 08:09:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56447) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j5823-0006WD-15 for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:51 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j5822-0002Uw-2q for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:50 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:41637) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j5821-0002UY-Sc for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:50 -0500 Received: by mail-wr1-x442.google.com with SMTP id c9so1984388wrw.8 for ; Fri, 21 Feb 2020 05:07:49 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.07.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:07:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=B9G9wP9yd2t33Xt2CQJ/kBsj3Yd6lYldXl2KRvMY6ks=; b=fWlubCz/PjHPuPsSpd7VhJ5DmSGdB1Tc3ZjTqDK7VYc+wkMX4XZf5WZSGmWMOr2f1R YZTCJkr8l2eWi4sTMnl7JY1GLgpCSjuwz5FmwpW/Prp33pEypAuw+Dn5iIeFAuVW7S0Z njyPBfnivx+wRlFQAOiU1e48IwweFDlPay3JpH4fpJZCoChzsmjQ35ur3FHN9vBJPEN8 RkSY8yE9aEMn7y8zi8DVEgJ2Vfmi1dn85sURHygrE2/yQLdD+8Igz/Cb/fGXqwNORcOw yln8dh+c6T0sl9JVINR6+nTQvaxBWeY30ieLGPFiRwkMYHJbcdQvKsgxJZPxxiu3rjqG YNaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B9G9wP9yd2t33Xt2CQJ/kBsj3Yd6lYldXl2KRvMY6ks=; b=ew7A+0IspT5uuD+QxVJ2mhtxpF+ySsVTZjvyRoCEW+jX66buGznBdCjQ1ypJFuksOo 86A0f/VYabzalmJV0PGJp8tEo1RoVUQWOTbwCAWE2aeImPPs2us//y6tq4PI49kGPnJq ZYZvDkpfVt2RSn8ZA9QbYKkEzxQxhXxwbb+WSISmAzSSm6EuTGLI08t9hde5KYpZa2LC mmmLby2/VJUH+hmRsp5smJGfIJObavOE5Y3aShONnFx87LnbCLucHlfakDorApaAqP+z Gu6YdtDKLzsACOfMGODvxxMMhgtgWeclCnS9+mlog6Rjy6BTP+G9wWgGFnrgOqR7V4pR KkRQ== X-Gm-Message-State: APjAAAVsES96GYf8JBtJpxjRqwPi15bizxaMJBAza9t782GDfCHTnuhU 9tPLr9G5NJGpkb5y3Yhi37yHu/DFkKbpsg== X-Google-Smtp-Source: APXvYqyCmNDKPjpaOrLY6uZR9M4mSpdzlMq+rJw5WZplzZIrm1Wigi8DMRxOF1Hk2GlK7IPZ8Ue76A== X-Received: by 2002:adf:a1d9:: with SMTP id v25mr47782570wrv.160.1582290468546; Fri, 21 Feb 2020 05:07:48 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/52] z2: Make providing flash images non-mandatory Date: Fri, 21 Feb 2020 13:06:53 +0000 Message-Id: <20200221130740.7583-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Guenter Roeck Up to now, the z2 machine only boots if a flash image is provided. This is not really necessary; the machine can boot from initrd or from SD without it. At the same time, having to provide dummy flash images is a nuisance and does not add any real value. Make it optional. Signed-off-by: Guenter Roeck Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200217210903.18602-1-linux@roeck-us.net Signed-off-by: Peter Maydell --- hw/arm/z2.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/hw/arm/z2.c b/hw/arm/z2.c index 34794fe3ae6..4bb237f22d2 100644 --- a/hw/arm/z2.c +++ b/hw/arm/z2.c @@ -314,12 +314,6 @@ static void z2_init(MachineState *machine) be =3D 0; #endif dinfo =3D drive_get(IF_PFLASH, 0, 0); - if (!dinfo && !qtest_enabled()) { - error_report("Flash image must be given with the " - "'pflash' parameter"); - exit(1); - } - if (!pflash_cfi01_register(Z2_FLASH_BASE, "z2.flash0", Z2_FLASH_SIZE, dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, sector_len, 4, 0, 0, 0, 0, be)) { --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582290657; cv=none; d=zohomail.com; s=zohoarc; b=PKXvF4pgp/lUCRlIIQboU/ERlHdgj6NRDn0vWmyPR+uEBUK69hgN2JUSaOLTIAazcW/r06CEhBP1IVbgcxs+SNoEXJT+9pZ1/RkgE9wTY87f6aoeVKLh3iBUjYm8qQq+wcKc2bcSbzViYy/QzJPR/u2OFxdy0qRbdHRLoJ4ccVg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582290657; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=W8sFFOUvnvr4vVzeaXqbU35p4T4/zerZ5D4EmGJn+5w=; b=UGF/NShRoUXZRIlNZ29mtMUHZBT/zKNmDQqeHAlqmJRBudPQkfRb5ewm/Dr4UfDxvi2+YXX+H8Bggs34nfxvtxgYyDvpPLAZmcybVPyDxiKdIJOsPMdf4N9tCStat1urWAGNGvW7vrXaR7WAfgKrwYnAx+W/+zw500hcgPTI/dg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582290657406133.93176434216468; Fri, 21 Feb 2020 05:10:57 -0800 (PST) Received: from localhost ([::1]:57190 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j5852-0003Uu-DM for importer@patchew.org; Fri, 21 Feb 2020 08:10:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56460) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j5824-0006YT-AN for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:53 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j5823-0002VS-4N for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:52 -0500 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:41736) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j5822-0002V6-Uz for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:51 -0500 Received: by mail-wr1-x434.google.com with SMTP id c9so1984449wrw.8 for ; Fri, 21 Feb 2020 05:07:50 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.07.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:07:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=W8sFFOUvnvr4vVzeaXqbU35p4T4/zerZ5D4EmGJn+5w=; b=BWdAlDLz/X3g1j02cl3oHU43f5cg1Ao+DLWqsM4s2yntPvCjANJLBO+rAllK++gyR8 684NKjwa0CcyXb/rMdREnjHuaEUR6nSDOAsZco7OVSxpq/ZRf5YweNJVYxu78Dus0CsD gpe2kVNVgYZMsf1H1ZuaRy8CNcM915APQSXfANWxSr5ZgbihG8WEGB3YBAcojMgTit1U z3lGT7bLqYpj7zIXfjUxTgviV4qLH8w6BYoLoiprT1MPZVN/izCWAMyyEmyCs9Zj3k8S oZ3wRSTxCCGttVOzyeND5pYiC6PPBXCme5NQLR95qveLUSrP+2Nt92LTTSxfruz/peok /KcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W8sFFOUvnvr4vVzeaXqbU35p4T4/zerZ5D4EmGJn+5w=; b=XNr1ITJR+g9UrPofs4lMJCsOBTS4JMrOBN3QFA15fQjf/SrRooZSmxMRpCLLpWZ4+U ivAm0IJKmSdYXdM7O8tqeShtZGvY2Gi7TRjchhAxQRpw5osl6sVPnj0N2N+iIEfby2dn WgIduF5SYnZPevVPy8P+NHwDQSr9Rb++bWRv87Sz9VQzjBTkQTMDKNK3By2cZcNrlg1F XOl9PCHPnCzV3szdYFLzv4CFkkcQ85GpjxaoP8RzpBlDSbzLYzad8tOitxTyrNl9aXzJ jOhgy383byQIydKTTF/t1aFkROKXAWPVFgyg8tZo7FBPqLSTB8dfHm5hLMKpH9y5GoGx 9X6g== X-Gm-Message-State: APjAAAVw6+Yc+DhGP/VGBW4HSns+dxmx94aje0keLBmCn82KPjPmV0ae Oun84eH/7olv18A/O3Gq7Zt6VlDUQhik8g== X-Google-Smtp-Source: APXvYqw1FZ68IH0p0wPns+bYXFnNAJ/dUqjzA9QszG+bgke39x5GKN13uTykJ8PmhnsJNJy329lJGA== X-Received: by 2002:adf:ec08:: with SMTP id x8mr45638132wrn.138.1582290469659; Fri, 21 Feb 2020 05:07:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/52] target/arm: Flush high bits of sve register after AdvSIMD EXT Date: Fri, 21 Feb 2020 13:06:54 +0000 Message-Id: <20200221130740.7583-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::434 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Writes to AdvSIMD registers flush the bits above 128. Buglink: https://bugs.launchpad.net/bugs/1863247 Signed-off-by: Richard Henderson Message-id: 20200214194643.23317-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7c26c3bfebb..620a4290671 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6895,6 +6895,7 @@ static void disas_simd_ext(DisasContext *s, uint32_t = insn) tcg_temp_free_i64(tcg_resl); write_vec_element(s, tcg_resh, rd, 1, MO_64); tcg_temp_free_i64(tcg_resh); + clear_vec_high(s, true, rd); } =20 /* TBL/TBX --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582290782; cv=none; d=zohomail.com; s=zohoarc; b=M+QHACqdjIm71RH3D9dy3a7v+AZa8tZLSBBRQEuwQAikw08zpnxo0+QC3k5+ZWo7oTflzJlh97lgkv7V0R3AGI26/c1YLNU87hG3P4kVoDsdxW0GIJreCqq2FO9EQdAynWq1PUuPU3xY/H7iSfmgX6eFVepkbQQ1L9Nq6daVo0s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582290782; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DxdO7EU52xd3l5dM1HO6ldFtWdD2ROmRpEMpsBaKfGc=; b=Zr6W/XpniQe7fe8nUrCjA28ou9rDh1JUy69FtcCgt8E53BCdtCP0u4vjLhmU2pmgFUcD4EoHVFPd4bOEfbefDJpyIhf8BudqK3RuIeduLkE/HKNZHh8R+fukO7nARzHtos/7kDGAup0Q7U4zSTfxEWmrjD3cSer9VSrR6BJR64Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582290782984536.0463727410016; Fri, 21 Feb 2020 05:13:02 -0800 (PST) Received: from localhost ([::1]:57250 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j5873-00072A-PC for importer@patchew.org; Fri, 21 Feb 2020 08:13:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56476) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j5825-0006bu-Sn for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j5824-0002W8-SW for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:53 -0500 Received: from mail-wm1-x341.google.com ([2a00:1450:4864:20::341]:36596) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j5824-0002Vm-Mu for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:52 -0500 Received: by mail-wm1-x341.google.com with SMTP id p17so1776516wma.1 for ; Fri, 21 Feb 2020 05:07:52 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.07.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:07:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DxdO7EU52xd3l5dM1HO6ldFtWdD2ROmRpEMpsBaKfGc=; b=w4KI827aC8d2X/kqG1eJviq5sBTgfcslYEyuzjtlK6vi6zkX6r+YdujR7Lf9SxHu0l YwHBHxoE9e3+bIMt6RMnLgexFgvRGkQtPj5tooT25WUYoctU7c/IjUyi6JA29su++1WR Yj+nYIgRkS7BQc6jrrDpec1qI+/QddIK23kg7XmWQXWTGlr1022IuBAiaf+zvvRQl6x5 YlgzQu/opojExWBaobwOEcnail5MWWJxCKByfhDjLnq2M1sa+moekq3ECrgHlxCnZkZN 8cgFYVR2ImTOkwaoA1K93C+cSSUdD6e1y1EvV942kgkaCv6uIREibhDxSF6y3fXVGgSC po8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DxdO7EU52xd3l5dM1HO6ldFtWdD2ROmRpEMpsBaKfGc=; b=sSZLXi/H3ZR0leoffympUA5RCz3cpgRPYl7ysLnjZ7GPb0H5psbHpktHGpEkzYNQkz 125t2EWhoLuTLAD8VKoOLga20VFdR2DrYe+/NXc/c1fDxXZoMPjJIdyqaKXMQeNUSEi1 rPv2P3Ff5pXFYtZsgtE3J8ElTCTs8ycX5sobEmoL+GdKQGVHIVHe4C3npQTyTgGEnGpx u/xXZf0B+aki1zEFE5TJgU6YiAYVV/gCXEi9Y/sIabJx/TNvH5HIRrp7npVZFcE9NCTf y+5QOmlZioR3UdJpK9ZrTOsnLv4LRBBmiPf2727dQSns6VXYgcsrDm+m3l7G0KbUsZM1 mpfw== X-Gm-Message-State: APjAAAWggwqiGDvVtcvFzDvve/Z55ivgXTefTB+x1rk9hsqfFHzDJpOU 1sDq8PGLWo437ZIKAXL7fRx4oBJCN6E1JQ== X-Google-Smtp-Source: APXvYqwHHQTlduBU9Fiz62M8sK5flmled3nrVC4c+ie65EBSYAder/uPOie4vcYv+brI7xep1dFA2A== X-Received: by 2002:a1c:238e:: with SMTP id j136mr3736756wmj.17.1582290471292; Fri, 21 Feb 2020 05:07:51 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/52] target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX Date: Fri, 21 Feb 2020 13:06:55 +0000 Message-Id: <20200221130740.7583-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Writes to AdvSIMD registers flush the bits above 128. Signed-off-by: Richard Henderson Message-id: 20200214194643.23317-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 620a4290671..096a854aed7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6964,6 +6964,7 @@ static void disas_simd_tb(DisasContext *s, uint32_t i= nsn) tcg_temp_free_i64(tcg_resl); write_vec_element(s, tcg_resh, rd, 1, MO_64); tcg_temp_free_i64(tcg_resh); + clear_vec_high(s, true, rd); } =20 /* ZIP/UZP/TRN --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582290704; cv=none; d=zohomail.com; s=zohoarc; b=OiHwfz2vIfutw2rhDgwuZrjA5/eePtcAW4+69Sj5pLd9wHkYij1iQLk6pmivm1v5gGbXXVuc74Felra/drJMpX26H5puewa658fLq4dUtjtXI3pr9/Q4GxUjurYLn8Q6o3IcIya2p0gIeNXlWeQveuIFYea6G2+EzS9uRG15Y6w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582290704; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=B8FETunjdDzohDWrvxwGEHSQ/75b6YPRtF3e06IhvLQ=; b=Uq83vXVV2n7MC2Y7a1+nP8Y4PIhvOhBuXYLM2hwA+aVnXkUFaeT914e9EkGatDxZhxpNL7n67nVJrFpJhFjxLvOssp9+OC/M7o0nk91x4x3j5brBuNDgsWQss+ysbdv4LoS1OB/3L6hSppZKwg6pNKw7pwEgNEEi/zKCrzBcI+s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582290704131808.9459616875997; Fri, 21 Feb 2020 05:11:44 -0800 (PST) Received: from localhost ([::1]:57206 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j585n-0004aY-1z for importer@patchew.org; Fri, 21 Feb 2020 08:11:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56487) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j5827-0006f3-7u for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:56 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j5825-0002Wp-Pz for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:55 -0500 Received: from mail-wr1-x442.google.com ([2a00:1450:4864:20::442]:45946) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j5825-0002WM-Ja for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:53 -0500 Received: by mail-wr1-x442.google.com with SMTP id g3so1977158wrs.12 for ; Fri, 21 Feb 2020 05:07:53 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.07.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:07:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=B8FETunjdDzohDWrvxwGEHSQ/75b6YPRtF3e06IhvLQ=; b=e+gDthJf8CtX/fw9I0E6R7UjxY6ekWZg77lR+BHzWHoSXwey9pr9ny69Sbem3hAdcu Vc9bdxNn3BTXIpGqXz+JYbXfqG+3Dbp5nbfaZhwZgSQHBSfOQMOdL6bROwVFsApizhXh 0EF43GkHWtharvEVqXchS/f6W+Nrscal+awsyb40VKO3zjIt/9YwIe9le0ztWyYfPyPk UEM859eLG8+DJsHtJT8pZdWnpepRcmmu9GeeelsjLEwfgl4Bd+Saaf1qKXUK1eAaqx8J UNs+FFPU76LOzXvxm/+g62hM6I/x8lZA0pOwdM9qpcgAqJ3xcDHGw1IRBOi1WLBhWTMI Qt3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B8FETunjdDzohDWrvxwGEHSQ/75b6YPRtF3e06IhvLQ=; b=WbqtZ75DQceHsYU7xtBB98/RUro21nKiccmbrDRtAbBZZfTSji2SB+7RP8vqQgnYBi F2TbWzKo265emkPMV9vPY3aGxw7byrtRdZpZq408qIuJfNIrQRnca2uTa0p44OzUEc4M xpa6o6fiGdK8JElKpzdAGazFtvjuxH4bUSRiSgmYwvx4yvQh2uHCKX4YDeCb5rbOwuuB Q/TK9MtPP9BE0pp1nnBx8hmrqcMZjHsOcBu2g+HXdWkgp1XmNKPV9nF7SqJ7DASBDvMo L3vbphko2MFTnFDDW3gEpBvXEFGjXqeq3tFGaO7CmuWWRrWwX5Vip2n6O1BW1u4GYR0s uyvg== X-Gm-Message-State: APjAAAVvaY4YRCcgBPsRUEz1molNatpBLx/qybJ4l7s5Qsb76/5T/4wG 2nZS0Z4X1GNxOGfZZuDUJ6NFKXcSYw2tXw== X-Google-Smtp-Source: APXvYqxnbIoXnB0IlBm/kWORNwpdz/3c1o7+qEsvXWbdeyiSbuAMmLv+jjt+mhXGl0TLP3PclxDL2g== X-Received: by 2002:a5d:6703:: with SMTP id o3mr46556882wru.235.1582290472303; Fri, 21 Feb 2020 05:07:52 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/52] target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN Date: Fri, 21 Feb 2020 13:06:56 +0000 Message-Id: <20200221130740.7583-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Writes to AdvSIMD registers flush the bits above 128. Signed-off-by: Richard Henderson Message-id: 20200214194643.23317-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 096a854aed7..b83d09dbcd7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7054,6 +7054,7 @@ static void disas_simd_zip_trn(DisasContext *s, uint3= 2_t insn) tcg_temp_free_i64(tcg_resl); write_vec_element(s, tcg_resh, rd, 1, MO_64); tcg_temp_free_i64(tcg_resh); + clear_vec_high(s, true, rd); } =20 /* --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582290778; cv=none; d=zohomail.com; s=zohoarc; b=DTTgoqziAr2w7ADsiLl28LRDb4JOZ48TCmGDSUiX+cCD0h5d1673MpbQmT4RIgzHbQRzq/akSew6Zw+6XkKN/4adxThEbzt+p8HL28bEB9JAKdgwdu2imPgOl0WKOr1tDHhBvPPLYx7POxY450OnimrrpXOiFhcAKNIWaZZS8GM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582290778; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ows304RxUz9Hn/1Tf4KQX6grU12RJO2tytM+z5pmWvE=; b=UkGZ/40nYvis3onPDuWXEuvFqWU5watGyH8bdIpcpsSXlgXLq2L/d1DztVDvikjFrD9zbkcIjpDnknxzHiv+jBEm+Vs0YoSp3TzqjvKQ1sd2Gfy41PgJjJk3ynY4yQH60izRHgKE569iUvUTydt52BYCm6lZF5biVH03w7JtLb4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582290778269567.1273775170953; Fri, 21 Feb 2020 05:12:58 -0800 (PST) Received: from localhost ([::1]:57242 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j586z-0006qc-29 for importer@patchew.org; Fri, 21 Feb 2020 08:12:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56500) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j5828-0006fU-6h for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:57 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j5827-0002XP-7M for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:56 -0500 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:38881) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j5826-0002X2-QJ for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:55 -0500 Received: by mail-wm1-x342.google.com with SMTP id a9so1774937wmj.3 for ; Fri, 21 Feb 2020 05:07:54 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.07.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:07:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ows304RxUz9Hn/1Tf4KQX6grU12RJO2tytM+z5pmWvE=; b=IuCN3yQh1GwsRynYk3smduSDINEdq8H6PPNJdPEm9N+NslQXrS1a5rF5ohh05vr0hW vQrqKsFzvI1jisVJ/RexhOKbcXOdEMveX98EtaAj905E+Q0fBK0Jw6vsWfJ8LZL1ddhQ c+nMRjm4YIBBIg663Q3jcFnDdCMHspP6wJeNPpn4O8LxVfo8K5FVjFRCDwHbbBp4JLqx cr0t5fCxR/YoRcajzXzlHmKjYSEDul6kSbUcUt5sWNOT56qLuzxs7t+tI+pBpZpScJ1K 4//J+kLdmPSjp6ZznULGEZ0IDiT8BzUHX+E09XY9tPXb2i9LGzCEPKMrFDG3SgZo4Qa6 clXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ows304RxUz9Hn/1Tf4KQX6grU12RJO2tytM+z5pmWvE=; b=kR2BIrEajaW1IqvjTvLkCsWavlczWb+AotSB4yZgwy2BOSNpyMyaaKGRA4xSvvQP08 zAok8+JJSRvTrBb1zZXN2JUIckqzJHu4/J/v1rNRQjJnfYuAHAer/4INTmllli5CUpQd KKma13W0dvjm9+PLm4w/kvk0v5t+OjQU1EyVitLQLescCaQshERmCtVOP5jpLVo3c013 raXbo/v0MKXTcwJoh2bzq1AqT68q19COCbwTrwNTxpbtLGgPLje7/tfwEFMECUcgZkRb 8qATEqWBTSKhxx+Z6dcVvWD9KSY6ePsyDX7HiqA22w33bdJyJnoeku4gwVDc3l87ki7P vLUg== X-Gm-Message-State: APjAAAUN5aMoftO880pK1934c4KCAouwUpy5ONaKyWrVH5LBOx02QL/6 fgCf4JKoJTlbQShnFQX3ARpewkvqOS7ypQ== X-Google-Smtp-Source: APXvYqwRkZmn/Ht/UrjgVGqUeDsTzQS6GE9l1p2wn7R32qNKn5ekmTPbrfZxZDOPHaIOIxNnM+p+mQ== X-Received: by 2002:a05:600c:2254:: with SMTP id a20mr3820640wmm.188.1582290473497; Fri, 21 Feb 2020 05:07:53 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/52] target/arm: Flush high bits of sve register after AdvSIMD INS Date: Fri, 21 Feb 2020 13:06:57 +0000 Message-Id: <20200221130740.7583-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Writes to AdvSIMD registers flush the bits above 128. Signed-off-by: Richard Henderson Message-id: 20200214194643.23317-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b83d09dbcd7..bd68588a710 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -7412,6 +7412,9 @@ static void handle_simd_inse(DisasContext *s, int rd,= int rn, write_vec_element(s, tmp, rd, dst_index, size); =20 tcg_temp_free_i64(tmp); + + /* INS is considered a 128-bit write for SVE. */ + clear_vec_high(s, true, rd); } =20 =20 @@ -7441,6 +7444,9 @@ static void handle_simd_insg(DisasContext *s, int rd,= int rn, int imm5) =20 idx =3D extract32(imm5, 1 + size, 4 - size); write_vec_element(s, cpu_reg(s, rn), rd, idx, size); + + /* INS is considered a 128-bit write for SVE. */ + clear_vec_high(s, true, rd); } =20 /* --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582290779; cv=none; d=zohomail.com; s=zohoarc; b=SS43Zr6snwDBUBwPNSnt37z0EM8pe7EGQP312FU5FY+RrA/QQniqQ192gmuCaUw1u+JUvN98clk2LZACFV4v96Gjy/qEfBhJWdCiSF16QbJKb7eZHGlmBHs/IAEwXQxI5wGLFSl1iQf/KY4baH1ZOi2kcn1t6VGx29UfwRw3L4g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582290779; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kEbZ0H6BPcwPTKlgGDMsr9sYvm7F+OeNwNzpuyE6fjM=; b=H4MFWWPYF7XaGfs2qIa0NdQxN2Pq7gSqLebBkBJoeoywsebDewtsf+P9lmmOYGbZsGnC3nRpBe2rlijZrf6AnjF3KG+GuSQRPw9FfxsfsOmpMRcbhqfG2fzaNE6NF2bDA/bwYVlhPfe6qAu/jsFZCHP+9IyhXh8aJ6evpCqoCXQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582290779455512.8321324624608; Fri, 21 Feb 2020 05:12:59 -0800 (PST) Received: from localhost ([::1]:57246 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j5870-0006wN-9L for importer@patchew.org; Fri, 21 Feb 2020 08:12:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56512) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j5829-0006gH-3n for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j5828-0002Xz-6E for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:57 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:37595) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j5827-0002XZ-VK for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:56 -0500 Received: by mail-wr1-x441.google.com with SMTP id w15so1996689wru.4 for ; Fri, 21 Feb 2020 05:07:55 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.07.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:07:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=kEbZ0H6BPcwPTKlgGDMsr9sYvm7F+OeNwNzpuyE6fjM=; b=Cx14x+zdlr4CfYn+gZ/j2E05IpYY52A7kALoVOySYJlgoDy3AIBN6oaijZIYt12nVB UhBz1fz1giuPLTmf3h/xj0e5tZ7t4x3K7F/Grf5Onk6n9T4nVOYqpG+lZr3s12Zica7d z4DA4tLDsmGb5p7vnF0SZBdOlvJTdtVwTYn11otqkVCeXngJWxTZPhj7NwMsRFZWnQNX eBjhibnq68ALOi+c9wDSp++l5chHvKNLnhb5WDVJJEKRBi9XMp7N42/TGnV/qn3EU49X NOFoCN7XgajK5rNoJ8nfVTCwinIEOJ5WLvDI502qZeQbPQM5T0Z6JyUwFGnTMeNmtMU6 iUsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kEbZ0H6BPcwPTKlgGDMsr9sYvm7F+OeNwNzpuyE6fjM=; b=lXjFheqIhAArpdZv4+33teM2q35nzDrnet8feMbPYgkx4QdfadtQEvxdbcjzQJa0xU +dw14Hic43cTGsxcG1cfU3LrV5V+GFtlg+b4IVKBv8yboaJhnUqUJFMTzuTlpAW1nXxx Tk3OANhNpPNpbE1JNPfKexv4Rk4+bhX2QL8uwD0vqSnAz9BEVXfZN2jEUiJbgW1Wc70w EQuzTxwsgr8/uMfzWgj21PlyFKlu4w4wR0P3mch1Z7Aqb0R0JUtzqupJi88cwdSN7yq5 gLFs821CdegumAiUVBBvwVXi3fOy22/uK4VSBwf3BftOfmE3EE7SnFVyJvk8XF6RzjZD LXCg== X-Gm-Message-State: APjAAAUllbGTn/P8KAM2rYTAyIbd9j/XOPbZm/PG11U94EaIvHD/qfU8 08NvjgS9HPHICabtzQvc2+waBunIs5J9Hw== X-Google-Smtp-Source: APXvYqwTuXvWNsIVXXvYLenqZ09snTdL1PsxYOZSpTDMuF6gde9e4SKXoAPnhuvh0zf7yoNH/GRJkg== X-Received: by 2002:adf:b351:: with SMTP id k17mr48286933wrd.199.1582290474574; Fri, 21 Feb 2020 05:07:54 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/52] target/arm: Use bit 55 explicitly for pauth Date: Fri, 21 Feb 2020 13:06:58 +0000 Message-Id: <20200221130740.7583-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson The psuedocode in aarch64/functions/pac/auth/Auth and aarch64/functions/pac/strip/Strip always uses bit 55 for extfield and do not consider if the current regime has 2 ranges. Suggested-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20200216194343.21331-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/pauth_helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/pauth_helper.c b/target/arm/pauth_helper.c index 9746e32bf81..b909630317e 100644 --- a/target/arm/pauth_helper.c +++ b/target/arm/pauth_helper.c @@ -320,7 +320,8 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t= ptr, uint64_t modifier, =20 static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) { - uint64_t extfield =3D -param.select; + /* Note that bit 55 is used whether or not the regime has 2 ranges. */ + uint64_t extfield =3D sextract64(ptr, 55, 1); int bot_pac_bit =3D 64 - param.tsz; int top_pac_bit =3D 64 - 8 * param.tbi; =20 --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582290895; cv=none; d=zohomail.com; s=zohoarc; b=dXqUnYIGCEDvqgd1rwOXal/CC1aFyOhrTRcfWdGC5th3EDL/LPb6J+bTsy+o6Ju2gT6rE/a7tTNKwAAqcPB8ikk3abpyaK0yyidsxMT1QvYVhPwiGySJu9am6uALElKVcoF/1vDvjNh1kJgP943OQN98YWjtTMtIFUlfC2b45pE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582290895; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nvzeMWUSUjCUFT9WRsYP0rykgD3WLIPD7Ig/88Et8tY=; b=c8DGzeBz41iZINce4vV2CkAvzTHWUBvR8imjowAEtvW4NNLaA8iTZ8pbO5uFk+4naA4lo3MFDnJvyktzmJsWRWb35BlsIkvWSKPZ+iVgJ4cxTM0u+PXadLCF4vFqjJsotpFGesJZcqjMe/8VaVmsaorfh3W+YEDD9bl1UfTLBHw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582290894835712.5190284145258; Fri, 21 Feb 2020 05:14:54 -0800 (PST) Received: from localhost ([::1]:57296 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j588r-0001ze-J0 for importer@patchew.org; Fri, 21 Feb 2020 08:14:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56539) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582A-0006hR-Gx for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j5829-0002Zc-Aq for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:58 -0500 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:39956) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j5829-0002YC-4R for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:07:57 -0500 Received: by mail-wr1-x432.google.com with SMTP id t3so1983166wru.7 for ; Fri, 21 Feb 2020 05:07:57 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.07.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:07:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=nvzeMWUSUjCUFT9WRsYP0rykgD3WLIPD7Ig/88Et8tY=; b=Nfo2QmVemaqSnFMOj7L3uFoFV2aSeRgi4UqeSxEQWD8fS1K4Maq8wWEjlpSVl4Dn9W ipOsAgHKQu8v5czeF2RCJn8kNDXunzXP+ujxmEDsYbbQFjBoastQFewY7ndg5lHyC6fO NVk9rNV62Kl5kfu8NQ8z1sktpYIvvKck4ETIcwdA8YqoqEauS1NTpx3nBVK87g6chjEy t+evPldeBrUhrFEMb+DV6mE39PIGEn8fwuYuJNYR3HH/M2+oQOlzFSxnjbxxym5Y3yBe qvfE7EOcECSheNNM5f5TLKHxqgB+pNvQDhN0kScODJcEzWrXs0Zh2v0nuZiqg+1CjfKf 3sSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nvzeMWUSUjCUFT9WRsYP0rykgD3WLIPD7Ig/88Et8tY=; b=XjQoUbFWC7F0D468Qg6HgeTQ+83AuScko1zTqyDACZOz2VbvrY1KqZfbAOg0sjYEX0 WI83rLCmEXhyoENt8MviKB8wxclHofWnz/ziiDU+Yfcs5Y7DpU21I7/Zp0wXP2KWTpDd Lgvnk7dvdx9KekHcUmB+eGYndSoSPvu0pWhReOblyGcx4mqY9GCQxGQST/NlLTG/IbFf 5i/fI0cwVDENdQYUDm4WFJqKrd8J0u9sfnuJnJRdz75JOeOvX40ChXj5xa/y4zt5M+r6 wAPRcSZQ6iQDwne5KWjUPTqrRiGjZXsEVP3JsbOc7ibZsETwHlDOVwbG0ZROZ0PwA8E3 1lZA== X-Gm-Message-State: APjAAAVLF/HKbSsY9GR1aGETCADFFetKCWgG8DT9qs75dhDxWzwpyE6y YjIwI+JGnjh900Ksea0rlRRPQF3d8zXk5Q== X-Google-Smtp-Source: APXvYqyGdteC5MQmaPv0JTAq1Cycp8lyGv6Dr7ehWb2RWg1fnyrgXvESiLwZ/zcrCtRWbRSpvL0aJQ== X-Received: by 2002:adf:e683:: with SMTP id r3mr51503006wrm.38.1582290475808; Fri, 21 Feb 2020 05:07:55 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/52] target/arm: Fix select for aa64_va_parameters_both Date: Fri, 21 Feb 2020 13:06:59 +0000 Message-Id: <20200221130740.7583-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::432 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Select should always be 0 for a regime with one range. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200216194343.21331-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 46 +++++++++++++++++++++++---------------------- 1 file changed, 24 insertions(+), 22 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 366dbcf460d..b09a5012841 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10241,13 +10241,8 @@ ARMVAParameters aa64_va_parameters_both(CPUARMStat= e *env, uint64_t va, bool tbi, tbid, epd, hpd, using16k, using64k; int select, tsz; =20 - /* - * Bit 55 is always between the two regions, and is canonical for - * determining if address tagging is enabled. - */ - select =3D extract64(va, 55, 1); - if (!regime_has_2_ranges(mmu_idx)) { + select =3D 0; tsz =3D extract32(tcr, 0, 6); using64k =3D extract32(tcr, 14, 1); using16k =3D extract32(tcr, 15, 1); @@ -10260,23 +10255,30 @@ ARMVAParameters aa64_va_parameters_both(CPUARMSta= te *env, uint64_t va, tbid =3D extract32(tcr, 29, 1); } epd =3D false; - } else if (!select) { - tsz =3D extract32(tcr, 0, 6); - epd =3D extract32(tcr, 7, 1); - using64k =3D extract32(tcr, 14, 1); - using16k =3D extract32(tcr, 15, 1); - tbi =3D extract64(tcr, 37, 1); - hpd =3D extract64(tcr, 41, 1); - tbid =3D extract64(tcr, 51, 1); } else { - int tg =3D extract32(tcr, 30, 2); - using16k =3D tg =3D=3D 1; - using64k =3D tg =3D=3D 3; - tsz =3D extract32(tcr, 16, 6); - epd =3D extract32(tcr, 23, 1); - tbi =3D extract64(tcr, 38, 1); - hpd =3D extract64(tcr, 42, 1); - tbid =3D extract64(tcr, 52, 1); + /* + * Bit 55 is always between the two regions, and is canonical for + * determining if address tagging is enabled. + */ + select =3D extract64(va, 55, 1); + if (!select) { + tsz =3D extract32(tcr, 0, 6); + epd =3D extract32(tcr, 7, 1); + using64k =3D extract32(tcr, 14, 1); + using16k =3D extract32(tcr, 15, 1); + tbi =3D extract64(tcr, 37, 1); + hpd =3D extract64(tcr, 41, 1); + tbid =3D extract64(tcr, 51, 1); + } else { + int tg =3D extract32(tcr, 30, 2); + using16k =3D tg =3D=3D 1; + using64k =3D tg =3D=3D 3; + tsz =3D extract32(tcr, 16, 6); + epd =3D extract32(tcr, 23, 1); + tbi =3D extract64(tcr, 38, 1); + hpd =3D extract64(tcr, 42, 1); + tbid =3D extract64(tcr, 52, 1); + } } tsz =3D MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ tsz =3D MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582290921; cv=none; d=zohomail.com; s=zohoarc; b=Li7j15By+pkQbNQL0PJgXir0/6MoMDHh7OsDpXIaDqXUvc9rlv+U68LiDxHc9LRELugky/IEqETSiyjiId5ZxQozcXRgPG2V6wfxFxkfmbhtMXXMZsHgFPp59aSnPsdu8qCPst8/5zKHr5x96BKuhe4MGovBYE58RY0W2TFjPxY= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.07.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:07:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=w1YmYCcAKRBV1EX92vhM6AptB/gtkq7KXvJqv02+0/4=; b=s5GZtK5q4skwH/fcsDQhTuvnjwKdeuabFxbjd0n7oJvtEdGRKVJW8dN7u3nv8vMMlk hYdcwO10xhNPNpJmM8OTb8oh1N4k8Y62gIK7AeGs5h4JZN+z0WrQ/u0MYEBek9QyZkEn XHCGRPT63yec2F/RliFJP0XR5N75NTKptR3Convnqfn/DKEoPfG1YuwJhi7WpXK3tXFS USRSr12yz0m/bsUDmgCBBq2/RZ0gxivCwC0yg1hp0UIJafRXMbgOF/dGYnOFnIuZYP+9 LAOBGoqImMpETsf1nk/WtqW5S4xJ/8oDr19svsEuBgpbbCkCcTaZxCvWBkv0aa77HeEY mmnA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w1YmYCcAKRBV1EX92vhM6AptB/gtkq7KXvJqv02+0/4=; b=cIuzNj9voNX7zIuGNkEjTK9wVuZPR872ZK+CxBXRN23FvbhSHIfDqusV3uF09EnsFW FqhLMdOlZv0/xItaOGmLL+wGjJN4FsCa9hvEVMeA8Lyl/195ljaNpRjMdkX4ETWhTw6w 7ZCSlPWqrZ+Ewp5IZdwHpDtkz2tcQdj3afS6v8h3AkJ8cZhTov9/MRyoMjVUhm1dZcx8 tZqJn53eWVrVKE6lTpLb+zwyrUpKxLNltsIatkai/ppn2/QOAiEkQk25FKs17R/I//pA 3Bbfz18ZPHf4Yf/Ei5dkXRiChvu+XnkD4hRpa+y5nb+y6iTVAHyKtYd45UleNlLsnEZ3 7ztg== X-Gm-Message-State: APjAAAV3a6uvY+a7v7LBwzmdrNA4FpeP4HGap8LHXt7Fg2p4qtb7T0Cf D6ugWbV0hM5ERVqX6z72KcVclcrVt5Eopw== X-Google-Smtp-Source: APXvYqyYxMNFn8RarhmAthdqVSRsbGbrPw8/vBDz3qQi+24Rcv3IKiMgPki5R05U1UA5iAgY13NpIg== X-Received: by 2002:a1c:5f41:: with SMTP id t62mr3922182wmb.42.1582290476756; Fri, 21 Feb 2020 05:07:56 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/52] target/arm: Remove ttbr1_valid check from get_phys_addr_lpae Date: Fri, 21 Feb 2020 13:07:00 +0000 Message-Id: <20200221130740.7583-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::333 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Now that aa64_va_parameters_both sets select based on the number of ranges in the regime, the ttbr1_valid check is redundant. Signed-off-by: Richard Henderson Message-id: 20200216194343.21331-4-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b09a5012841..eec7b01ab35 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10390,7 +10390,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta= rget_ulong address, TCR *tcr =3D regime_tcr(env, mmu_idx); int ap, ns, xn, pxn; uint32_t el =3D regime_el(env, mmu_idx); - bool ttbr1_valid; uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); bool guarded =3D false; @@ -10405,14 +10404,11 @@ static bool get_phys_addr_lpae(CPUARMState *env, = target_ulong address, param =3D aa64_va_parameters(env, address, mmu_idx, access_type !=3D MMU_INST_FETCH); level =3D 0; - ttbr1_valid =3D regime_has_2_ranges(mmu_idx); addrsize =3D 64 - 8 * param.tbi; inputsize =3D 64 - param.tsz; } else { param =3D aa32_va_parameters(env, address, mmu_idx); level =3D 1; - /* There is no TTBR1 for EL2 */ - ttbr1_valid =3D (el !=3D 2); addrsize =3D (mmu_idx =3D=3D ARMMMUIdx_Stage2 ? 40 : 32); inputsize =3D addrsize - param.tsz; } @@ -10429,7 +10425,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta= rget_ulong address, if (inputsize < addrsize) { target_ulong top_bits =3D sextract64(address, inputsize, addrsize - inputsize); - if (-top_bits !=3D param.select || (param.select && !ttbr1_valid))= { + if (-top_bits !=3D param.select) { /* The gap between the two regions is a Translation fault */ fault_type =3D ARMFault_Translation; goto do_fault; --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582290895; cv=none; d=zohomail.com; s=zohoarc; b=WA4v+e1i5+fDCtVPEqeKdO+OUteBU04o3SCWOGfyx71eWNHV1r5HCluxebA5C+emG/qv5A7yLIP5ZoOpSYx1MMpc8kIGtVjKSSz4B3iSjC3ZGRaaoE0iR1NONbLG/baHbG0tvX/8fJ9N8JJVmSsTrm1VFd9OcX9dH7Y5hw3J/Ng= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582290895; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=erpCrXEQNw7w6CRXISwFOLOWw8r/yT2DPAkNDqPVIP0=; b=ZIhi7/8fvFUNG6az4Mh/OAb8j2VbWCrJfVM5yQEQnIPlMHJp2zc+ZXbIuDzHVZLDPzmrnlj53lbXvNmaG4/StO5QxQk0D0SG8q/s4tFPxLGsQWXijhOPgqoxdpObKjbyt/oJNTVEdS13ivSxu+8/Nwn8OyCQZHSyRZFfWi1cND8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582290894977590.4157468430661; Fri, 21 Feb 2020 05:14:54 -0800 (PST) Received: from localhost ([::1]:57292 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j588r-0001yR-TF for importer@patchew.org; Fri, 21 Feb 2020 08:14:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56611) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582F-0006o1-Ve for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582E-0002i8-CZ for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:03 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:42073) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582E-0002c5-4i for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:02 -0500 Received: by mail-wr1-x42c.google.com with SMTP id k11so1983552wrd.9 for ; Fri, 21 Feb 2020 05:07:59 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.07.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:07:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=erpCrXEQNw7w6CRXISwFOLOWw8r/yT2DPAkNDqPVIP0=; b=R3HMUa6vL5nxmxfQeJP+muczfvK33hmTxKgP5UaSAS8bL1lq9kN6SgaRebzZrxqfZK uMa+tC/VG3tI/8275aCPJCIBQQsEXDztGKBPeMYWMyDfseyrnuS7MU6iieH6xVo+tvZa hT7lqqEkjwh7ITGPwpysZy9cUU/5u/VlsnuYI10zZ6Dcw6T6W6mdwgE+vLDmB2AXieE5 S78x1vRa4oQVRklZQSPj7HQLK3XdWqsY7U6Y/ldNs+H+fBM5WuXuxso+y8JUkE+jduR2 bgsWx399lrxQwicL4fza2RVgJZq1guiLGffHLi5Uf9IWaSfiMrQHJlv6dgjgBzedVDBQ W6yQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=erpCrXEQNw7w6CRXISwFOLOWw8r/yT2DPAkNDqPVIP0=; b=hreLDyRST9ZbWIJrmOcuxkbgaWoMYyGcWi+elAawmMEReXgT5HNFi8UaAloqLs37E/ X5v6izAKJUA7iAosd4vjnn64cD8KLP/WXEjb7Ziht/fcv7bBDpDCx/5xmOSVdKModaHn gS8+viT8CfIFpHDIu4ITL/zwAp6+QcjVGP8qmPvdiw0HRgkAu+CoI32t5/dK8oRPBgoR DggdWGpD9vNC0AykEZOb9Xi3ccVucA0gXCRvESDFJl6XBSK8uubBD1euXvBYfaACW5JU ymSu5yaz+kky+iKybYn+bxCAPtq8seM0eXoUntQp47abLdWefRHrXurEZj6ZbsLfRm6A 0f9A== X-Gm-Message-State: APjAAAUwhX2B1ryhOjdhN9ds5cf7+8PAVYi6ysHmlqmz9+vW8vs+4Atz 2NeJXBh+v3jqSVFH5Zp1/LLqYrjl0/Dlpg== X-Google-Smtp-Source: APXvYqzJqbzX6Ge8LL92/QlpEjpxwn41EgfxPThHl7Nz/9H/5Vy9ekP3Xbfa606L+RSCy50AvAu/GA== X-Received: by 2002:a5d:61c2:: with SMTP id q2mr46866816wrv.425.1582290477960; Fri, 21 Feb 2020 05:07:57 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/52] target/arm: Split out aa64_va_parameter_tbi, aa64_va_parameter_tbid Date: Fri, 21 Feb 2020 13:07:01 +0000 Message-Id: <20200221130740.7583-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson For the purpose of rebuild_hflags_a64, we do not need to compute all of the va parameters, only tbi. Moreover, we can compute them in a form that is more useful to storing in hflags. This eliminates the need for aa64_va_parameter_both, so fold that in to aa64_va_parameter. The remaining calls to aa64_va_parameter are in get_phys_addr_lpae and in pauth_helper.c. This reduces the total cpu consumption of aa64_va_parameter in a kernel boot plus a kvm guest kernel boot from 3% to 0.5%. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20200216194343.21331-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 3 -- target/arm/helper.c | 68 +++++++++++++++++++++++------------------- 2 files changed, 37 insertions(+), 34 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 58c4d707c5d..14328e3f7da 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1127,15 +1127,12 @@ typedef struct ARMVAParameters { unsigned tsz : 8; unsigned select : 1; bool tbi : 1; - bool tbid : 1; bool epd : 1; bool hpd : 1; bool using16k : 1; bool using64k : 1; } ARMVAParameters; =20 -ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx); ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index eec7b01ab35..8d0f6eca27b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10234,12 +10234,34 @@ static uint8_t convert_stage2_attrs(CPUARMState *= env, uint8_t s2attrs) } #endif /* !CONFIG_USER_ONLY */ =20 -ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx) +static int aa64_va_parameter_tbi(uint64_t tcr, ARMMMUIdx mmu_idx) +{ + if (regime_has_2_ranges(mmu_idx)) { + return extract64(tcr, 37, 2); + } else if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + return 0; /* VTCR_EL2 */ + } else { + return extract32(tcr, 20, 1); + } +} + +static int aa64_va_parameter_tbid(uint64_t tcr, ARMMMUIdx mmu_idx) +{ + if (regime_has_2_ranges(mmu_idx)) { + return extract64(tcr, 51, 2); + } else if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + return 0; /* VTCR_EL2 */ + } else { + return extract32(tcr, 29, 1); + } +} + +ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, + ARMMMUIdx mmu_idx, bool data) { uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; - bool tbi, tbid, epd, hpd, using16k, using64k; - int select, tsz; + bool epd, hpd, using16k, using64k; + int select, tsz, tbi; =20 if (!regime_has_2_ranges(mmu_idx)) { select =3D 0; @@ -10248,11 +10270,9 @@ ARMVAParameters aa64_va_parameters_both(CPUARMStat= e *env, uint64_t va, using16k =3D extract32(tcr, 15, 1); if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { /* VTCR_EL2 */ - tbi =3D tbid =3D hpd =3D false; + hpd =3D false; } else { - tbi =3D extract32(tcr, 20, 1); hpd =3D extract32(tcr, 24, 1); - tbid =3D extract32(tcr, 29, 1); } epd =3D false; } else { @@ -10266,28 +10286,30 @@ ARMVAParameters aa64_va_parameters_both(CPUARMSta= te *env, uint64_t va, epd =3D extract32(tcr, 7, 1); using64k =3D extract32(tcr, 14, 1); using16k =3D extract32(tcr, 15, 1); - tbi =3D extract64(tcr, 37, 1); hpd =3D extract64(tcr, 41, 1); - tbid =3D extract64(tcr, 51, 1); } else { int tg =3D extract32(tcr, 30, 2); using16k =3D tg =3D=3D 1; using64k =3D tg =3D=3D 3; tsz =3D extract32(tcr, 16, 6); epd =3D extract32(tcr, 23, 1); - tbi =3D extract64(tcr, 38, 1); hpd =3D extract64(tcr, 42, 1); - tbid =3D extract64(tcr, 52, 1); } } tsz =3D MIN(tsz, 39); /* TODO: ARMv8.4-TTST */ tsz =3D MAX(tsz, 16); /* TODO: ARMv8.2-LVA */ =20 + /* Present TBI as a composite with TBID. */ + tbi =3D aa64_va_parameter_tbi(tcr, mmu_idx); + if (!data) { + tbi &=3D ~aa64_va_parameter_tbid(tcr, mmu_idx); + } + tbi =3D (tbi >> select) & 1; + return (ARMVAParameters) { .tsz =3D tsz, .select =3D select, .tbi =3D tbi, - .tbid =3D tbid, .epd =3D epd, .hpd =3D hpd, .using16k =3D using16k, @@ -10295,16 +10317,6 @@ ARMVAParameters aa64_va_parameters_both(CPUARMStat= e *env, uint64_t va, }; } =20 -ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, - ARMMMUIdx mmu_idx, bool data) -{ - ARMVAParameters ret =3D aa64_va_parameters_both(env, va, mmu_idx); - - /* Present TBI as a composite with TBID. */ - ret.tbi &=3D (data || !ret.tbid); - return ret; -} - #ifndef CONFIG_USER_ONLY static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx) @@ -12134,21 +12146,15 @@ static uint32_t rebuild_hflags_a64(CPUARMState *e= nv, int el, int fp_el, { uint32_t flags =3D rebuild_hflags_aprofile(env); ARMMMUIdx stage1 =3D stage_1_mmu_idx(mmu_idx); - ARMVAParameters p0 =3D aa64_va_parameters_both(env, 0, stage1); + uint64_t tcr =3D regime_tcr(env, mmu_idx)->raw_tcr; uint64_t sctlr; int tbii, tbid; =20 flags =3D FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); =20 /* Get control bits for tagged addresses. */ - if (regime_has_2_ranges(mmu_idx)) { - ARMVAParameters p1 =3D aa64_va_parameters_both(env, -1, stage1); - tbid =3D (p1.tbi << 1) | p0.tbi; - tbii =3D tbid & ~((p1.tbid << 1) | p0.tbid); - } else { - tbid =3D p0.tbi; - tbii =3D tbid & !p0.tbid; - } + tbid =3D aa64_va_parameter_tbi(tcr, mmu_idx); + tbii =3D tbid & ~aa64_va_parameter_tbid(tcr, mmu_idx); =20 flags =3D FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); flags =3D FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582290947; cv=none; d=zohomail.com; s=zohoarc; b=OifEStw6VeZzM5OKZZ8dS4XyfgSg/J4Fis48oou5XjmT08CTN42lXjaFrSW0wdkwRDXf4n3eoU3YGBPuR8GEKoCVa92Tq0k4hTc+h9Qy2ZOMlOWJrmmyE9VVpXiTB4lR1pvO798Nr/xHbRdhUTaK7jn4nKMRqnyXz8++2R0TJvE= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.07.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:07:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ab/N74S0Z/UQCYSVFfJ9xvcUWpUkXYgMA94Bf6u7eRk=; b=L4v/EB1Ngl2j8yRTvJHFsdxqKXMMA0m16HO58KAV6LQcWaN50dYVfmjxEEsdBNqzk0 mWQE1K5RzneQbQ5ZXdlCtFgFbThJ8A4VnR4mP1uD8Q34SvYOdu9s2tA2hjoRYmeLPdCG c4uKUkfFEYg664LXAJocA1jeZXLkTwUOXsjvUFJxeeAZ+8y1fIn7G9DhRo1qWqYXUg+k 3nBBL/PMPIYa1VVQgCH6q67SXVcMUfR/DnWd7q95YjyUDwPsm9CmW4FcO8oD7TRsaxfd lEvNHGRdmTCln5oU7Ttn372JwRBngRfegYV0hpYk2VgDoNxWPEDSnXcpMTjbFnyh8do3 c7Sw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ab/N74S0Z/UQCYSVFfJ9xvcUWpUkXYgMA94Bf6u7eRk=; b=QcQ/rdT/0U/hsxt2BGxbXerbZL6EmrroOMCzaJHNP88khGDE05Cl3DifTjMnE/14tw I6BKnuIqCzkNuwi/lZ/uJ+55JfYgTDmsSUsfJz9p8EpPQvLAH1KUlgOy0FtDe0qGxDtQ Li+9stQjEL400NwPyDO3V29w6ure/7m/tqBY7jXVH+43gCYJmmTuy3YT5ywKU26TcZGM glpuhKMQPcU57UtL87O2+EtMYoT4ZATA6jbXyLqiyj9Hfgbdt7YiJ4G+vCIG4PIKpE8k bdMMWOKGfkgYoc++ESSG1zIcgH1EywnyrAnZ3lqD0FA6uW3n3ka0ZHKRlCcMCDuwKGKE reug== X-Gm-Message-State: APjAAAXnj7G4gAZPIC/MVBytx0u7WcK5KzBq9X632eMC7NOzPp25S/Xv zITpgUIQwvCIbxBxWaodkZZ2tNwDp7qz8w== X-Google-Smtp-Source: APXvYqwlu91xSYTQC1Z/uqCcdeesQrJK8cC8deYiQZ/Bj9JWz4T5xcSEtucmU/VPBbGIvDFVnrQC9g== X-Received: by 2002:a1c:20d6:: with SMTP id g205mr3961010wmg.38.1582290479513; Fri, 21 Feb 2020 05:07:59 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/52] target/arm: Add _aa32_ to isar_feature functions testing 32-bit ID registers Date: Fri, 21 Feb 2020 13:07:02 +0000 Message-Id: <20200221130740.7583-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32e X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Enforce a convention that an isar_feature function that tests a 32-bit ID register always has _aa32_ in its name, and one that tests a 64-bit ID register always has _aa64_ in its name. We already follow this except for three cases: thumb_div, arm_div and jazelle, which all need _aa32_ adding. (As noted in the comment, isar_feature_aa32_fp16_arith() is an exception in that it currently tests ID_AA64PFR0_EL1, but will switch to MVFR1 once we've properly implemented FP16 for AArch32.) Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 20200214175116.9164-2-peter.maydell@linaro.org --- target/arm/cpu.h | 13 ++++++++++--- target/arm/internals.h | 2 +- linux-user/elfload.c | 4 ++-- target/arm/cpu.c | 6 ++++-- target/arm/helper.c | 2 +- target/arm/translate.c | 6 +++--- 6 files changed, 21 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e943ffe8a9a..37d40e57901 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3324,20 +3324,27 @@ static inline uint64_t *aa64_vfp_qreg(CPUARMState *= env, unsigned regno) /* Shared between translate-sve.c and sve_helper.c. */ extern const uint64_t pred_esz_masks[4]; =20 +/* + * Naming convention for isar_feature functions: + * Functions which test 32-bit ID registers should have _aa32_ in + * their name. Functions which test 64-bit ID registers should have + * _aa64_ in their name. + */ + /* * 32-bit feature tests via id registers. */ -static inline bool isar_feature_thumb_div(const ARMISARegisters *id) +static inline bool isar_feature_aa32_thumb_div(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) !=3D 0; } =20 -static inline bool isar_feature_arm_div(const ARMISARegisters *id) +static inline bool isar_feature_aa32_arm_div(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar0, ID_ISAR0, DIVIDE) > 1; } =20 -static inline bool isar_feature_jazelle(const ARMISARegisters *id) +static inline bool isar_feature_aa32_jazelle(const ARMISARegisters *id) { return FIELD_EX32(id->id_isar1, ID_ISAR1, JAZELLE) !=3D 0; } diff --git a/target/arm/internals.h b/target/arm/internals.h index 14328e3f7da..31aaa0eff87 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1091,7 +1091,7 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64= _t features, if ((features >> ARM_FEATURE_THUMB2) & 1) { valid |=3D CPSR_IT; } - if (isar_feature_jazelle(id)) { + if (isar_feature_aa32_jazelle(id)) { valid |=3D CPSR_J; } if (isar_feature_aa32_pan(id)) { diff --git a/linux-user/elfload.c b/linux-user/elfload.c index f3080a16358..b1a895f24ce 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -475,8 +475,8 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE(ARM_FEATURE_VFP3, ARM_HWCAP_ARM_VFPv3); GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); GET_FEATURE(ARM_FEATURE_VFP4, ARM_HWCAP_ARM_VFPv4); - GET_FEATURE_ID(arm_div, ARM_HWCAP_ARM_IDIVA); - GET_FEATURE_ID(thumb_div, ARM_HWCAP_ARM_IDIVT); + GET_FEATURE_ID(aa32_arm_div, ARM_HWCAP_ARM_IDIVA); + GET_FEATURE_ID(aa32_thumb_div, ARM_HWCAP_ARM_IDIVT); /* All QEMU's VFPv3 CPUs have 32 registers, see VFP_DREG in translate.= c. * Note that the ARM_HWCAP_ARM_VFPv3D16 bit is always the inverse of * ARM_HWCAP_ARM_VFPD32 (and so always clear for QEMU); it is unrelated diff --git a/target/arm/cpu.c b/target/arm/cpu.c index de733aceeb8..56f2ab865da 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1586,7 +1586,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * Presence of EL2 itself is ARM_FEATURE_EL2, and of the * Security Extensions is ARM_FEATURE_EL3. */ - assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(arm_div, cpu)= ); + assert(!tcg_enabled() || no_aa32 || + cpu_isar_feature(aa32_arm_div, cpu)); set_feature(env, ARM_FEATURE_LPAE); set_feature(env, ARM_FEATURE_V7); } @@ -1612,7 +1613,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) if (arm_feature(env, ARM_FEATURE_V6)) { set_feature(env, ARM_FEATURE_V5); if (!arm_feature(env, ARM_FEATURE_M)) { - assert(!tcg_enabled() || no_aa32 || cpu_isar_feature(jazelle, = cpu)); + assert(!tcg_enabled() || no_aa32 || + cpu_isar_feature(aa32_jazelle, cpu)); set_feature(env, ARM_FEATURE_AUXCR); } } diff --git a/target/arm/helper.c b/target/arm/helper.c index 8d0f6eca27b..9c02d5d6b8e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7396,7 +7396,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (arm_feature(env, ARM_FEATURE_LPAE)) { define_arm_cp_regs(cpu, lpae_cp_reginfo); } - if (cpu_isar_feature(jazelle, cpu)) { + if (cpu_isar_feature(aa32_jazelle, cpu)) { define_arm_cp_regs(cpu, jazelle_regs); } /* Slightly awkwardly, the OMAP and StrongARM cores need all of diff --git a/target/arm/translate.c b/target/arm/translate.c index 20f89ace2fd..93f028f256b 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -42,7 +42,7 @@ #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) /* currently all emulated v5 cores are also v5TE, so don't bother */ #define ENABLE_ARCH_5TE arm_dc_feature(s, ARM_FEATURE_V5) -#define ENABLE_ARCH_5J dc_isar_feature(jazelle, s) +#define ENABLE_ARCH_5J dc_isar_feature(aa32_jazelle, s) #define ENABLE_ARCH_6 arm_dc_feature(s, ARM_FEATURE_V6) #define ENABLE_ARCH_6K arm_dc_feature(s, ARM_FEATURE_V6K) #define ENABLE_ARCH_6T2 arm_dc_feature(s, ARM_FEATURE_THUMB2) @@ -9845,8 +9845,8 @@ static bool op_div(DisasContext *s, arg_rrr *a, bool = u) TCGv_i32 t1, t2; =20 if (s->thumb - ? !dc_isar_feature(thumb_div, s) - : !dc_isar_feature(arm_div, s)) { + ? !dc_isar_feature(aa32_thumb_div, s) + : !dc_isar_feature(aa32_arm_div, s)) { return false; } =20 --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582290804; cv=none; d=zohomail.com; s=zohoarc; b=iZCwZjJ6UFfT6tEfMMkZ53pIyDaU7mc0gjikRdWHTxSa2gcbCRZLyzV/D1saEx6/MNXgs/I4vXTLzo3XDv9y5sPBWcrC69JcqXA2HZk9r83kc2PwWCyS0DGkNwOV+HYVx9mIkZt0Vf+yY/KTaODBO4xlfCUvILJyRNpVrNk11kY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582290804; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WKYx4GPNYSXdP+wNoi6Rt9rVKRj/zD7o674eYcMYUY8=; b=gL3ncz9M7tQjqyj7f86fSBxEnsRXfGP6ERdnQfMygQf9l9Hx3HsCmVgOiO3lcGHa8aIBTnIR5I4sNQaHD8S/qZd1XexHmQ5oLfXy6B/XPWllLrXij9mkvoxUfLiWGdOO3k8QT+DbLBFfDzscsaL7h+row1Dl3PKQpkWJ26bQyj4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582290804071157.20827951757633; Fri, 21 Feb 2020 05:13:24 -0800 (PST) Received: from localhost ([::1]:57254 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j587O-0007xl-OF for importer@patchew.org; Fri, 21 Feb 2020 08:13:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56617) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582G-0006ou-6T for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582F-0002jX-3j for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:04 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:45251) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582E-0002ho-Td for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:03 -0500 Received: by mail-wr1-x435.google.com with SMTP id g3so1977739wrs.12 for ; Fri, 21 Feb 2020 05:08:02 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.07.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=WKYx4GPNYSXdP+wNoi6Rt9rVKRj/zD7o674eYcMYUY8=; b=wHr8YC4Ixy2MsWtlzAbJCt18Nsr2mwCKKb6VbSL87eHNEPDNf3MOddWEJmbsaUWq0p bUnylDfLLBJRzwIAXDytqNyuy6Yi/JRZzb9zDq06GcVvQVfxfUVRQwaQHCxRojIV9UZV wd5+dV3AIFOKvhbJvRzR1NdBZGR9I3a6f5xm7EBinIZw0Oop0171Q2X+iW4B/VEodqaS 8yT7ZkiZwqX39bafNmcVfF76A/ora0LDhYy4f+IyvDUx+x9JkGjRlmrdUxCjfjvRUrEl qnFDIoQ8U92lBsLOau3EI9i5qhdFZkLPYLMMO0BrnH5/eICl99q4zHERJfD+7FVhkV5x pMCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WKYx4GPNYSXdP+wNoi6Rt9rVKRj/zD7o674eYcMYUY8=; b=uTMYtBjVvh8e+WbRXZ0h5e0pk9fJ3+3M2PZcwD8odiKEx0rZbrxZDN0HtM2FH7eb+Q 6dciy7YcwQDJKDPphHFF6rm3UKOrmFQ8EdADZVfi2g3m2hA9KeEkoVPjSIwMxLaVYg2C LEpCrWCFFJHpM4gctqFQI3eM/e7NcoJ6hvIUyifsiIepfTiBdtWcLhRW3pRLVMhcUBLg lQnuymT5LMpPKZ80Vyn6KmjSAp2wWmrSHWKKw0FEr6RWYdspqxJedCq4xmgNZf21kCYC iPSLemZlTOjADtIyJvZBfoclxInJDvbU5V9cmJqgPmVvHq6jj5/s6ZFsf7l3lgsWnOCX 6K4g== X-Gm-Message-State: APjAAAXWbF1oxNB6Psu9Hg6Fh8fHfx/mUmN9ptnVAG/yCa310Lvhjs/B WyB6CT4slWHGFoApLoysPSlnEO0JxslDDQ== X-Google-Smtp-Source: APXvYqxYNfVFmAVZN9K4IgzF85pR7GqGQZFLChMg2EykQugmshFaAas27xDyI2x/gpqsLn+OhC7NYw== X-Received: by 2002:a5d:55d2:: with SMTP id i18mr46938212wrw.287.1582290481174; Fri, 21 Feb 2020 05:08:01 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/52] target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan Date: Fri, 21 Feb 2020 13:07:03 +0000 Message-Id: <20200221130740.7583-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::435 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In take_aarch32_exception(), we know we are dealing with a CPU that has AArch32, so the right isar_feature test is aa32_pan, not aa64_pan. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200214175116.9164-3-peter.maydell@linaro.org --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9c02d5d6b8e..ad2bfa9ef83 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8858,7 +8858,7 @@ static void take_aarch32_exception(CPUARMState *env, = int new_mode, env->elr_el[2] =3D env->regs[15]; } else { /* CPSR.PAN is normally preserved preserved unless... */ - if (cpu_isar_feature(aa64_pan, env_archcpu(env))) { + if (cpu_isar_feature(aa32_pan, env_archcpu(env))) { switch (new_el) { case 3: if (!arm_is_secure_below_el3(env)) { --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582291083; cv=none; d=zohomail.com; s=zohoarc; b=FBabv+Qu+MuVyaWmglU1rrMLZAHhE8TzIdvuPSZFHVLBse+Y64CQsYRYAyVKyNEn0jyTL7KEgYTziHgnlAu185FQGiVjm8xtyzlZwKFIDKG/NBQwQ7KtwxumPoLJe5AigfF1D6bkJMYBje1f1lwHPlcnq20qu8MWJDHUU+Obz94= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582291083; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=h5+A342D2iRjcWA3VICQY7RA9sDnarYqczi5siHyDGg=; b=W1Bx4pOeiaLKoXSTe6C6OOKXMtMNR+iw6A8SGqnYSteJUdgmgRtpd7xWYwvuUL2r/m7eB8kdjRdR8NcLm258jgWQaJCCQcGls8NG6Ik9ElN8dwlhxgwMJnLdsgpX5z+AQSc5v0cZLa+/0fn1JdgjiYmt9Y2qMWv48XVI4B2f/Dg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582291083346287.73478864677327; Fri, 21 Feb 2020 05:18:03 -0800 (PST) Received: from localhost ([::1]:57386 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58Bt-0006Ge-VI for importer@patchew.org; Fri, 21 Feb 2020 08:18:01 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56638) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582H-0006sV-EW for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582G-0002ks-3M for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:05 -0500 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:34596) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582F-0002k0-Ss for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:04 -0500 Received: by mail-wr1-x431.google.com with SMTP id n10so2019296wrm.1 for ; Fri, 21 Feb 2020 05:08:03 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=h5+A342D2iRjcWA3VICQY7RA9sDnarYqczi5siHyDGg=; b=SJ4YHADB8qITxhD0/V1SQ09SbxJ7d0BDYvVJ9vWgbZ2wEb+ntJWK6jR3CV6oAxVKiY O3+XOR88dPEV9YHZthnMxYO+CV8svltgHjL/sT8LczIXBwAbcw7VyztqS9Hnv83eGp8Q L/7DhiKSUceoS8c7hbz46R6MLmrdzHUyHtI0sqnY8o8tb7JDB08oQVv5Fq4mONGb0WtG /hTwlyhV+Xattv3OBUo8MMfhJPIAhYTzK6pCqWNPiPgHKSxQUXC9PT3HAjBvnVnIjw/A YKFl8gh2xLvpV8ES2nwf5iM2GRRJQKr30bT0bVCxq/byzPJOg62YFfRRmyS7/wJCbms/ e3pA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h5+A342D2iRjcWA3VICQY7RA9sDnarYqczi5siHyDGg=; b=KuwcaPUP/jONf8LSfc3pVH2UaSo24Z0fXE7mqeDig/1LqgOvmArbHqFywAeYTSRLSH tHNG26x5X+56ilm64uxBd7HpbgYhf6xPh7/PSJRueeW08ZlDzvqXdfavWW2P3qBVYlGw p9j5cyeWe8jgijEg3d262Mn8F/VorTfVpATdsSOu6jxF3uh2lpAfPr0e3qs0mevHl0tZ SYYhoYVIaUFGY6/LERF3+71q6CoYhb10nEUUdCH+EUcrqqiN92X6TIri3/bA6iXUOYot gtxp4ZKAFcNIrftoKVs1dgVmu4E9q5dab84bTVV/tXP8LeEklblMu1gi3GXTT1c0QqRC dpkw== X-Gm-Message-State: APjAAAXlUfCD78q4PyBpuUhnZB22ueZLmb6GD67FEN7jVjmqmZ34OjuL NXafcvdHSzKcrRVDAgBtPeTvO/q5+F41tw== X-Google-Smtp-Source: APXvYqxLdSYqjv24iEI9fHKQDkD1ESMif3uph7uJg4QgFydkLxKmTd++whEYXAxbWTFJJPAvq/JwoA== X-Received: by 2002:adf:b605:: with SMTP id f5mr46476770wre.383.1582290482505; Fri, 21 Feb 2020 05:08:02 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/52] target/arm: Add isar_feature_any_fp16 and document naming/usage conventions Date: Fri, 21 Feb 2020 13:07:04 +0000 Message-Id: <20200221130740.7583-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::431 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Our current usage of the isar_feature feature tests almost always uses an _aa32_ test when the code path is known to be AArch32 specific and an _aa64_ test when the code path is known to be AArch64 specific. There is just one exception: in the vfp_set_fpscr helper we check aa64_fp16 to determine whether the FZ16 bit in the FP(S)CR exists, but this code is also used for AArch32. There are other places in future where we're likely to want a general "does this feature exist for either AArch32 or AArch64" check (typically where architecturally the feature exists for both CPU states if it exists at all, but the CPU might be AArch32-only or AArch64-only, and so only have one set of ID registers). Introduce a new category of isar_feature_* functions: isar_feature_any_foo() should be tested when what we want to know is "does this feature exist for either AArch32 or AArch64", and always returns the logical OR of isar_feature_aa32_foo() and isar_feature_aa64_foo(). Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 20200214175116.9164-4-peter.maydell@linaro.org --- target/arm/cpu.h | 19 ++++++++++++++++++- target/arm/vfp_helper.c | 2 +- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 37d40e57901..7ccd65bdce3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3328,7 +3328,16 @@ extern const uint64_t pred_esz_masks[4]; * Naming convention for isar_feature functions: * Functions which test 32-bit ID registers should have _aa32_ in * their name. Functions which test 64-bit ID registers should have - * _aa64_ in their name. + * _aa64_ in their name. These must only be used in code where we + * know for certain that the CPU has AArch32 or AArch64 respectively + * or where the correct answer for a CPU which doesn't implement that + * CPU state is "false" (eg when generating A32 or A64 code, if adding + * system registers that are specific to that CPU state, for "should + * we let this system register bit be set" tests where the 32-bit + * flavour of the register doesn't have the bit, and so on). + * Functions which simply ask "does this feature exist at all" have + * _any_ in their name, and always return the logical OR of the _aa64_ + * and the _aa32_ function. */ =20 /* @@ -3660,6 +3669,14 @@ static inline bool isar_feature_aa64_bti(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) !=3D 0; } =20 +/* + * Feature tests for "does this exist in either 32-bit or 64-bit?" + */ +static inline bool isar_feature_any_fp16(const ARMISARegisters *id) +{ + return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 0ae7d4f34a9..930d6e747f6 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -185,7 +185,7 @@ uint32_t vfp_get_fpscr(CPUARMState *env) void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) { /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ - if (!cpu_isar_feature(aa64_fp16, env_archcpu(env))) { + if (!cpu_isar_feature(any_fp16, env_archcpu(env))) { val &=3D ~FPCR_FZ16; } =20 --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582291207; cv=none; d=zohomail.com; s=zohoarc; b=SfecyQ8MKN/jmNWbxlxHWvicXprE3HYsN+/3zuzuUa1m54o86O/yzrJo7dRrdc/M0uDsJt1e6Ou7WF3ATxFah5aKtHsXtC4E8rxa6r5DW01U9oQ6c9DSCBLM12e0Vifez94XvGES5yh7qRl5COAGGSafI5L35WmbVjV9CPsglng= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582291207; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HSTddCvvLAI7dOqdxIhz4N+v4u/0AHPDflmr9CxICTo=; b=NNnd4QnJbPQ40S0S+EqPn5UzVLz5D3jpN7WVVLkQnEQ0rFgahx1sDAeUew2lQGir+t9kxkGZUQMhc0vcgWxPq/W62u2wLOk8JuFKKrxAt6kcFZFFR0p/AJyhck7H6xsu2S1aJslLUNX9r6bet/CT4AyLPiFNETU5nQ6WkDG9tMc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582291207518119.7395449102138; Fri, 21 Feb 2020 05:20:07 -0800 (PST) Received: from localhost ([::1]:57434 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58Du-0001DR-F1 for importer@patchew.org; Fri, 21 Feb 2020 08:20:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56649) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582I-0006ut-7b for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:07 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582H-0002nO-4V for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:06 -0500 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:37632) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582G-0002lJ-TV for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:05 -0500 Received: by mail-wr1-x42c.google.com with SMTP id w15so1997303wru.4 for ; Fri, 21 Feb 2020 05:08:04 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=HSTddCvvLAI7dOqdxIhz4N+v4u/0AHPDflmr9CxICTo=; b=TPSstwLm7q0kCRtSyxH49Fo6OwJLN3Na+9lc2NJxWqVcWx/MVXcSOJh8gWSQkZHbie 9tJV+ocGqfm13kVOSglxRpU7n4peFnGfHAUfUZCbh0HRLT6lFCfYp6ngACwdZpQESnuN w9oNEqCEvSQsCpm73jd6iFrdjB+apP05fpd/v3JJiB/ecxiqHOOlgzsOxD5fDu263VaQ XGk03b7OmZvPZkSF3vV+KnLukW30ruhjZgYIQfHpnqhKSVQXSUNaytka71GC9oqy65vF K0P+9UkXX5FonyhegwxLWTBfnDlO9cGIJrO3Py7kiyTRZemZmtlIlwfttytrbcO84GZJ bFjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HSTddCvvLAI7dOqdxIhz4N+v4u/0AHPDflmr9CxICTo=; b=n7ZvR9/C+UEIIakpMoAvYnfYqFHZWCXtp25DpbX495lBjAlrhVbze5kE/uF0mMj7Rz oVy8t7+BzbpEhCEMmKfnxdZ4nt2NnZTyssngbdfzenutSWloUCIyi4k2AHwg3iB/qzY3 JhmKgYct6rPuJjsmSVOagwm0sJNs5+Vpcn71PJyCUew24OtT+7RklrmOCtup31Kittx1 cY4D9SLq+wO8V6KC+8XqQAhFhWLBXBoY7FuoVXev43ah+ywTXbp4vSmyh6MfGHRPzlbR vVZYCOWasfBAg5hSBQXm/C438SiC1y4DG8oFTKTfsqJD/Ytc/rCYUQDgtPb/RmsYm1Ib f9OA== X-Gm-Message-State: APjAAAUBizvMTfP/p0fGb+Obccza1AZrDg4srdVzdieMaUe8LtEfQfAD fkB6c5gLi7xkkoMT71PPp0rl+tdnW+p9EQ== X-Google-Smtp-Source: APXvYqwcRHFnChCUCi9ACzEeKAukCuIXpXA0dUjYq6SAEFI2LENkJ1FJxloUdHHt4Rhj6sUYZrpFHw== X-Received: by 2002:adf:a1d9:: with SMTP id v25mr47783904wrv.160.1582290483588; Fri, 21 Feb 2020 05:08:03 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/52] target/arm: Define and use any_predinv isar_feature test Date: Fri, 21 Feb 2020 13:07:05 +0000 Message-Id: <20200221130740.7583-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Instead of open-coding "ARM_FEATURE_AARCH64 ? aa64_predinv: aa32_predinv", define and use an any_predinv isar_feature test function. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 20200214175116.9164-5-peter.maydell@linaro.org --- target/arm/cpu.h | 5 +++++ target/arm/helper.c | 9 +-------- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7ccd65bdce3..ef0feb228ab 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3677,6 +3677,11 @@ static inline bool isar_feature_any_fp16(const ARMIS= ARegisters *id) return isar_feature_aa64_fp16(id) || isar_feature_aa32_fp16_arith(id); } =20 +static inline bool isar_feature_any_predinv(const ARMISARegisters *id) +{ + return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index ad2bfa9ef83..ab36f33b719 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7721,14 +7721,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) #endif /*CONFIG_USER_ONLY*/ #endif =20 - /* - * While all v8.0 cpus support aarch64, QEMU does have configurations - * that do not set ID_AA64ISAR1, e.g. user-only qemu-arm -cpu max, - * which will set ID_ISAR6. - */ - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64) - ? cpu_isar_feature(aa64_predinv, cpu) - : cpu_isar_feature(aa32_predinv, cpu)) { + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } =20 --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582291062; cv=none; d=zohomail.com; s=zohoarc; b=cLvQxsyo209VixIciqE8GBFe70XykaEV/OlOhIDu4b4sL+eOdFiI+i411xUH4RrDX4qoUn/meHrcSnb8OwPjcFi5xasXonlyXCzt6386rBKMan7LMx9QoA+9LeOl2h8B/wstpnB7DoufT5rI1dT/ty7yK2c3z07m8DkdelEVLs4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582291062; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8bdHdi62p5PzPAd0CdOGxqVtsuzmqbR0T0M8VLe4aj4=; b=Flgri58S1DNUhNFgButA8n7LIxqqxj5+pBNq4UtBIhE/IprF2L9RH8hYpUWbquwnrCY6aNL7xPguZMIzPaPAGfGGP8LE2zK7gR+mqziK/1p0adMLchwMfDFXujmanJNcd+KKuJbpBoInGM23ClmrE8n14etvL2H5o/HauCFNjTk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582291061914441.0448041803627; Fri, 21 Feb 2020 05:17:41 -0800 (PST) Received: from localhost ([::1]:57376 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58BY-0005QH-QW for importer@patchew.org; Fri, 21 Feb 2020 08:17:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56669) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582K-00071b-Gd for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582I-0002pq-QB for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:08 -0500 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:39765) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582I-0002oy-J2 for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:06 -0500 Received: by mail-wr1-x443.google.com with SMTP id y11so1995631wrt.6 for ; Fri, 21 Feb 2020 05:08:06 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8bdHdi62p5PzPAd0CdOGxqVtsuzmqbR0T0M8VLe4aj4=; b=nNkUe5L7XNgCNJYsr+LNVUTzdRO1VHn2BJnWzNthWjvcRXoWe+vuoNfiPERXua08P6 FMeQoXNLMtVmtl9MvDXlG/rC5b1rFJ8gmwtxdfn1usZXFtWRlfue2JptzLjhMJc8agUG pwTzA6mFCy99xCkB4s8LyifPcdz7tnF9Lx2W3WzQlm8NAhILOfga1cdsJxl2UvBIhlJl Omnn1SVjBkbnbmXq5Iyu+UIPcFGDanJEGFSnoRt0mGrftVvu1xNQ6JbNRL/wcwHJ976y HvXnMl7BFfqbZ7yIHOMOfTO7PblF7OecV668vFuJHqVAxJ8YqMGiowjCuYi8GRU1prnm OwRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8bdHdi62p5PzPAd0CdOGxqVtsuzmqbR0T0M8VLe4aj4=; b=BbDiOI2jMA1teBGsTcJ6MCM2KemHk33brYpCCfoPREpBjPuIBHTSNbQJ3Lr0vhN5DL GPGYckWBnZkBaHPyX22NaJMHG3HOJU5Qfp1mk0fGWaRaVsKWy06Y5/UpZnwCqQNHHCf+ xeCQesSBSQq2N1N9IUnqgeJ+XkhEZatpfKTPG1WdCrYN++gHAxy28Jd1abs9ngWt9ZIJ 8jrVd2USGpjKnSN//DGKlziavFzMVBoS3xjgeVeOzjdOlSetBAYiNAfaOrg3f3GlVBA5 z6N/N0iUe1hg7sLK77fuDv+egW2aHodcEkAy3hB08V8pJaUa02HJ7QMZ9kQzOSbCnXIr XQqA== X-Gm-Message-State: APjAAAU9XXnUye/VXK+cwzhAHjMCncWFqFwJbO9r4/skK21iP04vMzlf lCZBzZ+TBd6oqFoYOARENN0Zq2nd//5L6Q== X-Google-Smtp-Source: APXvYqyZGOp6lCNV6Ciu/5lSYz81JU03rAsqg1vhtfYSjT01XM3m31T7ef469ZRMtUDyTdyWnecZgg== X-Received: by 2002:a5d:4f8a:: with SMTP id d10mr22577212wru.143.1582290484848; Fri, 21 Feb 2020 05:08:04 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/52] target/arm: Factor out PMU register definitions Date: Fri, 21 Feb 2020 13:07:06 +0000 Message-Id: <20200221130740.7583-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Pull the code that defines the various PMU registers out into its own function, matching the pattern we have already for the debug registers. Apart from one style fix to a multi-line comment, this is purely movement of code with no changes to it. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 20200214175116.9164-6-peter.maydell@linaro.org --- target/arm/helper.c | 158 +++++++++++++++++++++++--------------------- 1 file changed, 82 insertions(+), 76 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ab36f33b719..cb2f4d8bbdb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6317,6 +6317,87 @@ static void define_debug_regs(ARMCPU *cpu) } } =20 +static void define_pmu_regs(ARMCPU *cpu) +{ + /* + * v7 performance monitor control register: same implementor + * field as main ID register, and we implement four counters in + * addition to the cycle count register. + */ + unsigned int i, pmcrn =3D 4; + ARMCPRegInfo pmcr =3D { + .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 =3D 0= , .opc2 =3D 0, + .access =3D PL0_RW, + .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcr), + .accessfn =3D pmreg_access, .writefn =3D pmcr_write, + .raw_writefn =3D raw_write, + }; + ARMCPRegInfo pmcr64 =3D { + .name =3D "PMCR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 0, + .access =3D PL0_RW, .accessfn =3D pmreg_access, + .type =3D ARM_CP_IO, + .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), + .resetvalue =3D (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT), + .writefn =3D pmcr_write, .raw_writefn =3D raw_write, + }; + define_one_arm_cp_reg(cpu, &pmcr); + define_one_arm_cp_reg(cpu, &pmcr64); + for (i =3D 0; i < pmcrn; i++) { + char *pmevcntr_name =3D g_strdup_printf("PMEVCNTR%d", i); + char *pmevcntr_el0_name =3D g_strdup_printf("PMEVCNTR%d_EL0", i); + char *pmevtyper_name =3D g_strdup_printf("PMEVTYPER%d", i); + char *pmevtyper_el0_name =3D g_strdup_printf("PMEVTYPER%d_EL0", i); + ARMCPRegInfo pmev_regs[] =3D { + { .name =3D pmevcntr_name, .cp =3D 15, .crn =3D 14, + .crm =3D 8 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7, + .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn, + .accessfn =3D pmreg_access }, + { .name =3D pmevcntr_el0_name, .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 8 | (3 & (i = >> 3)), + .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc= ess, + .type =3D ARM_CP_IO, + .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn, + .raw_readfn =3D pmevcntr_rawread, + .raw_writefn =3D pmevcntr_rawwrite }, + { .name =3D pmevtyper_name, .cp =3D 15, .crn =3D 14, + .crm =3D 12 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7, + .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, + .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_writefn, + .accessfn =3D pmreg_access }, + { .name =3D pmevtyper_el0_name, .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 12 | (3 & (i= >> 3)), + .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc= ess, + .type =3D ARM_CP_IO, + .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_writefn, + .raw_writefn =3D pmevtyper_rawwrite }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, pmev_regs); + g_free(pmevcntr_name); + g_free(pmevcntr_el0_name); + g_free(pmevtyper_name); + g_free(pmevtyper_el0_name); + } + if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >=3D 4 && + FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf) { + ARMCPRegInfo v81_pmu_regs[] =3D { + { .name =3D "PMCEID2", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 4, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .resetvalue =3D extract64(cpu->pmceid0, 32, 32) }, + { .name =3D "PMCEID3", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 5, + .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, + .resetvalue =3D extract64(cpu->pmceid1, 32, 32) }, + REGINFO_SENTINEL + }; + define_arm_cp_regs(cpu, v81_pmu_regs); + } +} + /* We don't know until after realize whether there's a GICv3 * attached, and that is what registers the gicv3 sysregs. * So we have to fill in the GIC fields in ID_PFR/ID_PFR1_EL1/ID_AA64PFR0_= EL1 @@ -6859,67 +6940,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, pmovsset_cp_reginfo); } if (arm_feature(env, ARM_FEATURE_V7)) { - /* v7 performance monitor control register: same implementor - * field as main ID register, and we implement four counters in - * addition to the cycle count register. - */ - unsigned int i, pmcrn =3D 4; - ARMCPRegInfo pmcr =3D { - .name =3D "PMCR", .cp =3D 15, .crn =3D 9, .crm =3D 12, .opc1 = =3D 0, .opc2 =3D 0, - .access =3D PL0_RW, - .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .fieldoffset =3D offsetoflow32(CPUARMState, cp15.c9_pmcr), - .accessfn =3D pmreg_access, .writefn =3D pmcr_write, - .raw_writefn =3D raw_write, - }; - ARMCPRegInfo pmcr64 =3D { - .name =3D "PMCR_EL0", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D 0, - .access =3D PL0_RW, .accessfn =3D pmreg_access, - .type =3D ARM_CP_IO, - .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), - .resetvalue =3D (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHI= FT), - .writefn =3D pmcr_write, .raw_writefn =3D raw_write, - }; - define_one_arm_cp_reg(cpu, &pmcr); - define_one_arm_cp_reg(cpu, &pmcr64); - for (i =3D 0; i < pmcrn; i++) { - char *pmevcntr_name =3D g_strdup_printf("PMEVCNTR%d", i); - char *pmevcntr_el0_name =3D g_strdup_printf("PMEVCNTR%d_EL0", = i); - char *pmevtyper_name =3D g_strdup_printf("PMEVTYPER%d", i); - char *pmevtyper_el0_name =3D g_strdup_printf("PMEVTYPER%d_EL0"= , i); - ARMCPRegInfo pmev_regs[] =3D { - { .name =3D pmevcntr_name, .cp =3D 15, .crn =3D 14, - .crm =3D 8 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & = 7, - .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_write= fn, - .accessfn =3D pmreg_access }, - { .name =3D pmevcntr_el0_name, .state =3D ARM_CP_STATE_AA6= 4, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 8 | (3 &= (i >> 3)), - .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg= _access, - .type =3D ARM_CP_IO, - .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_write= fn, - .raw_readfn =3D pmevcntr_rawread, - .raw_writefn =3D pmevcntr_rawwrite }, - { .name =3D pmevtyper_name, .cp =3D 15, .crn =3D 14, - .crm =3D 12 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i &= 7, - .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, - .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_wri= tefn, - .accessfn =3D pmreg_access }, - { .name =3D pmevtyper_el0_name, .state =3D ARM_CP_STATE_AA= 64, - .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 12 | (3 = & (i >> 3)), - .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg= _access, - .type =3D ARM_CP_IO, - .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_wri= tefn, - .raw_writefn =3D pmevtyper_rawwrite }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, pmev_regs); - g_free(pmevcntr_name); - g_free(pmevcntr_el0_name); - g_free(pmevtyper_name); - g_free(pmevtyper_el0_name); - } ARMCPRegInfo clidr =3D { .name =3D "CLIDR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 1, .opc2 =3D 1, @@ -6930,24 +6950,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &clidr); define_arm_cp_regs(cpu, v7_cp_reginfo); define_debug_regs(cpu); + define_pmu_regs(cpu); } else { define_arm_cp_regs(cpu, not_v7_cp_reginfo); } - if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >=3D 4 && - FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf) { - ARMCPRegInfo v81_pmu_regs[] =3D { - { .name =3D "PMCEID2", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 4, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .resetvalue =3D extract64(cpu->pmceid0, 32, 32) }, - { .name =3D "PMCEID3", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 5, - .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, - .resetvalue =3D extract64(cpu->pmceid1, 32, 32) }, - REGINFO_SENTINEL - }; - define_arm_cp_regs(cpu, v81_pmu_regs); - } if (arm_feature(env, ARM_FEATURE_V8)) { /* AArch64 ID registers, which all have impdef reset values. * Note that within the ID register ranges the unused slots --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582291087; cv=none; d=zohomail.com; s=zohoarc; b=XBIwrLWOZTS+WPtKbt1tp7ManC5Y4LAiWXEEG4jfxuxcPDEbTd68GRt3z3dOchYvpF0NypaVhVWLm1wEYq7nWRKPgAq0CBvPfR4x20VBgXqLXC+SByh9HiFVQEz/IuMSMYzjk/MWHA6lkuf+fbuPc/ZwdVzL2skFZof5fjXnsSM= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ixHvPZovlXIaICo5d8Ua17czbh6t9v18RdBxgNVk+74=; b=uiK6Yz0QMBMXZmWJxR4OR/8fFbi/FJCDi7v5Zu+MEdW90Rnc5cXgh/HQvbBkyMyAJP SQhrlqwSCEKRCXYcs4mhWQ6OzCoe9qI3BPqozeEQbLNE44Tz79BpgRhUqslqymgoVz6+ T2jouRDPO0jJZ6NjNOMuIGfmok80fn3TME4VORWKtz5HAxU9U0PxIyEm2/nFFLmCdzJk EYdOD9KrdI9sEpDaS5Kg+gy90/i/koMuiDdmABRWI1W0qariE6fPP8y55QE+HXRms3PS wMRCwr2ZbqiS22mtN1sM6uK3eGr9S0teeO3BfdOb3qTXuzIpe7e7rDkYCSlgZhtw4uXn XIcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ixHvPZovlXIaICo5d8Ua17czbh6t9v18RdBxgNVk+74=; b=uWIlMEAU+DsMiV9+bxnITT6MXc9g5vrjoY+hra2n9goIgScfVpOo6785PvEW9IBAvu CfwVtRpYOKimxE9curKSnciGvfWfGlc5fZcwX5twu208jmKkq9T4KS7SQ4tQGBqpfF6M 4NJ8TT3+a8D9w/19bnvbuO0taoR92RUeg3zKuISMNURAU+h3+W53BkMMBWt34pS/nMjO HTUPCepkskpouaofzhJDu2CaSBIAL/ALHoN0eKbBsR/GeoPKbxux+2peKgJlBdlthFbj Yad80EX7fNQnjGUvRxzOKGNB0T8FmmbVskgWecXAzCP4a4h6ClHUa1fZTGW/Wd3paNGP GjtQ== X-Gm-Message-State: APjAAAW3cMzwIo2UZhEGGfCq9c9X9GcIj550LjLZDJUiIIbkn+9DPfDC e07nl6bMCvsjPJnvjDbpjxP7mTcHG0RcXg== X-Google-Smtp-Source: APXvYqyFpcQXMa3fdTprKsXLnd7RXSqzK1D73mCS2Jh6TFBbzf9krhwhb+cwk+9hDLmEFiyRFCr+Gw== X-Received: by 2002:a5d:4085:: with SMTP id o5mr48163725wrp.321.1582290485753; Fri, 21 Feb 2020 05:08:05 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/52] target/arm: Add and use FIELD definitions for ID_AA64DFR0_EL1 Date: Fri, 21 Feb 2020 13:07:07 +0000 Message-Id: <20200221130740.7583-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Add FIELD() definitions for the ID_AA64DFR0_EL1 and use them where we currently have hard-coded bit values. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 20200214175116.9164-7-peter.maydell@linaro.org --- target/arm/cpu.h | 10 ++++++++++ target/arm/cpu.c | 2 +- target/arm/helper.c | 6 +++--- 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ef0feb228ab..081955094dc 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1821,6 +1821,16 @@ FIELD(ID_AA64MMFR2, BBM, 52, 4) FIELD(ID_AA64MMFR2, EVT, 56, 4) FIELD(ID_AA64MMFR2, E0PD, 60, 4) =20 +FIELD(ID_AA64DFR0, DEBUGVER, 0, 4) +FIELD(ID_AA64DFR0, TRACEVER, 4, 4) +FIELD(ID_AA64DFR0, PMUVER, 8, 4) +FIELD(ID_AA64DFR0, BRPS, 12, 4) +FIELD(ID_AA64DFR0, WRPS, 20, 4) +FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) +FIELD(ID_AA64DFR0, PMSVER, 32, 4) +FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) +FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) + FIELD(ID_DFR0, COPDBG, 0, 4) FIELD(ID_DFR0, COPSDBG, 4, 4) FIELD(ID_DFR0, MMAPDBG, 8, 4) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 56f2ab865da..12bf9688007 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1718,7 +1718,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) cpu); #endif } else { - cpu->id_aa64dfr0 &=3D ~0xf00; + cpu->id_aa64dfr0 =3D FIELD_DP64(cpu->id_aa64dfr0, ID_AA64DFR0, PMU= VER, 0); cpu->id_dfr0 &=3D ~(0xf << 24); cpu->pmceid0 =3D 0; cpu->pmceid1 =3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index cb2f4d8bbdb..f183ac5cbfe 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6266,9 +6266,9 @@ static void define_debug_regs(ARMCPU *cpu) * check that if they both exist then they agree. */ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - assert(extract32(cpu->id_aa64dfr0, 12, 4) =3D=3D brps); - assert(extract32(cpu->id_aa64dfr0, 20, 4) =3D=3D wrps); - assert(extract32(cpu->id_aa64dfr0, 28, 4) =3D=3D ctx_cmps); + assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, BRPS) =3D=3D brps= ); + assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, WRPS) =3D=3D wrps= ); + assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) =3D=3D = ctx_cmps); } =20 define_one_arm_cp_reg(cpu, &dbgdidr); --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582291344; cv=none; d=zohomail.com; s=zohoarc; b=EOEP0jVPOzwfwpXkA8Bik/w0DiShS/BE1gux62ybpY7WFycAV7dN9YQ9A2b97nAtSx6WzGcCfgj/Srh4R7C7YJzKpgYfGVScpfzfsmMczVTMIRCgKQ/sMrc1u1PKIfRYqiGVlsxhiYMyJ9HuHpoEJJqKk/iYwq9iZGvm3rZfXlU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582291344; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fKZcomZs0VaBPiSTJ1VeQVN6QYLYuVLclLOmNVPEHRo=; b=ncv1nkocbAfOv/SfyVGiFThug/V1C+xaYJpXIwIenbWzYE9rqNHWyj0rAva9BBLNfEaPhSLuvWNJM0yDlJHFPzjpAp0vCTk9X0nqgr3FdKuW9GsHbA22OuNutOHtvVXzHtXfQ1RTzKPE+wSgDBenbgNkKMPCIvsCvcr/YF4goAk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582291344537142.4651745022354; Fri, 21 Feb 2020 05:22:24 -0800 (PST) Received: from localhost ([::1]:57502 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58G7-0004ie-Fn for importer@patchew.org; Fri, 21 Feb 2020 08:22:23 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56679) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582L-00074h-LL for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:10 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582K-0002s8-D2 for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:09 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:39767) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582K-0002qx-75 for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:08 -0500 Received: by mail-wr1-x444.google.com with SMTP id y11so1995803wrt.6 for ; Fri, 21 Feb 2020 05:08:08 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=fKZcomZs0VaBPiSTJ1VeQVN6QYLYuVLclLOmNVPEHRo=; b=UpwcwZ5oKzwuT5HkeJYNWfxQrNjf/7ouqqjBLbV6obmHPLx1PkG+hJSi3+GU0GFtIL 4wvD6+IY99QtlkErBuzl/5JGvt5fcvRdPg9ELqPUdXGOfg/7JJFvieMvB1664A4EZ8j0 J13tTSTk1AcMNal51ax30iu14VX5zNhbzSpfT7WMZYfEHKw2d9XJ00r5cTe+WSSfNdOf AmgH3E7oeDNofFgwymrNOz8LL0as3GVlxGS8zMedRBl48kywclsF30nTaJqy0CfU5D2o CoDZ5XTXO9QU2eejtSPV9VPLNoAVvJutd2avPR49fgj5UTLOD1eiSkb8w0xwO0m5Zunc /Evg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fKZcomZs0VaBPiSTJ1VeQVN6QYLYuVLclLOmNVPEHRo=; b=CVtvD46uokVt/5VsyXxPAaIO27AzUhLnwZ+01h3ycF6wX8jHnMkwYblUWF3rfSZwGE NPCYvZXO8GrBeMB8cV0XxxehGMXd3Fv/KHdhsxiqxQOVGpSqZfGCYPAIGr2ZUWHHORd7 0eQ/6lfTUABv3gy58S8QNVRjVf6KSP0HRzU2nqdDy96TqPDVyP7DEYkzhOmAer8jdxBP h6wpECpyO/PDEr14e6K/StbsVwBoM/j2sLoHo/E63mf4neEZfZaHTWJdCZH/GlqWolg9 Zwq2GTdZp4DUrdXoXCjEvMBJaPVqzNdgh8JFRFSrefHC53nIUPHxI/BP1rC3OzsXAVVl 4KLg== X-Gm-Message-State: APjAAAVEZVtt9fas9SccZ6iyoeNNVm6keBXCG6n0lO0fQxwTOzwFm1HJ ktERJx/EL4THVvp3+KeSJe8KB9K3GN098g== X-Google-Smtp-Source: APXvYqwjpscEU5D7ns72kwjIMNMLfsgb7mpj6jeOYEYTnwJeLMAsHXOUD+xURLO0OQSd5+/B07diXw== X-Received: by 2002:a5d:6a52:: with SMTP id t18mr46749984wrw.335.1582290486982; Fri, 21 Feb 2020 05:08:06 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/52] target/arm: Use FIELD macros for clearing ID_DFR0 PERFMON field Date: Fri, 21 Feb 2020 13:07:08 +0000 Message-Id: <20200221130740.7583-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) We already define FIELD macros for ID_DFR0, so use them in the one place where we're doing direct bit value manipulation. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 20200214175116.9164-8-peter.maydell@linaro.org --- target/arm/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 12bf9688007..1024f506c51 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1719,7 +1719,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) #endif } else { cpu->id_aa64dfr0 =3D FIELD_DP64(cpu->id_aa64dfr0, ID_AA64DFR0, PMU= VER, 0); - cpu->id_dfr0 &=3D ~(0xf << 24); + cpu->id_dfr0 =3D FIELD_DP32(cpu->id_dfr0, ID_DFR0, PERFMON, 0); cpu->pmceid0 =3D 0; cpu->pmceid1 =3D 0; } --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582291074; cv=none; d=zohomail.com; s=zohoarc; b=nPIDUpAyTbGSvazkDPi0mcYLurFc2YZQ7dkzwhwidg2CTzUiKvEcv73EeQLtGc+nj4DiSmFOrkv1F2IFqc+zPmOIGtSNPBCjL9qqmYy48lUYrY+0wYwCCQd3vElSZWA398qEQFCqRlIvDtoc+EvUu0FPaLMXrPyE/MVUcWIfZLQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582291074; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HdQJL7/rEvscwaJjQVOtW65DO3G59LUkNq7ToMdEFXg=; b=iREqzUnuiPu844ymjoy5FDKNyKTh2wHDtkZZBfzlm34PyOq76z3PVLOS1bD/rVP//QdqZqPJxUgx3QQ5JxqQ1Yxdr758P4Xh1rFQsGHq1NYcDNcOi3q3wFPC187wR+VEMrJ3tMaW8QVflWwHJsTLeg7ko7XIvd7tQ5e6EZwYOQc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582291074781946.8552746316826; Fri, 21 Feb 2020 05:17:54 -0800 (PST) Received: from localhost ([::1]:57382 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58Bl-0005vB-LK for importer@patchew.org; Fri, 21 Feb 2020 08:17:53 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56700) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582N-0007AB-L2 for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:13 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582L-0002tr-UU for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:11 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:43937) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582L-0002sx-N1 for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:09 -0500 Received: by mail-wr1-x436.google.com with SMTP id r11so1986770wrq.10 for ; Fri, 21 Feb 2020 05:08:09 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=HdQJL7/rEvscwaJjQVOtW65DO3G59LUkNq7ToMdEFXg=; b=PHGePh533ZlG4TMeTVkhl+XDqvlsBCFUS2e6vh7/5AR3sQfR4jc+B3CKXVB4oF3wN3 34XpEXH1lmWqLuoTqgFmnWo5uhORIxNRVJ0quFrTMpzTf7wQiN6YIID7oCE84WSSppYh CoBhkZO97Xb/gcmrZpsi+gIlsYMs/O5nfoFlTSK8oHrBBIM4uimWDPbyG5A/m7PJ9VdY i2tikOANJV85ctPIMA9fSj7FBz7T7tKxAwM5ze6lEhaobWSRoRUL8H5VCo/wppRAURMZ p006EPT/qKr08P/mrn1p7g0PyqQSQiF2W6XU8m0sdmrCK21Kj4yOES7rZwGP2X58QNq8 uAlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HdQJL7/rEvscwaJjQVOtW65DO3G59LUkNq7ToMdEFXg=; b=TGzdJqZrq6+PR9ZbzxCSRWdIN69NGBvfJCRSHe6p3Hj1wp9OC/G8jCwwIh5PorHbyN 3FvjBcFsvSqKBxtKtOblAGCmOYce10bmlAAplxV9u/OZQDRFTFgIjqD11BW7MWB1BHlX MUnQa+FIz3EWvKj9alCvs8fYbC+tYYw7oyOe0pYmMGOJsQp0L4e8M1LkkvFAJiwWdcmu YAI26lYyDs90LbcKALTu6XNiYYX4ccY0foQ2GdcU1p8rb4xpv63hdqlIAfzmsScGU6bA ivizjBNXKoX7haF7nAUJSjSZ7vApCODf20SRkSoZ74rRVxIf++4T5HteEZVGK7j4Sjna 7CqA== X-Gm-Message-State: APjAAAXBzcNyX3C5xz4Edzp5/eP1xIMo4SvaVDrMPiBuc7c+LvA4AFiV GVJroytQ7Zm+g0zU9qfz9I/pTsgFbeeJHg== X-Google-Smtp-Source: APXvYqx6MxXJpz6bcRNEFVvaU3Y+jbpE64HnEesIQLoLOb3MEzVhBJdPGxF+NuO3y9+Va2IdqFXAmg== X-Received: by 2002:a5d:53c1:: with SMTP id a1mr47222119wrw.373.1582290488064; Fri, 21 Feb 2020 05:08:08 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/52] target/arm: Define an aa32_pmu_8_1 isar feature test function Date: Fri, 21 Feb 2020 13:07:09 +0000 Message-Id: <20200221130740.7583-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::436 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Instead of open-coding a check on the ID_DFR0 PerfMon ID register field, create a standardly-named isar_feature for "does AArch32 have a v8.1 PMUv3" and use it. This entails moving the id_dfr0 field into the ARMISARegisters struct. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 20200214175116.9164-9-peter.maydell@linaro.org --- target/arm/cpu.h | 9 ++++++++- hw/intc/armv7m_nvic.c | 2 +- target/arm/cpu.c | 28 ++++++++++++++-------------- target/arm/cpu64.c | 6 +++--- target/arm/helper.c | 5 ++--- 5 files changed, 28 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 081955094dc..6c6088eb587 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -865,6 +865,7 @@ struct ARMCPU { uint32_t mvfr0; uint32_t mvfr1; uint32_t mvfr2; + uint32_t id_dfr0; uint64_t id_aa64isar0; uint64_t id_aa64isar1; uint64_t id_aa64pfr0; @@ -880,7 +881,6 @@ struct ARMCPU { uint32_t reset_sctlr; uint32_t id_pfr0; uint32_t id_pfr1; - uint32_t id_dfr0; uint64_t pmceid0; uint64_t pmceid1; uint32_t id_afr0; @@ -3500,6 +3500,13 @@ static inline bool isar_feature_aa32_ats1e1(const AR= MISARegisters *id) return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >=3D 2; } =20 +static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) +{ + /* 0xf means "non-standard IMPDEF PMU" */ + return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >=3D 4 && + FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; +} + /* * 64-bit feature tests via id registers. */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index f9e0eeaace6..5a403fc9704 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1227,7 +1227,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) case 0xd44: /* PFR1. */ return cpu->id_pfr1; case 0xd48: /* DFR0. */ - return cpu->id_dfr0; + return cpu->isar.id_dfr0; case 0xd4c: /* AFR0. */ return cpu->id_afr0; case 0xd50: /* MMFR0. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1024f506c51..b85040d36bc 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1719,7 +1719,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) #endif } else { cpu->id_aa64dfr0 =3D FIELD_DP64(cpu->id_aa64dfr0, ID_AA64DFR0, PMU= VER, 0); - cpu->id_dfr0 =3D FIELD_DP32(cpu->id_dfr0, ID_DFR0, PERFMON, 0); + cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFM= ON, 0); cpu->pmceid0 =3D 0; cpu->pmceid1 =3D 0; } @@ -1957,7 +1957,7 @@ static void arm1136_r2_initfn(Object *obj) cpu->reset_sctlr =3D 0x00050078; cpu->id_pfr0 =3D 0x111; cpu->id_pfr1 =3D 0x1; - cpu->id_dfr0 =3D 0x2; + cpu->isar.id_dfr0 =3D 0x2; cpu->id_afr0 =3D 0x3; cpu->id_mmfr0 =3D 0x01130003; cpu->id_mmfr1 =3D 0x10030302; @@ -1989,7 +1989,7 @@ static void arm1136_initfn(Object *obj) cpu->reset_sctlr =3D 0x00050078; cpu->id_pfr0 =3D 0x111; cpu->id_pfr1 =3D 0x1; - cpu->id_dfr0 =3D 0x2; + cpu->isar.id_dfr0 =3D 0x2; cpu->id_afr0 =3D 0x3; cpu->id_mmfr0 =3D 0x01130003; cpu->id_mmfr1 =3D 0x10030302; @@ -2022,7 +2022,7 @@ static void arm1176_initfn(Object *obj) cpu->reset_sctlr =3D 0x00050078; cpu->id_pfr0 =3D 0x111; cpu->id_pfr1 =3D 0x11; - cpu->id_dfr0 =3D 0x33; + cpu->isar.id_dfr0 =3D 0x33; cpu->id_afr0 =3D 0; cpu->id_mmfr0 =3D 0x01130003; cpu->id_mmfr1 =3D 0x10030302; @@ -2052,7 +2052,7 @@ static void arm11mpcore_initfn(Object *obj) cpu->ctr =3D 0x1d192992; /* 32K icache 32K dcache */ cpu->id_pfr0 =3D 0x111; cpu->id_pfr1 =3D 0x1; - cpu->id_dfr0 =3D 0; + cpu->isar.id_dfr0 =3D 0; cpu->id_afr0 =3D 0x2; cpu->id_mmfr0 =3D 0x01100103; cpu->id_mmfr1 =3D 0x10020302; @@ -2084,7 +2084,7 @@ static void cortex_m3_initfn(Object *obj) cpu->pmsav7_dregion =3D 8; cpu->id_pfr0 =3D 0x00000030; cpu->id_pfr1 =3D 0x00000200; - cpu->id_dfr0 =3D 0x00100000; + cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x00000030; cpu->id_mmfr1 =3D 0x00000000; @@ -2115,7 +2115,7 @@ static void cortex_m4_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000000; cpu->id_pfr0 =3D 0x00000030; cpu->id_pfr1 =3D 0x00000200; - cpu->id_dfr0 =3D 0x00100000; + cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x00000030; cpu->id_mmfr1 =3D 0x00000000; @@ -2146,7 +2146,7 @@ static void cortex_m7_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000040; cpu->id_pfr0 =3D 0x00000030; cpu->id_pfr1 =3D 0x00000200; - cpu->id_dfr0 =3D 0x00100000; + cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x00100030; cpu->id_mmfr1 =3D 0x00000000; @@ -2179,7 +2179,7 @@ static void cortex_m33_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000040; cpu->id_pfr0 =3D 0x00000030; cpu->id_pfr1 =3D 0x00000210; - cpu->id_dfr0 =3D 0x00200000; + cpu->isar.id_dfr0 =3D 0x00200000; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x00101F40; cpu->id_mmfr1 =3D 0x00000000; @@ -2231,7 +2231,7 @@ static void cortex_r5_initfn(Object *obj) cpu->midr =3D 0x411fc153; /* r1p3 */ cpu->id_pfr0 =3D 0x0131; cpu->id_pfr1 =3D 0x001; - cpu->id_dfr0 =3D 0x010400; + cpu->isar.id_dfr0 =3D 0x010400; cpu->id_afr0 =3D 0x0; cpu->id_mmfr0 =3D 0x0210030; cpu->id_mmfr1 =3D 0x00000000; @@ -2286,7 +2286,7 @@ static void cortex_a8_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50078; cpu->id_pfr0 =3D 0x1031; cpu->id_pfr1 =3D 0x11; - cpu->id_dfr0 =3D 0x400; + cpu->isar.id_dfr0 =3D 0x400; cpu->id_afr0 =3D 0; cpu->id_mmfr0 =3D 0x31100003; cpu->id_mmfr1 =3D 0x20000000; @@ -2359,7 +2359,7 @@ static void cortex_a9_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50078; cpu->id_pfr0 =3D 0x1031; cpu->id_pfr1 =3D 0x11; - cpu->id_dfr0 =3D 0x000; + cpu->isar.id_dfr0 =3D 0x000; cpu->id_afr0 =3D 0; cpu->id_mmfr0 =3D 0x00100103; cpu->id_mmfr1 =3D 0x20000000; @@ -2424,7 +2424,7 @@ static void cortex_a7_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50078; cpu->id_pfr0 =3D 0x00001131; cpu->id_pfr1 =3D 0x00011011; - cpu->id_dfr0 =3D 0x02010555; + cpu->isar.id_dfr0 =3D 0x02010555; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x10101105; cpu->id_mmfr1 =3D 0x40000000; @@ -2470,7 +2470,7 @@ static void cortex_a15_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50078; cpu->id_pfr0 =3D 0x00001131; cpu->id_pfr1 =3D 0x00011011; - cpu->id_dfr0 =3D 0x02010555; + cpu->isar.id_dfr0 =3D 0x02010555; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x10201105; cpu->id_mmfr1 =3D 0x20000000; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f0d98bc79d1..9e4387158f9 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -121,7 +121,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50838; cpu->id_pfr0 =3D 0x00000131; cpu->id_pfr1 =3D 0x00011011; - cpu->id_dfr0 =3D 0x03010066; + cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x10101105; cpu->id_mmfr1 =3D 0x40000000; @@ -175,7 +175,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50838; cpu->id_pfr0 =3D 0x00000131; cpu->id_pfr1 =3D 0x00011011; - cpu->id_dfr0 =3D 0x03010066; + cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x10101105; cpu->id_mmfr1 =3D 0x40000000; @@ -228,7 +228,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->reset_sctlr =3D 0x00c50838; cpu->id_pfr0 =3D 0x00000131; cpu->id_pfr1 =3D 0x00011011; - cpu->id_dfr0 =3D 0x03010066; + cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; cpu->id_mmfr0 =3D 0x10201105; cpu->id_mmfr1 =3D 0x40000000; diff --git a/target/arm/helper.c b/target/arm/helper.c index f183ac5cbfe..f78500e2a9e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6381,8 +6381,7 @@ static void define_pmu_regs(ARMCPU *cpu) g_free(pmevtyper_name); g_free(pmevtyper_el0_name); } - if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >=3D 4 && - FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf) { + if (cpu_isar_feature(aa32_pmu_8_1, cpu)) { ARMCPRegInfo v81_pmu_regs[] =3D { { .name =3D "PMCEID2", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 4, @@ -6856,7 +6855,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->id_dfr0 }, + .resetvalue =3D cpu->isar.id_dfr0 }, { .name =3D "ID_AFR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 3, .access =3D PL1_R, .type =3D ARM_CP_CONST, --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=EsdiaTm0IFB2gzMCnWsA71C+8ZH9oy94y+EHWu8Arx4=; b=ALrj4K9M14gp9kwKII/ofaQUUYxEa+RBEdM+s3KPYHpmzINtVg3CsOhv3pNyPsffkB mxfsEZ05lnmdCQdQnoBBFRWd0biZqCJwWgijG7IQ2MzIkyup9R5bV8+WgTNHziRjRjO+ SAHu2c5d9N4+/2qfVTmOwkDbTqj84V5RgkUGUFyXskKqUoOSNp4fJr9hUP6+IPbTIiDN mkKK6Bb3XBh4NVxiB/7OJUZ1yi/WLSexq8uR5M84lABGunpqptGJWb5Yo+2VdnJLeXgm hL68FOKQVRgCyMpLwLfj+3g3NxUFNMADKpL3LnuJNh+HqiMSVP9LUvqR6YzE2mcziNUS 3XYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EsdiaTm0IFB2gzMCnWsA71C+8ZH9oy94y+EHWu8Arx4=; b=XKN1tXAf5pNKZv7YoEYVlosIbSZIV/30IL9itkjHlDw9Jrs3QIYH+yFLO3FiKUVGU4 ycsgP9lOl9+qY/jn7XHDPN0kUBJhogrqDUfm/2AoXNfF/AVSHr4jdLZuPsM3lAz4zGfm Q2yXJyYIRE9E93w4QSv2v4GU/potGxxkfddtqkRsHh8u5g2wb/lCbVZCYpUnN0WfOY4n +C6qRZ51r1YLJ5vb8j3CPt2vHEweaGCN5j2GocKdS6+wwNdt7mRM+sI8zcCFPZ/4CzQO BT5sf2gcC1EFh5he96V+Sg62mKuGvCBpHhbnBeuucsFnZ/jrT73kCMIL9uHiGt6OthFp WVYg== X-Gm-Message-State: APjAAAX2tvlCSoh6UWKSn9md62/e0leFk3RY52lDaqNYAPmXOSevOFUR T/08Lq1nZmk3+rphkEuDVy13vT83g2VJsA== X-Google-Smtp-Source: APXvYqwnRhnzRjhvq6d7Q0INO69kT3UnorSyctzRZ6PoTgnN+/MRCbKLo1DOgkRIUYDKOVzcIYmEhQ== X-Received: by 2002:a05:600c:21da:: with SMTP id x26mr3711841wmj.114.1582290489546; Fri, 21 Feb 2020 05:08:09 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/52] target/arm: Add _aa64_ and _any_ versions of pmu_8_1 isar checks Date: Fri, 21 Feb 2020 13:07:10 +0000 Message-Id: <20200221130740.7583-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32e X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Add the 64-bit version of the "is this a v8.1 PMUv3?" ID register check function, and the _any_ version that checks for either AArch32 or AArch64 support. We'll use this in a later commit. We don't (yet) do any isar_feature checks on ID_AA64DFR1_EL1, but we move id_aa64dfr1 into the ARMISARegisters struct with id_aa64dfr0, for consistency. Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell Message-id: 20200214175116.9164-10-peter.maydell@linaro.org --- target/arm/cpu.h | 15 +++++++++++++-- target/arm/cpu.c | 3 ++- target/arm/cpu64.c | 6 +++--- target/arm/helper.c | 12 +++++++----- 4 files changed, 25 insertions(+), 11 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6c6088eb587..98240224c0c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -873,6 +873,8 @@ struct ARMCPU { uint64_t id_aa64mmfr0; uint64_t id_aa64mmfr1; uint64_t id_aa64mmfr2; + uint64_t id_aa64dfr0; + uint64_t id_aa64dfr1; } isar; uint32_t midr; uint32_t revidr; @@ -889,8 +891,6 @@ struct ARMCPU { uint32_t id_mmfr2; uint32_t id_mmfr3; uint32_t id_mmfr4; - uint64_t id_aa64dfr0; - uint64_t id_aa64dfr1; uint64_t id_aa64afr0; uint64_t id_aa64afr1; uint32_t dbgdidr; @@ -3686,6 +3686,12 @@ static inline bool isar_feature_aa64_bti(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) !=3D 0; } =20 +static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 4 && + FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ @@ -3699,6 +3705,11 @@ static inline bool isar_feature_any_predinv(const AR= MISARegisters *id) return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); } =20 +static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id) +{ + return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b85040d36bc..7759e0f9329 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1718,7 +1718,8 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) cpu); #endif } else { - cpu->id_aa64dfr0 =3D FIELD_DP64(cpu->id_aa64dfr0, ID_AA64DFR0, PMU= VER, 0); + cpu->isar.id_aa64dfr0 =3D + FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMUVER, 0); cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, PERFM= ON, 0); cpu->pmceid0 =3D 0; cpu->pmceid1 =3D 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 9e4387158f9..2030e5e384b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -135,7 +135,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_isar6 =3D 0; cpu->isar.id_aa64pfr0 =3D 0x00002222; - cpu->id_aa64dfr0 =3D 0x10305106; + cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64isar0 =3D 0x00011120; cpu->isar.id_aa64mmfr0 =3D 0x00001124; cpu->dbgdidr =3D 0x3516d000; @@ -189,7 +189,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_isar6 =3D 0; cpu->isar.id_aa64pfr0 =3D 0x00002222; - cpu->id_aa64dfr0 =3D 0x10305106; + cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64isar0 =3D 0x00011120; cpu->isar.id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ cpu->dbgdidr =3D 0x3516d000; @@ -241,7 +241,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_isar4 =3D 0x00011142; cpu->isar.id_isar5 =3D 0x00011121; cpu->isar.id_aa64pfr0 =3D 0x00002222; - cpu->id_aa64dfr0 =3D 0x10305106; + cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64isar0 =3D 0x00011120; cpu->isar.id_aa64mmfr0 =3D 0x00001124; cpu->dbgdidr =3D 0x3516d000; diff --git a/target/arm/helper.c b/target/arm/helper.c index f78500e2a9e..679f340c55f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -25,6 +25,7 @@ #include "hw/semihosting/semihost.h" #include "sysemu/cpus.h" #include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "qemu/range.h" #include "qapi/qapi-commands-machine-target.h" #include "qapi/error.h" @@ -6266,9 +6267,10 @@ static void define_debug_regs(ARMCPU *cpu) * check that if they both exist then they agree. */ if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, BRPS) =3D=3D brps= ); - assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, WRPS) =3D=3D wrps= ); - assert(FIELD_EX64(cpu->id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) =3D=3D = ctx_cmps); + assert(FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) =3D=3D= brps); + assert(FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) =3D=3D= wrps); + assert(FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + =3D=3D ctx_cmps); } =20 define_one_arm_cp_reg(cpu, &dbgdidr); @@ -7010,12 +7012,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->id_aa64dfr0 }, + .resetvalue =3D cpu->isar.id_aa64dfr0 }, { .name =3D "ID_AA64DFR1_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 1, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa64_tid3, - .resetvalue =3D cpu->id_aa64dfr1 }, + .resetvalue =3D cpu->isar.id_aa64dfr1 }, { .name =3D "ID_AA64DFR2_EL1_RESERVED", .state =3D ARM_CP_STAT= E_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 5, .opc2 =3D = 2, .access =3D PL1_R, .type =3D ARM_CP_CONST, --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=fQNBVqODkD8LKZELJsekhva6udMFsBGMkDMTJVnh7us=; b=aIsp5g1QZ0hcFrX94r0NMD3lYJjW8PYVK6vgAafAR5yi4jkLSE+LmCMhiXCnoCcteP KY4JsKJh5N8aig9W4gWAuAUwwagVe6lewJpdAwSgYhydTl5HgyZnOFrUT8CuAT/OOOga VEASguYBrkeDVTVNF02EMCkSxsyddpkjCvnjs9PWfosSxVkoiS4dxkqzQ58I5y9emv2y pmL7uhI4rFjtPivkfAQGQZlWZ4Thtcwvdb0uf21oGmoW65OgZusN0zxz+vrVN9J9iEKV H0wDhl7CqqCYYyP/qZhQ0zwui8w2GvWvN7dxtowlLGQJNBrqz8YDdN9W8zewKP7/P1/M WqjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fQNBVqODkD8LKZELJsekhva6udMFsBGMkDMTJVnh7us=; b=rdWuZA0SxK4mbk5tVqDunnuTGlk4Bu3pSD6b+IzyzB2xqhCSzaWcm14b0JYy6bJl5D VosDSjH7uMNepp9HPTFrPU8y0KomKwwnWGBRzoZ3d9ReUZEnVcuRv/pYXlGz3EQTXyZY Kzbjd9BQQfy+w90GwO1J69HFCA9eWNP2XMNt80J0RDzzvo34nC6xLRsdrb+GE7yyszpf oFUCYZesqADVS8Mric6d/4eJXAe2Dw+k9TISNshLagVvFqqK7DreeITJNkum0I9MwY5W zODBbBG/AMxdcOglk3FpO7M9cTPr9pNugklxNArYmGGs/qMngYX5HncrrUpgysgMOEsl /4Jw== X-Gm-Message-State: APjAAAWuixAEkMOhqFW1QUrJz0uP6/q8tcKf4+fro7gEEhQs3Wm719AX NXRA7I27akErBv6KP27wjC/YJYChnhsiRA== X-Google-Smtp-Source: APXvYqyogsNgWQ2d52kjlrRLfMf5H4ZJ9TrTOr3zVwvlixt4Y4RLjlFNYfmixuJXX6EUyv3Xg27NFQ== X-Received: by 2002:adf:f084:: with SMTP id n4mr48355644wro.200.1582290490763; Fri, 21 Feb 2020 05:08:10 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/52] target/arm: Stop assuming DBGDIDR always exists Date: Fri, 21 Feb 2020 13:07:11 +0000 Message-Id: <20200221130740.7583-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::432 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The AArch32 DBGDIDR defines properties like the number of breakpoints, watchpoints and context-matching comparators. On an AArch64 CPU, the register may not even exist if AArch32 is not supported at EL1. Currently we hard-code use of DBGDIDR to identify the number of breakpoints etc; this works for all our TCG CPUs, but will break if we ever add an AArch64-only CPU. We also have an assert() that the AArch32 and AArch64 registers match, which currently works only by luck for KVM because we don't populate either of these ID registers from the KVM vCPU and so they are both zero. Clean this up so we have functions for finding the number of breakpoints, watchpoints and context comparators which look in the appropriate ID register. This allows us to drop the "check that AArch64 and AArch32 agree on the number of breakpoints etc" asserts: * we no longer look at the AArch32 versions unless that's the right place to be looking * it's valid to have a CPU (eg AArch64-only) where they don't match * we shouldn't have been asserting the validity of ID registers in a codepath used with KVM anyway Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200214175116.9164-11-peter.maydell@linaro.org --- target/arm/cpu.h | 7 +++++++ target/arm/internals.h | 42 +++++++++++++++++++++++++++++++++++++++ target/arm/debug_helper.c | 6 +++--- target/arm/helper.c | 21 +++++--------------- 4 files changed, 57 insertions(+), 19 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 98240224c0c..0f21b6ed803 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1840,6 +1840,13 @@ FIELD(ID_DFR0, MPROFDBG, 20, 4) FIELD(ID_DFR0, PERFMON, 24, 4) FIELD(ID_DFR0, TRACEFILT, 28, 4) =20 +FIELD(DBGDIDR, SE_IMP, 12, 1) +FIELD(DBGDIDR, NSUHD_IMP, 14, 1) +FIELD(DBGDIDR, VERSION, 16, 4) +FIELD(DBGDIDR, CTX_CMPS, 20, 4) +FIELD(DBGDIDR, BRPS, 24, 4) +FIELD(DBGDIDR, WRPS, 28, 4) + FIELD(MVFR0, SIMDREG, 0, 4) FIELD(MVFR0, FPSP, 4, 4) FIELD(MVFR0, FPDP, 8, 4) diff --git a/target/arm/internals.h b/target/arm/internals.h index 31aaa0eff87..e07a7306c77 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -931,6 +931,48 @@ static inline uint32_t arm_debug_exception_fsr(CPUARMS= tate *env) } } =20 +/** + * arm_num_brps: Return number of implemented breakpoints. + * Note that the ID register BRPS field is "number of bps - 1", + * and we return the actual number of breakpoints. + */ +static inline int arm_num_brps(ARMCPU *cpu) +{ + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1; + } else { + return FIELD_EX32(cpu->dbgdidr, DBGDIDR, BRPS) + 1; + } +} + +/** + * arm_num_wrps: Return number of implemented watchpoints. + * Note that the ID register WRPS field is "number of wps - 1", + * and we return the actual number of watchpoints. + */ +static inline int arm_num_wrps(ARMCPU *cpu) +{ + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1; + } else { + return FIELD_EX32(cpu->dbgdidr, DBGDIDR, WRPS) + 1; + } +} + +/** + * arm_num_ctx_cmps: Return number of implemented context comparators. + * Note that the ID register CTX_CMPS field is "number of cmps - 1", + * and we return the actual number of comparators. + */ +static inline int arm_num_ctx_cmps(ARMCPU *cpu) +{ + if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { + return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + = 1; + } else { + return FIELD_EX32(cpu->dbgdidr, DBGDIDR, CTX_CMPS) + 1; + } +} + /* Note make_memop_idx reserves 4 bits for mmu_idx, and MO_BSWAP is bit 3. * Thus a TCGMemOpIdx, without any MO_ALIGN bits, fits in 8 bits. */ diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 2e3e90c6a57..2ff72d47d19 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -16,8 +16,8 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) { CPUARMState *env =3D &cpu->env; uint64_t bcr =3D env->cp15.dbgbcr[lbn]; - int brps =3D extract32(cpu->dbgdidr, 24, 4); - int ctx_cmps =3D extract32(cpu->dbgdidr, 20, 4); + int brps =3D arm_num_brps(cpu); + int ctx_cmps =3D arm_num_ctx_cmps(cpu); int bt; uint32_t contextidr; uint64_t hcr_el2; @@ -29,7 +29,7 @@ static bool linked_bp_matches(ARMCPU *cpu, int lbn) * case DBGWCR_EL1.LBN must indicate that breakpoint). * We choose the former. */ - if (lbn > brps || lbn < (brps - ctx_cmps)) { + if (lbn >=3D brps || lbn < (brps - ctx_cmps)) { return false; } =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 679f340c55f..87e71fb8c78 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6256,23 +6256,12 @@ static void define_debug_regs(ARMCPU *cpu) }; =20 /* Note that all these register fields hold "number of Xs minus 1". */ - brps =3D extract32(cpu->dbgdidr, 24, 4); - wrps =3D extract32(cpu->dbgdidr, 28, 4); - ctx_cmps =3D extract32(cpu->dbgdidr, 20, 4); + brps =3D arm_num_brps(cpu); + wrps =3D arm_num_wrps(cpu); + ctx_cmps =3D arm_num_ctx_cmps(cpu); =20 assert(ctx_cmps <=3D brps); =20 - /* The DBGDIDR and ID_AA64DFR0_EL1 define various properties - * of the debug registers such as number of breakpoints; - * check that if they both exist then they agree. - */ - if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { - assert(FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) =3D=3D= brps); - assert(FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) =3D=3D= wrps); - assert(FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) - =3D=3D ctx_cmps); - } - define_one_arm_cp_reg(cpu, &dbgdidr); define_arm_cp_regs(cpu, debug_cp_reginfo); =20 @@ -6280,7 +6269,7 @@ static void define_debug_regs(ARMCPU *cpu) define_arm_cp_regs(cpu, debug_lpae_cp_reginfo); } =20 - for (i =3D 0; i < brps + 1; i++) { + for (i =3D 0; i < brps; i++) { ARMCPRegInfo dbgregs[] =3D { { .name =3D "DBGBVR", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 4, @@ -6299,7 +6288,7 @@ static void define_debug_regs(ARMCPU *cpu) define_arm_cp_regs(cpu, dbgregs); } =20 - for (i =3D 0; i < wrps + 1; i++) { + for (i =3D 0; i < wrps; i++) { ARMCPRegInfo dbgregs[] =3D { { .name =3D "DBGWVR", .state =3D ARM_CP_STATE_BOTH, .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D i= , .opc2 =3D 6, --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582291243; cv=none; d=zohomail.com; s=zohoarc; b=hUUaHj6PNZL+ASJ6QxrROSJo6qaqSTlRAKMGfgJpyRU+lG/7/rTKw78LvePTyaJrJCZ5OvbJyX37HUZWantBr/eLBkK4yeaVh/6iSbpPps5syCxCIaW2tnNVBIPEuPASfJTEF806pSMrAhX2k2g4SOy2/zVT3fUZ2fEfixgX/yk= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ayxTwKJPtrH+7ITeMQGolZtlE+otPOpXrIHYXAP1MJg=; b=UpolRszcWk2bBb/8nqkb8iEEkbuCX9ChgH1jRV/747x8OdA8ohnHadF28jH5/TkCSx l3CBKIrS8w80uMeb2SOD3DZggZwyLbUawSjDlqa+xBH+OwomoXEAVnvrZRltkibapXCJ jZfJ4orjsZ0BeekqcJys1BPTfKUY2IwVX4pbchssrgLevR6yeYQ6Xn2vjpKurJMYHI/V T50+Q0ugM4xhzhSsDa/8OPrZTr3FpIUcrx/Mojcbnx7IVMwv1AO8cHpvoomQUaoPke0I ObleRdU7GNHDg4covXnwPSSef1ovnqePC7ZEemFyZ02thn7B+ISNjyBx/3vZq3UA+9V3 cqVQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ayxTwKJPtrH+7ITeMQGolZtlE+otPOpXrIHYXAP1MJg=; b=jzzcA9+YJZbZ5pa/gsoMKEUntlDZCmIHaQ4H7qiO/f2HeO90gdcr/DpN1DTeUpDM14 fi8FCCfKjXFc+2gAz7q/2ERNqedTu9ibYGyTjM0Nge74K6oH1AsnRmTFsMb7KxLLSRcU jFIk54wA/bXVKECkpdJYcGS6tWb4xGnWTR0G6fav5JAPHzQEyGiJ/6SkNcONI9Ydxcj2 ToTQNUJeyxCnmDgqRVsxIEEsNBvEFfo3KwV15q+aVlRzv0E3qfhrFCNg1eTjng/bWFBi BYHgtHlr0UNXsfmD94CH7sinjln2awUqykccrc/mIiaJ0T9VMegcKo96jPE6LSIGNLU9 lVDg== X-Gm-Message-State: APjAAAWVpeior6P2uYhQpfYFRdz7pshctu8GlMg4tVwfSpBsiY3MPhu8 HguwrQUMpd0yZyPAfTurWrlxJ1BtZmFB4Q== X-Google-Smtp-Source: APXvYqzk72vcv2HUL5uodtyW6scMLzu0C8hBn/l773FRAGj+G//hdGxfHXgzwiBwa8aZ2NeHR7+WDA== X-Received: by 2002:a7b:c389:: with SMTP id s9mr3650328wmj.7.1582290491975; Fri, 21 Feb 2020 05:08:11 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/52] target/arm: Move DBGDIDR into ARMISARegisters Date: Fri, 21 Feb 2020 13:07:12 +0000 Message-Id: <20200221130740.7583-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::334 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" We're going to want to read the DBGDIDR register from KVM in a subsequent commit, which means it needs to be in the ARMISARegisters sub-struct. Move it. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200214175116.9164-12-peter.maydell@linaro.org --- target/arm/cpu.h | 2 +- target/arm/internals.h | 6 +++--- target/arm/cpu.c | 8 ++++---- target/arm/cpu64.c | 6 +++--- target/arm/helper.c | 2 +- 5 files changed, 12 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 0f21b6ed803..3c996db3e45 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -866,6 +866,7 @@ struct ARMCPU { uint32_t mvfr1; uint32_t mvfr2; uint32_t id_dfr0; + uint32_t dbgdidr; uint64_t id_aa64isar0; uint64_t id_aa64isar1; uint64_t id_aa64pfr0; @@ -893,7 +894,6 @@ struct ARMCPU { uint32_t id_mmfr4; uint64_t id_aa64afr0; uint64_t id_aa64afr1; - uint32_t dbgdidr; uint32_t clidr; uint64_t mp_affinity; /* MP ID without feature bits */ /* The elements of this array are the CCSIDR values for each cache, diff --git a/target/arm/internals.h b/target/arm/internals.h index e07a7306c77..9f96a2359f3 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -941,7 +941,7 @@ static inline int arm_num_brps(ARMCPU *cpu) if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, BRPS) + 1; } else { - return FIELD_EX32(cpu->dbgdidr, DBGDIDR, BRPS) + 1; + return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, BRPS) + 1; } } =20 @@ -955,7 +955,7 @@ static inline int arm_num_wrps(ARMCPU *cpu) if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, WRPS) + 1; } else { - return FIELD_EX32(cpu->dbgdidr, DBGDIDR, WRPS) + 1; + return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, WRPS) + 1; } } =20 @@ -969,7 +969,7 @@ static inline int arm_num_ctx_cmps(ARMCPU *cpu) if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) { return FIELD_EX64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS) + = 1; } else { - return FIELD_EX32(cpu->dbgdidr, DBGDIDR, CTX_CMPS) + 1; + return FIELD_EX32(cpu->isar.dbgdidr, DBGDIDR, CTX_CMPS) + 1; } } =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7759e0f9329..f58b4da4427 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2298,7 +2298,7 @@ static void cortex_a8_initfn(Object *obj) cpu->isar.id_isar2 =3D 0x21232031; cpu->isar.id_isar3 =3D 0x11112131; cpu->isar.id_isar4 =3D 0x00111142; - cpu->dbgdidr =3D 0x15141000; + cpu->isar.dbgdidr =3D 0x15141000; cpu->clidr =3D (1 << 27) | (2 << 24) | 3; cpu->ccsidr[0] =3D 0xe007e01a; /* 16k L1 dcache. */ cpu->ccsidr[1] =3D 0x2007e01a; /* 16k L1 icache. */ @@ -2371,7 +2371,7 @@ static void cortex_a9_initfn(Object *obj) cpu->isar.id_isar2 =3D 0x21232041; cpu->isar.id_isar3 =3D 0x11112131; cpu->isar.id_isar4 =3D 0x00111142; - cpu->dbgdidr =3D 0x35141000; + cpu->isar.dbgdidr =3D 0x35141000; cpu->clidr =3D (1 << 27) | (1 << 24) | 3; cpu->ccsidr[0] =3D 0xe00fe019; /* 16k L1 dcache. */ cpu->ccsidr[1] =3D 0x200fe019; /* 16k L1 icache. */ @@ -2439,7 +2439,7 @@ static void cortex_a7_initfn(Object *obj) cpu->isar.id_isar2 =3D 0x21232041; cpu->isar.id_isar3 =3D 0x11112131; cpu->isar.id_isar4 =3D 0x10011142; - cpu->dbgdidr =3D 0x3515f005; + cpu->isar.dbgdidr =3D 0x3515f005; cpu->clidr =3D 0x0a200023; cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ @@ -2482,7 +2482,7 @@ static void cortex_a15_initfn(Object *obj) cpu->isar.id_isar2 =3D 0x21232041; cpu->isar.id_isar3 =3D 0x11112131; cpu->isar.id_isar4 =3D 0x10011142; - cpu->dbgdidr =3D 0x3515f021; + cpu->isar.dbgdidr =3D 0x3515f021; cpu->clidr =3D 0x0a200023; cpu->ccsidr[0] =3D 0x701fe00a; /* 32K L1 dcache */ cpu->ccsidr[1] =3D 0x201fe00a; /* 32K L1 icache */ diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2030e5e384b..f8f74a7ecda 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -138,7 +138,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64isar0 =3D 0x00011120; cpu->isar.id_aa64mmfr0 =3D 0x00001124; - cpu->dbgdidr =3D 0x3516d000; + cpu->isar.dbgdidr =3D 0x3516d000; cpu->clidr =3D 0x0a200023; cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ @@ -192,7 +192,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64isar0 =3D 0x00011120; cpu->isar.id_aa64mmfr0 =3D 0x00001122; /* 40 bit physical addr */ - cpu->dbgdidr =3D 0x3516d000; + cpu->isar.dbgdidr =3D 0x3516d000; cpu->clidr =3D 0x0a200023; cpu->ccsidr[0] =3D 0x700fe01a; /* 32KB L1 dcache */ cpu->ccsidr[1] =3D 0x201fe00a; /* 32KB L1 icache */ @@ -244,7 +244,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->isar.id_aa64dfr0 =3D 0x10305106; cpu->isar.id_aa64isar0 =3D 0x00011120; cpu->isar.id_aa64mmfr0 =3D 0x00001124; - cpu->dbgdidr =3D 0x3516d000; + cpu->isar.dbgdidr =3D 0x3516d000; cpu->clidr =3D 0x0a200023; cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 87e71fb8c78..68649121250 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6252,7 +6252,7 @@ static void define_debug_regs(ARMCPU *cpu) ARMCPRegInfo dbgdidr =3D { .name =3D "DBGDIDR", .cp =3D 14, .crn =3D 0, .crm =3D 0, .opc1 =3D= 0, .opc2 =3D 0, .access =3D PL0_R, .accessfn =3D access_tda, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->dbgdidr, + .type =3D ARM_CP_CONST, .resetvalue =3D cpu->isar.dbgdidr, }; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=5RqW1VFvoNTFM/LOz4YrIKBR0ShqAPTrRui+k6Sqcms=; b=ls7HslZR2GfKu7fI7DUeZXJDeEd1RD7151UUdOMoFQF/UdqPO/TEqOKmnjdJPmUwqw UxO6UC32OUHl6izG7It7OC5ycILll3iX8fNpr9KHWcrjYZGZSq2Uh2/76EmEoWoq20yG W1veY/oyRrJ1Yo6ZtfDhN6SWTA77vdZTOtg87qjwF5N36r6ViItVizkH+6Zd5m2NhyAF 20E1pCjT9To+hVIosTTPFKpX1LOE6b47yHVEZGaKRw8so1E1VnHQinKPEeRfF7iC7RlC R8f2dHRTeOByGhUSy2adSkjX5EdjNHR1Ta4gKHojR6uHBvDtT9FEc1n3cxgxAGrah1/g h37w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5RqW1VFvoNTFM/LOz4YrIKBR0ShqAPTrRui+k6Sqcms=; b=C0BlUIKlKwyK+YrOzQeGbFR2/7SJSPCitth776KrjW8a2rGD7atWMXP4ncoMuCb6wB n4vHSxukzYUCWSk7d4GsqBGVCLIkE1Zi1v+FdcHofpBDvL2Cnb3UA3yC3T5fYbZR/ofQ IGxQ2m1n40DYP5kiF8iBQxeZcpnAMUl0G5WcGSZa8T7u47AEE/WZIwhW8KMmJ7k7u1Ef ClrBPprQfLUvkxxtm+M0/3ETq1mygzglD2pG/BQZxd1VfoL9//i/+cKiQj9muoFQaGxS 4YApxLQzJkZoRiEEIDdlJkPrFOYIGXygFgLjp8nrDJkrSmW6n3DX59F0HWOjSqewyPTH Q7aA== X-Gm-Message-State: APjAAAUXBymfh4b4h1oJqTt7aNXH2SxiB8XpOh8Z0tVBpkBybq6maPB7 pnAU+g+BnpNNiSndWCUj26evTnRC7+iNKg== X-Google-Smtp-Source: APXvYqwsz52aYKlJoJv+2Ub+TEKPif2djidD/0rVLsW3YNEU6WjwS3u9lP/pOwGqF1TzK+9di3RNmQ== X-Received: by 2002:a7b:c152:: with SMTP id z18mr3789392wmi.70.1582290493256; Fri, 21 Feb 2020 05:08:13 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/52] target/arm: Read debug-related ID registers from KVM Date: Fri, 21 Feb 2020 13:07:13 +0000 Message-Id: <20200221130740.7583-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Now we have isar_feature test functions that look at fields in the ID_AA64DFR0_EL1 and ID_DFR0 ID registers, add the code that reads these register values from KVM so that the checks behave correctly when we're using KVM. No isar_feature function tests ID_AA64DFR1_EL1 or DBGDIDR yet, but we add it to maintain the invariant that every field in the ARMISARegisters struct is populated for a KVM CPU and can be relied on. This requirement isn't actually written down yet, so add a note to the relevant comment. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200214175116.9164-13-peter.maydell@linaro.org --- target/arm/cpu.h | 5 +++++ target/arm/kvm32.c | 8 ++++++++ target/arm/kvm64.c | 36 ++++++++++++++++++++++++++++++++++++ 3 files changed, 49 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 3c996db3e45..e043932fcb1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -853,6 +853,11 @@ struct ARMCPU { * prefix means a constant register. * Some of these registers are split out into a substructure that * is shared with the translators to control the ISA. + * + * Note that if you add an ID register to the ARMISARegisters struct + * you need to also update the 32-bit and 64-bit versions of the + * kvm_arm_get_host_cpu_features() function to correctly populate the + * field by reading the value from the KVM vCPU. */ struct ARMISARegisters { uint32_t id_isar0; diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index 3a8b437eef0..bca02553b25 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -97,6 +97,9 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *ah= cf) ahcf->isar.id_isar6 =3D 0; } =20 + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, + ARM_CP15_REG32(0, 0, 1, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr0, KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_VFP | KVM_REG_ARM_VFP_MVFR0); @@ -108,6 +111,11 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) * Fortunately there is not yet anything in there that affects migrati= on. */ =20 + /* + * There is no way to read DBGDIDR, because currently 32-bit KVM + * doesn't implement debug at all. Leave it at zero. + */ + kvm_arm_destroy_scratch_host_vcpu(fdarray); =20 if (err < 0) { diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 3bae9e4a663..e8d7cea74cb 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -541,6 +541,10 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) } else { err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64pfr1, ARM64_SYS_REG(3, 0, 0, 4, 1)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr0, + ARM64_SYS_REG(3, 0, 0, 5, 0)); + err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64dfr1, + ARM64_SYS_REG(3, 0, 0, 5, 1)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar0, ARM64_SYS_REG(3, 0, 0, 6, 0)); err |=3D read_sys_reg64(fdarray[2], &ahcf->isar.id_aa64isar1, @@ -559,6 +563,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) * than skipping the reads and leaving 0, as we must avoid * considering the values in every case. */ + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, + ARM64_SYS_REG(3, 0, 0, 1, 2)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, ARM64_SYS_REG(3, 0, 0, 2, 0)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, @@ -580,6 +586,36 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) ARM64_SYS_REG(3, 0, 0, 3, 1)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.mvfr2, ARM64_SYS_REG(3, 0, 0, 3, 2)); + + /* + * DBGDIDR is a bit complicated because the kernel doesn't + * provide an accessor for it in 64-bit mode, which is what this + * scratch VM is in, and there's no architected "64-bit sysreg + * which reads the same as the 32-bit register" the way there is + * for other ID registers. Instead we synthesize a value from the + * AArch64 ID_AA64DFR0, the same way the kernel code in + * arch/arm64/kvm/sys_regs.c:trap_dbgidr() does. + * We only do this if the CPU supports AArch32 at EL1. + */ + if (FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL1) >=3D 2) { + int wrps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, W= RPS); + int brps =3D FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, B= RPS); + int ctx_cmps =3D + FIELD_EX64(ahcf->isar.id_aa64dfr0, ID_AA64DFR0, CTX_CMPS); + int version =3D 6; /* ARMv8 debug architecture */ + bool has_el3 =3D + !!FIELD_EX32(ahcf->isar.id_aa64pfr0, ID_AA64PFR0, EL3); + uint32_t dbgdidr =3D 0; + + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, WRPS, wrps); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, BRPS, brps); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, CTX_CMPS, ctx_cmps); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, VERSION, version); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, NSUHD_IMP, has_el3); + dbgdidr =3D FIELD_DP32(dbgdidr, DBGDIDR, SE_IMP, has_el3); + dbgdidr |=3D (1 << 15); /* RES1 bit */ + ahcf->isar.dbgdidr =3D dbgdidr; + } } =20 sve_supported =3D ioctl(fdarray[0], KVM_CHECK_EXTENSION, KVM_CAP_ARM_S= VE) > 0; --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582291352; cv=none; d=zohomail.com; s=zohoarc; b=X1kl1jPpPOHPhydMwc9uBptufiiZShuDrqnp3hHoE03VH/6CcD2XrAO1BpqeoA5xX2XCNd2mu/xqD4a3cm0TQPx33eX3szXuhBuK8Jf9zsZiE73ioE0jZmmWzr6XkRDyOg1odrZEo59fWG/y8p0WE2BK4qS5T8Gipo9mjQjBkmI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582291352; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uveg6XQ+btPciQjR9M/wF8Pu54qyiyTAuMZo4NhoVOI=; b=aaqrb9ymY4TDbQgH1c0ocBCqVS6+txczMvm2YMlnGIvqDPArZqabe+qDu6Ube6QuAO4WBB2Q9Mzsb8fGSodXv2ExrH2rT68EPBDnhBVEEmuDdhBmkSpAiPdKea+X++HWcqhGRsWh4vFLP3PquKU5nWccSju87bbA707WDH+P6sU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582291352042238.98756161309495; Fri, 21 Feb 2020 05:22:32 -0800 (PST) Received: from localhost ([::1]:57506 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58GF-0004zw-03 for importer@patchew.org; Fri, 21 Feb 2020 08:22:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56793) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582T-0007PV-Er for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:18 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582S-00034b-2r for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:17 -0500 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:33740) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582R-00033u-S8 for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:16 -0500 Received: by mail-wr1-x433.google.com with SMTP id u6so2020226wrt.0 for ; Fri, 21 Feb 2020 05:08:15 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=uveg6XQ+btPciQjR9M/wF8Pu54qyiyTAuMZo4NhoVOI=; b=oFij9mrNkIDQEGntjoKsanDjlJHELjzSu1Lpv5MV+UXytzpOegM1ytd7/dT1cqqovN rNCd72obNVjc71pCHI10mRE1SG5MEVxcPBXpUM4XdVM8iWlOsXhE6B1BiqCxZDeE9LYJ 0bFeCdk09xilcOAn7wN5a8KyNv6xW4QVc1uJ7VzZLNDl7osuWNnuX2KIQmrPHyxXEhMd 9K3A7FQpW1lr4r6jrg68oXmlFM8F1nM+WwkF7/f4ivcVVXNiB3y7N6wlvNqaf71jBUVX CirFGRIS1r9mvyg5xJHjPYTNfyQGoxGUdLpMAvzXEjEXp+b392xpZns+mN8eErOetweb wZwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uveg6XQ+btPciQjR9M/wF8Pu54qyiyTAuMZo4NhoVOI=; b=kmMh8Ap7YC0BPdUDLm7NYuOAIzg6LILkyXjX2e8SGgVi8KY59qxCUt5JPA/v086Y1s HvZgMhQ4DzOp0quXIw036eB6pBqe3ATNuTqccOTRjF/p1dqgrUik0jHO9erqZdTiWRFq aTNV1GXTwlKXQI6kGM6Dka3PS09PTdGMrb6EcGaA2qK6Kpla+VccjJzd9lbTjzx9al4o yX+Aj6Bc3KCcJnaRCqKzOqvuqpmNrEQ7JogQu07pNCpTcSUhBA8B0WFP++yLgub+x/xz 86G/oo+XrNt9ZpMs4aniMYwOP5Gdvfvoju7C9IQbPbTf3k/u7wevpd+puguZHub3a6Vd FhmA== X-Gm-Message-State: APjAAAVvjC2GIRtlUIbXoVfQFdYWagN0YSuUwTHwdis7fW2B890W6p8O faAqQJL4U1jTTy246CSvrmxM/xbHU8ATuQ== X-Google-Smtp-Source: APXvYqzBvo/BFz4yT2cQo8cQatwmt7PNxobRbMA9xb+ylsBHr7g4zk+0fqDCKyiBXCl67JnkXAoGgg== X-Received: by 2002:adf:fa87:: with SMTP id h7mr51176917wrr.172.1582290494435; Fri, 21 Feb 2020 05:08:14 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/52] target/arm: Implement ARMv8.1-PMU extension Date: Fri, 21 Feb 2020 13:07:14 +0000 Message-Id: <20200221130740.7583-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::433 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The ARMv8.1-PMU extension requires: * the evtCount field in PMETYPER_EL0 is 16 bits, not 10 * MDCR_EL2.HPMD allows event counting to be disabled at EL2 * two new required events, STALL_FRONTEND and STALL_BACKEND * ID register bits in ID_AA64DFR0_EL1 and ID_DFR0 We already implement the 16-bit evtCount field and the HPMD bit, so all that is missing is the two new events: STALL_FRONTEND "counts every cycle counted by the CPU_CYCLES event on which no operation was issued because there are no operations available to issue to this PE from the frontend" STALL_BACKEND "counts every cycle counted by the CPU_CYCLES event on which no operation was issued because the backend is unable to accept any available operations from the frontend" QEMU never stalls in this sense, so our implementation is trivial: always return a zero count. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 20200214175116.9164-14-peter.maydell@linaro.org --- target/arm/helper.c | 32 ++++++++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 68649121250..2fe09c1d604 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1124,6 +1124,24 @@ static int64_t instructions_ns_per(uint64_t icount) } #endif =20 +static bool pmu_8_1_events_supported(CPUARMState *env) +{ + /* For events which are supported in any v8.1 PMU */ + return cpu_isar_feature(any_pmu_8_1, env_archcpu(env)); +} + +static uint64_t zero_event_get_count(CPUARMState *env) +{ + /* For events which on QEMU never fire, so their count is always zero = */ + return 0; +} + +static int64_t zero_event_ns_per(uint64_t cycles) +{ + /* An event which never fires can never overflow */ + return -1; +} + static const pm_event pm_events[] =3D { { .number =3D 0x000, /* SW_INCR */ .supported =3D event_always_supported, @@ -1140,8 +1158,18 @@ static const pm_event pm_events[] =3D { .supported =3D event_always_supported, .get_count =3D cycles_get_count, .ns_per_count =3D cycles_ns_per, - } + }, #endif + { .number =3D 0x023, /* STALL_FRONTEND */ + .supported =3D pmu_8_1_events_supported, + .get_count =3D zero_event_get_count, + .ns_per_count =3D zero_event_ns_per, + }, + { .number =3D 0x024, /* STALL_BACKEND */ + .supported =3D pmu_8_1_events_supported, + .get_count =3D zero_event_get_count, + .ns_per_count =3D zero_event_ns_per, + }, }; =20 /* @@ -1150,7 +1178,7 @@ static const pm_event pm_events[] =3D { * should first be updated to something sparse instead of the current * supported_event_map[] array. */ -#define MAX_EVENT_ID 0x11 +#define MAX_EVENT_ID 0x24 #define UNSUPPORTED_EVENT UINT16_MAX static uint16_t supported_event_map[MAX_EVENT_ID + 1]; =20 --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582291360; cv=none; d=zohomail.com; s=zohoarc; b=lW3CfNW7v0u+R++fXxWSlNGY1Hzts7UDILOZOWKgGtrFRr3kvfmUH4rHr3gzdmkZYfP+r/vxgvRqsw79OvWobw7FxjSX1yZiW7r+iyNhgU5++tVDl2VVc8oouIxQ+3c1itRxeEdjiz9tqT43CpHROo3DRvj1VkcrvzvvdgmZx3I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582291360; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FgrSznS6GQA2r5mNaBbVlZPpkueYI11Yncfhcl8nXSI=; b=KgVSDJsFmlGklp+XshXFDmahxHAU3FTkij3flcTmw/oPaod7sUKaBD15Vmr4gREcxCYajk0IbI6cQ3fZCvrCLwcfve8A5xTNheDDEehMRvGrXQXSGYxcw7y3l+XyRJH4VGnSu9MLdZc78ArkNJGGFd8xjKne5GwFXt/bldFWjqs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582291360365743.9449599197816; Fri, 21 Feb 2020 05:22:40 -0800 (PST) Received: from localhost ([::1]:57510 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58GK-0005DY-ME for importer@patchew.org; Fri, 21 Feb 2020 08:22:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56810) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582U-0007Sv-P4 for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582T-00035L-Ap for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:18 -0500 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:37066) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582T-00034w-3Q for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:17 -0500 Received: by mail-wm1-x343.google.com with SMTP id a6so1777892wme.2 for ; Fri, 21 Feb 2020 05:08:17 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=FgrSznS6GQA2r5mNaBbVlZPpkueYI11Yncfhcl8nXSI=; b=TWqNjT1oW4nBL+siIovxN33o+NgO5a+tqblWw8YdCWdkmqq/9S1NxRafrrOc2AcBUx URAhxMxcMa/1JeASX7LCg5s7r+XFOWgt36IsFkj6GJDqAS72+VWbpt+iPIDnMTpgz99H 1mH+2Fol6x+63UeYR6n0QrhKuePBVKzj0bl8e/IzkIVnJPdcymiYPgTSCWQBXbouju+y v1YBse5lIsLF2OoLMS/AWpGbJ/kJLxh3Ha4dCfH8K9Nt1HLB0/lkJfE/EMnuca0/E3+g ICEUC2mZXmYbZVIJfMsQlY6Bw/IF+wytaQOZRMN1uFApcMIxwoq4eJLZraSjUX/r6MKm Anow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FgrSznS6GQA2r5mNaBbVlZPpkueYI11Yncfhcl8nXSI=; b=bx9yFmAmKd35r06WlUgRMynoKypDgqgn4wRsNlf8E9KTpvJVcbv3n7NBiTHZK9Kv9b LFlyD705H52/bJsQbv0LXV3H4CoAt4GJsYRnoSvL1AphvKo7ED64RcVbCPakGzKNcs2O XBO8XMymSD3CPjKNQiBoJ+wz358TcY4sEp24lryz7a21YnSkaVuiJX76Luqwka0rzS6f 1F2JFAvAykf2eaUXA4fOPh7PqJB0grvS438KKf7qeIvbPtIg9H8s1X0cQJsEZGQ3ckQB d6VwSbIhUo9RmaX/nMr3rAt2DLIa+HK4kuRNntDZaL+KG+InL3XMbAnNi/368wjFfmr/ IZsw== X-Gm-Message-State: APjAAAXSbGj4d6TkDy8qHAXxiDCjV8xHtjChb70GU9dU315x4DrGfqT9 MMDKxC0x7uE0mWZ2RWVjVhwsshpXr1IcEA== X-Google-Smtp-Source: APXvYqyXIucbqCKyD0rnmJc6s2WICrYIgd6sWDnDvNhIuKaVxkn5/1n+BrA89ebcKwYQYPICITKTcA== X-Received: by 2002:a7b:c4c3:: with SMTP id g3mr3702295wmk.131.1582290495626; Fri, 21 Feb 2020 05:08:15 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/52] target/arm: Implement ARMv8.4-PMU extension Date: Fri, 21 Feb 2020 13:07:15 +0000 Message-Id: <20200221130740.7583-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The ARMv8.4-PMU extension adds: * one new required event, STALL * one new system register PMMIR_EL1 (There are also some more L1-cache related events, but since we don't implement any cache we don't provide these, in the same way we don't provide the base-PMUv3 cache events.) The STALL event "counts every attributable cycle on which no attributable instruction or operation was sent for execution on this PE". QEMU doesn't stall in this sense, so this is another always-reads-zero event. The PMMIR_EL1 register is a read-only register providing implementation-specific information about the PMU; currently it has only one field, SLOTS, which defines behaviour of the STALL_SLOT PMU event. Since QEMU doesn't implement the STALL_SLOT event, we can validly make the register read zero. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 20200214175116.9164-15-peter.maydell@linaro.org --- target/arm/cpu.h | 18 ++++++++++++++++++ target/arm/helper.c | 22 +++++++++++++++++++++- 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e043932fcb1..cfa9fd6c1b9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3519,6 +3519,13 @@ static inline bool isar_feature_aa32_pmu_8_1(const A= RMISARegisters *id) FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; } =20 +static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) +{ + /* 0xf means "non-standard IMPDEF PMU" */ + return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >=3D 5 && + FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; +} + /* * 64-bit feature tests via id registers. */ @@ -3704,6 +3711,12 @@ static inline bool isar_feature_aa64_pmu_8_1(const A= RMISARegisters *id) FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; } =20 +static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >=3D 5 && + FIELD_EX32(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) !=3D 0xf; +} + /* * Feature tests for "does this exist in either 32-bit or 64-bit?" */ @@ -3722,6 +3735,11 @@ static inline bool isar_feature_any_pmu_8_1(const AR= MISARegisters *id) return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); } =20 +static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) +{ + return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 2fe09c1d604..72c9c7e694a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1130,6 +1130,12 @@ static bool pmu_8_1_events_supported(CPUARMState *en= v) return cpu_isar_feature(any_pmu_8_1, env_archcpu(env)); } =20 +static bool pmu_8_4_events_supported(CPUARMState *env) +{ + /* For events which are supported in any v8.1 PMU */ + return cpu_isar_feature(any_pmu_8_4, env_archcpu(env)); +} + static uint64_t zero_event_get_count(CPUARMState *env) { /* For events which on QEMU never fire, so their count is always zero = */ @@ -1170,6 +1176,11 @@ static const pm_event pm_events[] =3D { .get_count =3D zero_event_get_count, .ns_per_count =3D zero_event_ns_per, }, + { .number =3D 0x03c, /* STALL */ + .supported =3D pmu_8_4_events_supported, + .get_count =3D zero_event_get_count, + .ns_per_count =3D zero_event_ns_per, + }, }; =20 /* @@ -1178,7 +1189,7 @@ static const pm_event pm_events[] =3D { * should first be updated to something sparse instead of the current * supported_event_map[] array. */ -#define MAX_EVENT_ID 0x24 +#define MAX_EVENT_ID 0x3c #define UNSUPPORTED_EVENT UINT16_MAX static uint16_t supported_event_map[MAX_EVENT_ID + 1]; =20 @@ -6414,6 +6425,15 @@ static void define_pmu_regs(ARMCPU *cpu) }; define_arm_cp_regs(cpu, v81_pmu_regs); } + if (cpu_isar_feature(any_pmu_8_4, cpu)) { + static const ARMCPRegInfo v84_pmmir =3D { + .name =3D "PMMIR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D 6, + .access =3D PL1_R, .accessfn =3D pmreg_access, .type =3D ARM_C= P_CONST, + .resetvalue =3D 0 + }; + define_one_arm_cp_reg(cpu, &v84_pmmir); + } } =20 /* We don't know until after realize whether there's a GICv3 --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=JZA6WWoqNvxJ8t7RB0a9zhQRcd4pYujNBUcXHYtibLo=; b=GFYANrnzRAH4Ceb53VS3wMUVL76i37br/wfLhM2cU54NCz6Nv4y8tFGyz8/li5dzww U9pF9/u0pJfieitDmJicMbzOZnw2s7dcC9oIoaPaiUmgIJh6b7N5jRtEeVwz//ovcrsR JMyOPD3Sq/Qp3AcrpTbTs9vYUcWGkwOuCms2GY0vFJb2ISYfwTDBtm6bI/Rm89a1JIRi w+TKHaqrAfIDPtbzJktM6f3ZP5THQ4LXfM80L0uO/tNgBIys505M4CIB1aiq6H/JFBrD /E54xqxW9IfnerU0Ib19assSmgJkMkVEdh/WVXYSoq771AbLnrBQtiRYY5BusO+k1RHt NJ+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JZA6WWoqNvxJ8t7RB0a9zhQRcd4pYujNBUcXHYtibLo=; b=saVfRK2Rx4Caxuzpf72cfExH+O3V3hNyY1sybROdOfGgQGfijblKDkO/H7xKnl33XF IBNsB1WofTLRBcaFUAiriweOc+a/OduqKNuQ0g6PZH22KE8tIyf4z+YwZZw4ay8gruMn rKS8e89F7LaP88TGVMrOKMRO4l6hmv+/ZIjKrTt9dcmSYA13n+eFzkL/CvKxEbYvwq/1 YJL9WqJNPqEdHNn2HBq9EVFRAY+f0uZ9MdsuiWSitA+BRObb4sT3D9yWEWqwn/yfS9ms DEC/Vf/YAV49ByblJJA4uUlBZCDg8XZbyItb5eTA7FZiw31zvkCc0KIVsO21OArifnlp aHpg== X-Gm-Message-State: APjAAAVeMF7pbzljnE5DxGrsFEz3fafzzwp2HyeKbWzNJAc1qretttZk 6Bo1BtWloGLAqXenapsVUseQKTp64gAysg== X-Google-Smtp-Source: APXvYqyZ7uCMCW+UANk5+sM+nF4zzE2mgPNuzSGRRtvva6BBtA5xZSA68ubIayFraQvWUjHryZuuAg== X-Received: by 2002:a5d:6987:: with SMTP id g7mr47294161wru.422.1582290496812; Fri, 21 Feb 2020 05:08:16 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/52] target/arm: Provide ARMv8.4-PMU in '-cpu max' Date: Fri, 21 Feb 2020 13:07:16 +0000 Message-Id: <20200221130740.7583-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Set the ID register bits to provide ARMv8.4-PMU (and implicitly also ARMv8.1-PMU) in the 'max' CPU. Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 20200214175116.9164-16-peter.maydell@linaro.org --- target/arm/cpu64.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f8f74a7ecda..c9452894035 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -703,6 +703,14 @@ static void aarch64_max_initfn(Object *obj) u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ cpu->id_mmfr3 =3D u; =20 + u =3D cpu->isar.id_aa64dfr0; + u =3D FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ + cpu->isar.id_aa64dfr0 =3D u; + + u =3D cpu->isar.id_dfr0; + u =3D FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + cpu->isar.id_dfr0 =3D u; + /* * FIXME: We do not yet support ARMv8.2-fp16 for AArch32 yet, * so do not set MVFR1.FPHP. Strictly speaking this is not legal, --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582291656; cv=none; d=zohomail.com; s=zohoarc; b=LwVQmSw2aoOsEIZ5v9yYOVtFNrK6dcpL6qyK0+8Db21NtYGrrKHUpWbuAoih2m2mMOnJNmzVZV1O9tEfZfUGA+MnDL9EP9aPHXV0ci9xAWkCItN7FsHag7eAVo++kvrg8oVoQoPXD0QWPztwJSQYvqQ6s/QgRtUg1WC63Baud1w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582291656; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9YDEWfTgYbtJnejtZ5TxG4cpNRlX/38cACEqimzClc0=; b=R9E7yB3nnIsyveWEchSPDk88Az7F7AW/mfAa3F/DIoi61mYcugLa80tY6pI5pzpdqwUkqgJGlVvWK6lUKeF6Uy4Ug4aSRc1BM7mOOn0SA0u15dvXC0Bg1igB0LhGgaRkE/RcRuxpm/FuE6bmS2IuUZWHcDWo8Ni/91GA5j5yT30= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582291656991175.0401923637321; Fri, 21 Feb 2020 05:27:36 -0800 (PST) Received: from localhost ([::1]:57642 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58L9-000401-PO for importer@patchew.org; Fri, 21 Feb 2020 08:27:35 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56843) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582W-0007Yr-PO for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:21 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582V-00036y-PW for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:20 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:40380) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582V-00036M-Jf for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:19 -0500 Received: by mail-wm1-x335.google.com with SMTP id t14so1774601wmi.5 for ; Fri, 21 Feb 2020 05:08:19 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9YDEWfTgYbtJnejtZ5TxG4cpNRlX/38cACEqimzClc0=; b=JPCbO69M6gUgiN5X1o1Oo7L7typeOWAVGP8vCfx9+qlIUg3BYwkwBjyp82X+4oBrjd cSJSnV9L3jRUTJiQ5buVN5stpTAzyvFrQFRQLpv8BtwPGDmznpxoLHc5lT1nb6tMWN1y KYPMaLkjpLTRb9hFTgPWnHnMFMJXzDlbWuJ7dH+FqzHmUO5iheQwo4RvrcqJlT0fCKVa WpxQJoUrlgWZi8DrY5j7jgjvHJ2LuMyZn4Ok4oIS8lEgzljZR9NBzrKReHzzkPy6jMQJ koFqXo70T2zDCEexf5LeeDGJ5Pg7RwzOyzSCqNqxUK/9hIFffdbE4+Vxh4bLA4eYADUr SKIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9YDEWfTgYbtJnejtZ5TxG4cpNRlX/38cACEqimzClc0=; b=VrTjBJ7dbwS7hg59E/pltJ4G79Znu47W5hK3LtVGZ33y2trrvh6N16SYFNJELakLav UzH+5LEPWK8MZvXhRXtGtUHw3d3h4duvSsD3Tjq1TkM2h+eao/XPxN53LtDjlxgtqEfa Sgyv79ZdhJTpIT33R9w9Ll2J3Ofh0VzQKJaM0/ahMXo4nopsCVmKKX16lUhrbAMF3GrA PijbY2nu72XQvEOlR/ty2iWHdAqahmfdfda4q52AI7gtVxyZBGFPtg4j94aWfIqyN0Fg b2zpc3FCIHi44S8SBJOnd5fMILBefBFoyv+zcXSs5Ybv022FGpx13RHtXD1dVYJEQDoa v7Ug== X-Gm-Message-State: APjAAAUKdNZS47c2d5xrOgbpfCBOHlQdplS1rsfwwg4eJfL7MY1oYiMv O028v9ZWy5yN9r3qxrpRqOzQvJkZ1dKqsw== X-Google-Smtp-Source: APXvYqwr9PLOlTfS00vDi5LDQRaDlePGn/g3SWRWlS2ql60Cqf0AyGykLFMlQkUY5MpVY3g0yD6xHw== X-Received: by 2002:a1c:f003:: with SMTP id a3mr3871204wmb.41.1582290498041; Fri, 21 Feb 2020 05:08:18 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/52] target/arm: Correct definition of PMCRDP Date: Fri, 21 Feb 2020 13:07:17 +0000 Message-Id: <20200221130740.7583-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::335 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The PMCR_EL0.DP bit is bit 5, which is 0x20, not 0x10. 0x10 is 'X'. Correct our #define of PMCRDP and add the missing PMCRX. We do have the correct behaviour for handling the DP bit being set, so this fixes a guest-visible bug. Fixes: 033614c47de Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Peter Maydell Message-id: 20200214175116.9164-17-peter.maydell@linaro.org --- target/arm/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 72c9c7e694a..e868b08cc18 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1017,7 +1017,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { #define PMCRN_MASK 0xf800 #define PMCRN_SHIFT 11 #define PMCRLC 0x40 -#define PMCRDP 0x10 +#define PMCRDP 0x20 +#define PMCRX 0x10 #define PMCRD 0x8 #define PMCRC 0x4 #define PMCRP 0x2 --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582291197; cv=none; d=zohomail.com; s=zohoarc; b=VGgUn7skfhb6YAKfnhlLNR7qoXEhVy2zLrydsd7rcXHtz1H0AyfUg7WKsTqWQUBxCgfz4S2Eq7ZWZJ1dm7VeVG/YSN2Ebto7bn+A40g3k3veygjOIqdRUGa9P2mtE6bJSS9r/SC20ATafFNTYI/GIuuNfV7x9wPY69iUk1GqCog= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582291197; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8O3SsjgKcLhfOeNTmM2193LemAhafTVhhnio75aha0c=; b=Y2KsF3rNknssg6a8SozBWOr2DwCRqg9zo5PIiUNpo5X2KLnzyXPUdam0+0l6YJnCWaorYKYYaanfW1mH/kLVUNGONMi26gtqqQIVvGfEYpFQmdk9hlX8pTfISCAb/vxokT/btuV3NO1DWyeDVqoKWs7PbjpD4fCxXvalCRdEk0k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582291197159629.145885940934; Fri, 21 Feb 2020 05:19:57 -0800 (PST) Received: from localhost ([::1]:57430 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58Dj-0000nE-Os for importer@patchew.org; Fri, 21 Feb 2020 08:19:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56858) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582X-0007bV-Lv for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:22 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582W-00038N-Jw for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:21 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:42085) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582W-000374-Dc for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:20 -0500 Received: by mail-wr1-x435.google.com with SMTP id k11so1985055wrd.9 for ; Fri, 21 Feb 2020 05:08:20 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8O3SsjgKcLhfOeNTmM2193LemAhafTVhhnio75aha0c=; b=ES52HhmXrBeNfyKKeub1XgMCtuMpWVMSyduLW+qPVMOcgCbcqEKPm6djfO/Syl3r6W OIHUGwIQS3BjSojabD823K402qnwUSnlsgAfgwhqtZX2NNlyRjObFeGqNhFXpQ7x3bRM tnWyh5/61KdPARYTKQg9pi9fCOCFJz0Fn6gZADG0dDep2qUGqLyi7UwK8BmmiHQLXQZs 9glL462l2XcsVaD+xH5sg2ek55DM6kZB1GrEsEcIMEz3Y7j8OmnT7PBqIw/ADyzumwia uiRvJomsU6ZyYKC5Maw076DYR0rR1P84vx+DeknWSMC9w0L6z5nS4qbs6dzJw/Zpbvvj kCBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8O3SsjgKcLhfOeNTmM2193LemAhafTVhhnio75aha0c=; b=GgJ77NgSxL8frC3ZLRJKj42A7DRQPQvWMg7vmpEK+vsMZyW67CtQCB0WT9R9iHxiaN IYiP62AQho7fHppeXk7q+S/rwIqykO6CV19FizUnixLejFTav0LJYNjGiH9P6XrA8g/G PwLHQdaE+uQMVea4+fKH8uf8aqJCBnvC1Z6TYj/qYO4r50QUottw9ozaQ+C4jWGOdIDV WDoKfzeuOf9/81JrIjHXGNANc2mqNTAPDFk1bakAsCFHN7vF4w6BOezZxW/A8JtV18Ow wJi1qneTgfOzEYPUb9J79KYBVQo7soUba/Os+ltFLZRVGwSXnDlufQ9+8xH63h4LjYCs aonQ== X-Gm-Message-State: APjAAAV0B6hsF/LYmpRUhI2hPoFVaL+kunuzKa4NEv456KCxJ8Evx/+o dAVD7dnmkt+GrnnUeKX4Ncvq7eHMbkraFQ== X-Google-Smtp-Source: APXvYqwVO/maJb4fQANun8IvjPhPjiTDvHx80csrb/Hp4m2zDMtrbIMEBpw01ktBNFuVmxQNFRc1tQ== X-Received: by 2002:a5d:560d:: with SMTP id l13mr22512115wrv.222.1582290499179; Fri, 21 Feb 2020 05:08:19 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/52] target/arm: Correct handling of PMCR_EL0.LC bit Date: Fri, 21 Feb 2020 13:07:18 +0000 Message-Id: <20200221130740.7583-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::435 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) The LC bit in the PMCR_EL0 register is supposed to be: * read/write * RES1 on an AArch64-only implementation * an architecturally UNKNOWN value on reset (and use of LC=3D=3D0 by software is deprecated). We were implementing it incorrectly as read-only always zero, though we do have all the code needed to test it and behave accordingly. Instead make it a read-write bit which resets to 1 always, which satisfies all the architectural requirements above. Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell Message-id: 20200214175116.9164-18-peter.maydell@linaro.org --- target/arm/helper.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e868b08cc18..15a840f530b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1023,6 +1023,11 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { #define PMCRC 0x4 #define PMCRP 0x2 #define PMCRE 0x1 +/* + * Mask of PMCR bits writeable by guest (not including WO bits like C, P, + * which can be written as 1 to trigger behaviour but which stay RAZ). + */ +#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) =20 #define PMXEVTYPER_P 0x80000000 #define PMXEVTYPER_U 0x40000000 @@ -1577,9 +1582,8 @@ static void pmcr_write(CPUARMState *env, const ARMCPR= egInfo *ri, } } =20 - /* only the DP, X, D and E bits are writable */ - env->cp15.c9_pmcr &=3D ~0x39; - env->cp15.c9_pmcr |=3D (value & 0x39); + env->cp15.c9_pmcr &=3D ~PMCR_WRITEABLE_MASK; + env->cp15.c9_pmcr |=3D (value & PMCR_WRITEABLE_MASK); =20 pmu_op_finish(env); } @@ -6370,7 +6374,8 @@ static void define_pmu_regs(ARMCPU *cpu) .access =3D PL0_RW, .accessfn =3D pmreg_access, .type =3D ARM_CP_IO, .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmcr), - .resetvalue =3D (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT), + .resetvalue =3D (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) | + PMCRLC, .writefn =3D pmcr_write, .raw_writefn =3D raw_write, }; define_one_arm_cp_reg(cpu, &pmcr); --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582291653; cv=none; d=zohomail.com; s=zohoarc; b=PZSJgw7dc2R6g3ot6fTnQo77iis6BsiffpGTKBGU/qWnCydEKSCi/HNzmJiZnLLJi4zHt4lEjbjOouQ6fRqRQqR7XSeQw3u6awBnVs7Y/8s3geOv6M/vYQWVVr1mBaZ6RtErmGEHhWecqRL9VCQORgMSvxSmOBkJrtJzr6VuEao= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582291653; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9XeXxKjvTgowAC0ChVR9dLi0ZL5hUJzK8yf9TSj40eA=; b=DAveBdcFYX7HRBHGUh4hNzsj/tSaIKrYrbVcCfZKbwiSL1V1oX+B+EQjuWzKksmEWQ0wQsBrarmkCqAe4/cyiBOgMwQumG2Ip9Nh+zSEF6ZZeVnLzvvbAMZF65LAGmvA5tVRwj63c8PpE8yOkkXX61HxdVhbjpUI41EVTluFnaU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582291653582221.40042930261143; Fri, 21 Feb 2020 05:27:33 -0800 (PST) Received: from localhost ([::1]:57634 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58L6-0003jH-Ha for importer@patchew.org; Fri, 21 Feb 2020 08:27:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56904) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582b-0007kw-0L for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582Y-0003BV-QQ for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:24 -0500 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:37818) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582Y-0003B3-He for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:22 -0500 Received: by mail-wm1-x334.google.com with SMTP id a6so1778320wme.2 for ; Fri, 21 Feb 2020 05:08:22 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.19 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=9XeXxKjvTgowAC0ChVR9dLi0ZL5hUJzK8yf9TSj40eA=; b=UR3LZ+RjJZf0q9vEugAL0bvWMr/cLPVaA4Lk1n0JKGxKWGB74h0J8H43OMEfawaNPa GMQ2+9P6IyoEzBTuSKMdyA96yzLztIljTCuxDWYSxFrq6O4i6OYbO0+G608Qw7uSSUjF mJuOOAohcQ3MmEwMs4yaf2zyllfXvAwWXo9wegvH35oVDPKAS0wU2+9TvuAmdTsHB76m UpoE6d3KRACyB7+whwhhQ6Jmf69hL0QHoWKzOby4xyuY81M/Gcg0H/qR8YzrKdpG0nZP 1hN+g9JX6VPR+yVJyryXHwZLM9Ko4U5MhouOen6zhWBvM7a0a3lxI7PSmtf/565CYsEe lQmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9XeXxKjvTgowAC0ChVR9dLi0ZL5hUJzK8yf9TSj40eA=; b=gDIGKQOkIaELoVX2N6VR9y6NhL5Tst4rdLm6qujt/SjDxF2SjmIqBgl3w97drgBKf1 K+slxqfcrfyUMmxu5bHVX/WQAJVoQ7D1A474RWxjvs0Nw3S/+VRFnWh/JVpk1Qtd3pDi X1ZK0eMYcLIh0x+9wYXq6IV/oyw5sFltyweLECYRUVt+QGai8Hy/MHwN/xxP9Wdoc6Cv bIph4BMEnBdPlYieztnQjjKEXUtmQJjzMSYlh7fJqq1sfmed65IdMz84GZMkU0TGXJLu VpbFwxNNXy92bO1bXpt81K2Rv/t20fj1xV+N9Lv5eZ4zMiXupM9bzHeDUBeI3DnDSJTJ Gqlg== X-Gm-Message-State: APjAAAWPuZueQSgmMO1ZhcWDRgMAWyHjHKU4DpEXl1eQ6YBxksgoTeiO C7yxC5UEQ/O/Nr+O8v6pqCbBRszmzosRLA== X-Google-Smtp-Source: APXvYqyGtArToGysisqB7oSNwCfQ/Xryrr+Udk0J/72x7oY5x2zKrAhyZLsi5eJdynXVD60YhD9Ixw== X-Received: by 2002:a1c:8055:: with SMTP id b82mr3864999wmd.127.1582290500606; Fri, 21 Feb 2020 05:08:20 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/52] target/arm: Test correct register in aa32_pan and aa32_ats1e1 checks Date: Fri, 21 Feb 2020 13:07:19 +0000 Message-Id: <20200221130740.7583-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::334 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The isar_feature_aa32_pan and isar_feature_aa32_ats1e1 functions are supposed to be testing fields in ID_MMFR3; but a cut-and-paste error meant we were looking at MVFR0 instead. Fix the functions to look at the right register; this requires us to move at least id_mmfr3 to the ARMISARegisters struct; we choose to move all the ID_MMFRn registers for consistency. Fixes: 3d6ad6bb466f Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200214175116.9164-19-peter.maydell@linaro.org --- target/arm/cpu.h | 14 +++--- hw/intc/armv7m_nvic.c | 8 ++-- target/arm/cpu.c | 104 +++++++++++++++++++++--------------------- target/arm/cpu64.c | 28 ++++++------ target/arm/helper.c | 12 ++--- target/arm/kvm32.c | 17 +++++++ target/arm/kvm64.c | 10 ++++ 7 files changed, 110 insertions(+), 83 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index cfa9fd6c1b9..ba97fc75c1d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -867,6 +867,11 @@ struct ARMCPU { uint32_t id_isar4; uint32_t id_isar5; uint32_t id_isar6; + uint32_t id_mmfr0; + uint32_t id_mmfr1; + uint32_t id_mmfr2; + uint32_t id_mmfr3; + uint32_t id_mmfr4; uint32_t mvfr0; uint32_t mvfr1; uint32_t mvfr2; @@ -892,11 +897,6 @@ struct ARMCPU { uint64_t pmceid0; uint64_t pmceid1; uint32_t id_afr0; - uint32_t id_mmfr0; - uint32_t id_mmfr1; - uint32_t id_mmfr2; - uint32_t id_mmfr3; - uint32_t id_mmfr4; uint64_t id_aa64afr0; uint64_t id_aa64afr1; uint32_t clidr; @@ -3504,12 +3504,12 @@ static inline bool isar_feature_aa32_vminmaxnm(cons= t ARMISARegisters *id) =20 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) !=3D 0; + return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) !=3D 0; } =20 static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr0, ID_MMFR3, PAN) >=3D 2; + return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >=3D 2; } =20 static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 5a403fc9704..22a43e49847 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1231,13 +1231,13 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) case 0xd4c: /* AFR0. */ return cpu->id_afr0; case 0xd50: /* MMFR0. */ - return cpu->id_mmfr0; + return cpu->isar.id_mmfr0; case 0xd54: /* MMFR1. */ - return cpu->id_mmfr1; + return cpu->isar.id_mmfr1; case 0xd58: /* MMFR2. */ - return cpu->id_mmfr2; + return cpu->isar.id_mmfr2; case 0xd5c: /* MMFR3. */ - return cpu->id_mmfr3; + return cpu->isar.id_mmfr3; case 0xd60: /* ISAR0. */ return cpu->isar.id_isar0; case 0xd64: /* ISAR1. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f58b4da4427..c46bb5a5c09 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1960,9 +1960,9 @@ static void arm1136_r2_initfn(Object *obj) cpu->id_pfr1 =3D 0x1; cpu->isar.id_dfr0 =3D 0x2; cpu->id_afr0 =3D 0x3; - cpu->id_mmfr0 =3D 0x01130003; - cpu->id_mmfr1 =3D 0x10030302; - cpu->id_mmfr2 =3D 0x01222110; + cpu->isar.id_mmfr0 =3D 0x01130003; + cpu->isar.id_mmfr1 =3D 0x10030302; + cpu->isar.id_mmfr2 =3D 0x01222110; cpu->isar.id_isar0 =3D 0x00140011; cpu->isar.id_isar1 =3D 0x12002111; cpu->isar.id_isar2 =3D 0x11231111; @@ -1992,9 +1992,9 @@ static void arm1136_initfn(Object *obj) cpu->id_pfr1 =3D 0x1; cpu->isar.id_dfr0 =3D 0x2; cpu->id_afr0 =3D 0x3; - cpu->id_mmfr0 =3D 0x01130003; - cpu->id_mmfr1 =3D 0x10030302; - cpu->id_mmfr2 =3D 0x01222110; + cpu->isar.id_mmfr0 =3D 0x01130003; + cpu->isar.id_mmfr1 =3D 0x10030302; + cpu->isar.id_mmfr2 =3D 0x01222110; cpu->isar.id_isar0 =3D 0x00140011; cpu->isar.id_isar1 =3D 0x12002111; cpu->isar.id_isar2 =3D 0x11231111; @@ -2025,9 +2025,9 @@ static void arm1176_initfn(Object *obj) cpu->id_pfr1 =3D 0x11; cpu->isar.id_dfr0 =3D 0x33; cpu->id_afr0 =3D 0; - cpu->id_mmfr0 =3D 0x01130003; - cpu->id_mmfr1 =3D 0x10030302; - cpu->id_mmfr2 =3D 0x01222100; + cpu->isar.id_mmfr0 =3D 0x01130003; + cpu->isar.id_mmfr1 =3D 0x10030302; + cpu->isar.id_mmfr2 =3D 0x01222100; cpu->isar.id_isar0 =3D 0x0140011; cpu->isar.id_isar1 =3D 0x12002111; cpu->isar.id_isar2 =3D 0x11231121; @@ -2055,9 +2055,9 @@ static void arm11mpcore_initfn(Object *obj) cpu->id_pfr1 =3D 0x1; cpu->isar.id_dfr0 =3D 0; cpu->id_afr0 =3D 0x2; - cpu->id_mmfr0 =3D 0x01100103; - cpu->id_mmfr1 =3D 0x10020302; - cpu->id_mmfr2 =3D 0x01222000; + cpu->isar.id_mmfr0 =3D 0x01100103; + cpu->isar.id_mmfr1 =3D 0x10020302; + cpu->isar.id_mmfr2 =3D 0x01222000; cpu->isar.id_isar0 =3D 0x00100011; cpu->isar.id_isar1 =3D 0x12002111; cpu->isar.id_isar2 =3D 0x11221011; @@ -2087,10 +2087,10 @@ static void cortex_m3_initfn(Object *obj) cpu->id_pfr1 =3D 0x00000200; cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x00000030; - cpu->id_mmfr1 =3D 0x00000000; - cpu->id_mmfr2 =3D 0x00000000; - cpu->id_mmfr3 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00000030; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x00000000; + cpu->isar.id_mmfr3 =3D 0x00000000; cpu->isar.id_isar0 =3D 0x01141110; cpu->isar.id_isar1 =3D 0x02111000; cpu->isar.id_isar2 =3D 0x21112231; @@ -2118,10 +2118,10 @@ static void cortex_m4_initfn(Object *obj) cpu->id_pfr1 =3D 0x00000200; cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x00000030; - cpu->id_mmfr1 =3D 0x00000000; - cpu->id_mmfr2 =3D 0x00000000; - cpu->id_mmfr3 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00000030; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x00000000; + cpu->isar.id_mmfr3 =3D 0x00000000; cpu->isar.id_isar0 =3D 0x01141110; cpu->isar.id_isar1 =3D 0x02111000; cpu->isar.id_isar2 =3D 0x21112231; @@ -2149,10 +2149,10 @@ static void cortex_m7_initfn(Object *obj) cpu->id_pfr1 =3D 0x00000200; cpu->isar.id_dfr0 =3D 0x00100000; cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x00100030; - cpu->id_mmfr1 =3D 0x00000000; - cpu->id_mmfr2 =3D 0x01000000; - cpu->id_mmfr3 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00100030; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x01000000; + cpu->isar.id_mmfr3 =3D 0x00000000; cpu->isar.id_isar0 =3D 0x01101110; cpu->isar.id_isar1 =3D 0x02112000; cpu->isar.id_isar2 =3D 0x20232231; @@ -2182,10 +2182,10 @@ static void cortex_m33_initfn(Object *obj) cpu->id_pfr1 =3D 0x00000210; cpu->isar.id_dfr0 =3D 0x00200000; cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x00101F40; - cpu->id_mmfr1 =3D 0x00000000; - cpu->id_mmfr2 =3D 0x01000000; - cpu->id_mmfr3 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00101F40; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x01000000; + cpu->isar.id_mmfr3 =3D 0x00000000; cpu->isar.id_isar0 =3D 0x01101110; cpu->isar.id_isar1 =3D 0x02212000; cpu->isar.id_isar2 =3D 0x20232232; @@ -2234,10 +2234,10 @@ static void cortex_r5_initfn(Object *obj) cpu->id_pfr1 =3D 0x001; cpu->isar.id_dfr0 =3D 0x010400; cpu->id_afr0 =3D 0x0; - cpu->id_mmfr0 =3D 0x0210030; - cpu->id_mmfr1 =3D 0x00000000; - cpu->id_mmfr2 =3D 0x01200000; - cpu->id_mmfr3 =3D 0x0211; + cpu->isar.id_mmfr0 =3D 0x0210030; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x01200000; + cpu->isar.id_mmfr3 =3D 0x0211; cpu->isar.id_isar0 =3D 0x02101111; cpu->isar.id_isar1 =3D 0x13112111; cpu->isar.id_isar2 =3D 0x21232141; @@ -2289,10 +2289,10 @@ static void cortex_a8_initfn(Object *obj) cpu->id_pfr1 =3D 0x11; cpu->isar.id_dfr0 =3D 0x400; cpu->id_afr0 =3D 0; - cpu->id_mmfr0 =3D 0x31100003; - cpu->id_mmfr1 =3D 0x20000000; - cpu->id_mmfr2 =3D 0x01202000; - cpu->id_mmfr3 =3D 0x11; + cpu->isar.id_mmfr0 =3D 0x31100003; + cpu->isar.id_mmfr1 =3D 0x20000000; + cpu->isar.id_mmfr2 =3D 0x01202000; + cpu->isar.id_mmfr3 =3D 0x11; cpu->isar.id_isar0 =3D 0x00101111; cpu->isar.id_isar1 =3D 0x12112111; cpu->isar.id_isar2 =3D 0x21232031; @@ -2362,10 +2362,10 @@ static void cortex_a9_initfn(Object *obj) cpu->id_pfr1 =3D 0x11; cpu->isar.id_dfr0 =3D 0x000; cpu->id_afr0 =3D 0; - cpu->id_mmfr0 =3D 0x00100103; - cpu->id_mmfr1 =3D 0x20000000; - cpu->id_mmfr2 =3D 0x01230000; - cpu->id_mmfr3 =3D 0x00002111; + cpu->isar.id_mmfr0 =3D 0x00100103; + cpu->isar.id_mmfr1 =3D 0x20000000; + cpu->isar.id_mmfr2 =3D 0x01230000; + cpu->isar.id_mmfr3 =3D 0x00002111; cpu->isar.id_isar0 =3D 0x00101111; cpu->isar.id_isar1 =3D 0x13112111; cpu->isar.id_isar2 =3D 0x21232041; @@ -2427,10 +2427,10 @@ static void cortex_a7_initfn(Object *obj) cpu->id_pfr1 =3D 0x00011011; cpu->isar.id_dfr0 =3D 0x02010555; cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x10101105; - cpu->id_mmfr1 =3D 0x40000000; - cpu->id_mmfr2 =3D 0x01240000; - cpu->id_mmfr3 =3D 0x02102211; + cpu->isar.id_mmfr0 =3D 0x10101105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01240000; + cpu->isar.id_mmfr3 =3D 0x02102211; /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but * table 4-41 gives 0x02101110, which includes the arm div insns. */ @@ -2473,10 +2473,10 @@ static void cortex_a15_initfn(Object *obj) cpu->id_pfr1 =3D 0x00011011; cpu->isar.id_dfr0 =3D 0x02010555; cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x10201105; - cpu->id_mmfr1 =3D 0x20000000; - cpu->id_mmfr2 =3D 0x01240000; - cpu->id_mmfr3 =3D 0x02102211; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x20000000; + cpu->isar.id_mmfr2 =3D 0x01240000; + cpu->isar.id_mmfr3 =3D 0x02102211; cpu->isar.id_isar0 =3D 0x02101110; cpu->isar.id_isar1 =3D 0x13112111; cpu->isar.id_isar2 =3D 0x21232041; @@ -2712,13 +2712,13 @@ static void arm_max_initfn(Object *obj) t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ cpu->isar.mvfr2 =3D t; =20 - t =3D cpu->id_mmfr3; + t =3D cpu->isar.id_mmfr3; t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->id_mmfr3 =3D t; + cpu->isar.id_mmfr3 =3D t; =20 - t =3D cpu->id_mmfr4; + t =3D cpu->isar.id_mmfr4; t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - cpu->id_mmfr4 =3D t; + cpu->isar.id_mmfr4 =3D t; } #endif } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c9452894035..8430d432943 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -123,10 +123,10 @@ static void aarch64_a57_initfn(Object *obj) cpu->id_pfr1 =3D 0x00011011; cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x10101105; - cpu->id_mmfr1 =3D 0x40000000; - cpu->id_mmfr2 =3D 0x01260000; - cpu->id_mmfr3 =3D 0x02102211; + cpu->isar.id_mmfr0 =3D 0x10101105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02102211; cpu->isar.id_isar0 =3D 0x02101110; cpu->isar.id_isar1 =3D 0x13112111; cpu->isar.id_isar2 =3D 0x21232042; @@ -177,10 +177,10 @@ static void aarch64_a53_initfn(Object *obj) cpu->id_pfr1 =3D 0x00011011; cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x10101105; - cpu->id_mmfr1 =3D 0x40000000; - cpu->id_mmfr2 =3D 0x01260000; - cpu->id_mmfr3 =3D 0x02102211; + cpu->isar.id_mmfr0 =3D 0x10101105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02102211; cpu->isar.id_isar0 =3D 0x02101110; cpu->isar.id_isar1 =3D 0x13112111; cpu->isar.id_isar2 =3D 0x21232042; @@ -230,10 +230,10 @@ static void aarch64_a72_initfn(Object *obj) cpu->id_pfr1 =3D 0x00011011; cpu->isar.id_dfr0 =3D 0x03010066; cpu->id_afr0 =3D 0x00000000; - cpu->id_mmfr0 =3D 0x10201105; - cpu->id_mmfr1 =3D 0x40000000; - cpu->id_mmfr2 =3D 0x01260000; - cpu->id_mmfr3 =3D 0x02102211; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02102211; cpu->isar.id_isar0 =3D 0x02101110; cpu->isar.id_isar1 =3D 0x13112111; cpu->isar.id_isar2 =3D 0x21232042; @@ -699,9 +699,9 @@ static void aarch64_max_initfn(Object *obj) u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); cpu->isar.id_isar6 =3D u; =20 - u =3D cpu->id_mmfr3; + u =3D cpu->isar.id_mmfr3; u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->id_mmfr3 =3D u; + cpu->isar.id_mmfr3 =3D u; =20 u =3D cpu->isar.id_aa64dfr0; u =3D FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 15a840f530b..441e8bb6022 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6910,22 +6910,22 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 4, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->id_mmfr0 }, + .resetvalue =3D cpu->isar.id_mmfr0 }, { .name =3D "ID_MMFR1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 5, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->id_mmfr1 }, + .resetvalue =3D cpu->isar.id_mmfr1 }, { .name =3D "ID_MMFR2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->id_mmfr2 }, + .resetvalue =3D cpu->isar.id_mmfr2 }, { .name =3D "ID_MMFR3", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 1, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->id_mmfr3 }, + .resetvalue =3D cpu->isar.id_mmfr3 }, { .name =3D "ID_ISAR0", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 0, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -6960,7 +6960,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 6, .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, - .resetvalue =3D cpu->id_mmfr4 }, + .resetvalue =3D cpu->isar.id_mmfr4 }, { .name =3D "ID_ISAR6", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 =3D = 7, .access =3D PL1_R, .type =3D ARM_CP_CONST, @@ -7409,7 +7409,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); define_arm_cp_regs(cpu, vmsa_cp_reginfo); /* TTCBR2 is introduced with ARMv8.2-A32HPD. */ - if (FIELD_EX32(cpu->id_mmfr4, ID_MMFR4, HPDS) !=3D 0) { + if (FIELD_EX32(cpu->isar.id_mmfr4, ID_MMFR4, HPDS) !=3D 0) { define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); } } diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index bca02553b25..7981ae3bc4e 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -111,6 +111,23 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) * Fortunately there is not yet anything in there that affects migrati= on. */ =20 + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, + ARM_CP15_REG32(0, 0, 1, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1, + ARM_CP15_REG32(0, 0, 1, 5)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2, + ARM_CP15_REG32(0, 0, 1, 6)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, + ARM_CP15_REG32(0, 0, 1, 7)); + if (read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, + ARM_CP15_REG32(0, 0, 2, 6))) { + /* + * Older kernels don't support reading ID_MMFR4 (a new in v8 + * register); assume it's zero. + */ + ahcf->isar.id_mmfr4 =3D 0; + } + /* * There is no way to read DBGDIDR, because currently 32-bit KVM * doesn't implement debug at all. Leave it at zero. diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index e8d7cea74cb..0ad96c3500a 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -565,6 +565,14 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures = *ahcf) */ err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_dfr0, ARM64_SYS_REG(3, 0, 0, 1, 2)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr0, + ARM64_SYS_REG(3, 0, 0, 1, 4)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr1, + ARM64_SYS_REG(3, 0, 0, 1, 5)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr2, + ARM64_SYS_REG(3, 0, 0, 1, 6)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr3, + ARM64_SYS_REG(3, 0, 0, 1, 7)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar0, ARM64_SYS_REG(3, 0, 0, 2, 0)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar1, @@ -577,6 +585,8 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures *= ahcf) ARM64_SYS_REG(3, 0, 0, 2, 4)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar5, ARM64_SYS_REG(3, 0, 0, 2, 5)); + err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_mmfr4, + ARM64_SYS_REG(3, 0, 0, 2, 6)); err |=3D read_sys_reg32(fdarray[2], &ahcf->isar.id_isar6, ARM64_SYS_REG(3, 0, 0, 2, 7)); =20 --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582291473; cv=none; d=zohomail.com; s=zohoarc; b=PBbK+Bg97jGufdvBG+t3ppEiA7nQyOFdzk5c034YoyWPFZveUNQ9PWMJ1IIiT9eWuBhsXEvnl6TG/NarKIrhCvTu6g4NLWnM2FITkRHVZp3Ap6VlA+wfJHpMy8N7LZVPbHJF8ozIngoBLuCAzbMUYQO5zHJGPmm9512N+XSxqjI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582291473; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=e7EtrQPP4lbwreuGx+Kl/vTgu6XaCFRgZZBcf+txFYM=; b=B07FbltvcTu8nKOqYPOtVVnOLsrCSg4N8T7anpI7Jyz6mXgH8EUJ/RgIPqVjUWSnRYXlJAMQFSHSJwBo90npHkcvE0b8HCrt/U4KDY8PNhpuez9ioxAfSocQ5QuJjpYqZ/ZBw33pHLt8Uc3Ds8sqrja+Gnb9U5cVuSUgEK3k+ok= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582291473789556.9192233850848; Fri, 21 Feb 2020 05:24:33 -0800 (PST) Received: from localhost ([::1]:57556 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58IC-0008Nv-KH for importer@patchew.org; Fri, 21 Feb 2020 08:24:32 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56888) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582a-0007ia-7C for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582Z-0003Bj-3Y for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:24 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:44162) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582Y-0003BD-TW for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:23 -0500 Received: by mail-wr1-x441.google.com with SMTP id m16so1976732wrx.11 for ; Fri, 21 Feb 2020 05:08:22 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=e7EtrQPP4lbwreuGx+Kl/vTgu6XaCFRgZZBcf+txFYM=; b=qxqtQAhJtgPVW55AUGEcg+1dYw1H3n31/Y9h1gAWo2jL7EOqyZodicKMDAJ6N88GhQ hzzxJNxS4Up3sGfCvSX+O0HJf2CCXW6ZsPy5sooixrH1QdRhp8jfeQJKG8WttCq5Fqd0 u6Jc9uR+sxn1k/OgmLZ9OaMKL2kVtRisSa3QuA1RkxQa/v/WX/dJwMUXZT5OrGwt9sD5 P7TVQW5SjlxAxMPMGsOb97qtgVSQ631lwT4Q23N74RC4GD5AAP8HNs0SzltRA6FSNbFT T1eAwQvu05u6nuFR4RHA+EKwUdj0rECtpZmEoax0VowwDmeT3QxMVZpoGdJc9Hv0BcKc 1iiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e7EtrQPP4lbwreuGx+Kl/vTgu6XaCFRgZZBcf+txFYM=; b=tWgursUStjVDfAdcylMrix7UaxIKHkTQ447kubK1c6AiqIrLGYuPBT+iVJKrfT+T0/ 49ZE8j6D99G36S4YMD6udUt3SFyVN5M0fEnU4zByVbCM7dpuDUgNvOt+4L4IbVAL3qj6 1S849BBirGfVy4PmcGpAxn5p3zArCc7bDXBXnTQU6zs2RZZ3Iw7ccrUHF4EALD3scFIx WhwGzkRDj4pXvMxyYuOKaIgfBGStvdQqqMHdkozMF8MrhTuJK/PuyOCAPO4dtLAFBixq z6Z978BJYssL+7MMIn4m9P4wlzcCDoEoL3a/n6KxdjU0Tu5OO86Wq6LySjHFFINb6qxO FZHQ== X-Gm-Message-State: APjAAAW+O1ZaTq2apsXuarANL4Ihvt3+AB3YpSWUxWzWrzZnf/EB+ztC 2NH1/X854in5dwl8+h/ASc6KJ4o765O8oQ== X-Google-Smtp-Source: APXvYqzJKqDCWzj2nMrulNwFlJHqfoxXn+xGLpFRhd74B8RnFrhNaDQXaVeq1uCIims1eH1Jl7CSlA== X-Received: by 2002:adf:fa87:: with SMTP id h7mr51177548wrr.172.1582290501558; Fri, 21 Feb 2020 05:08:21 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/52] target/arm: Use isar_feature function for testing AA32HPD feature Date: Fri, 21 Feb 2020 13:07:20 +0000 Message-Id: <20200221130740.7583-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Now we have moved ID_MMFR4 into the ARMISARegisters struct, we can define and use an isar_feature for the presence of the ARMv8.2-AA32HPD feature, rather than open-coding the test. While we're here, correct a comment typo which missed an 'A' from the feature name. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200214175116.9164-20-peter.maydell@linaro.org --- target/arm/cpu.h | 5 +++++ target/arm/helper.c | 4 ++-- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ba97fc75c1d..276030a5cf3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3526,6 +3526,11 @@ static inline bool isar_feature_aa32_pmu_8_4(const A= RMISARegisters *id) FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) !=3D 0xf; } =20 +static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) !=3D 0; +} + /* * 64-bit feature tests via id registers. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 441e8bb6022..19d749a1913 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7408,8 +7408,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) } else { define_arm_cp_regs(cpu, vmsa_pmsa_cp_reginfo); define_arm_cp_regs(cpu, vmsa_cp_reginfo); - /* TTCBR2 is introduced with ARMv8.2-A32HPD. */ - if (FIELD_EX32(cpu->isar.id_mmfr4, ID_MMFR4, HPDS) !=3D 0) { + /* TTCBR2 is introduced with ARMv8.2-AA32HPD. */ + if (cpu_isar_feature(aa32_hpd, cpu)) { define_one_arm_cp_reg(cpu, &ttbcr2_reginfo); } } --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582291783; cv=none; d=zohomail.com; s=zohoarc; b=RWg2uNxcngBabZtrHAVaoi5Ai2sHyiEQJA5Z1soVEIfGydxf+URpJxiSmUntI1E1VvUbar/B7u8VglYfnNTKtRwvJ2luZvkOPKqeNb9pm+urECUwhvJnC96615XPAhUQg8hhH9xByGGhHih+VEnAPI87JzMAbWqbW0LX0vwTx/4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582291783; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VpFi9ia1qLZ3xYtg0o1IQedP9GIh+OffzPSN9uWqPKI=; b=H8DU1PypLJkZ3TLiqRlG7JdXZHw3OyYPheJrrkF9EXDuulKfYokzHOoRzzLMsmTc4IPyAyKA1wzgcyGdYkYtLv1zx2rq43ATvrI0851egu+iH0DtU0nR+PzZHutDi3FFJUJ8foOhO7/5e/R/osHPVSPY6h6zFETg2bnU1Jd4Vh0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582291783900588.8062069654753; Fri, 21 Feb 2020 05:29:43 -0800 (PST) Received: from localhost ([::1]:57694 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58NC-0007LJ-OJ for importer@patchew.org; Fri, 21 Feb 2020 08:29:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56913) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582b-0007mD-Fi for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582a-0003DQ-ER for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:25 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:54442) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582a-0003By-86 for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:24 -0500 Received: by mail-wm1-x335.google.com with SMTP id n3so1726051wmk.4 for ; Fri, 21 Feb 2020 05:08:24 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.21 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:22 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=VpFi9ia1qLZ3xYtg0o1IQedP9GIh+OffzPSN9uWqPKI=; b=UwXYwoa3cPc+cUb74Qzy2tfbgswAMf9vj6Rs8RdJmI9ShU2itOh0gErIACSZ7p6j3g Dh9iDIEykS8hbCTrZbqk5CChd97oFAwzrJwH+3ZEvVhExsS8i/hPZp7z0bwk19IPvIOl H9Hj6GD/xP6Df/SbiYPF4NlCekLQDN8X9bNFoA4RiN67qr8Ta0crRr6YMN5rI+nOPMHA /HbZaPTDeCNh9bUXSun0qe96M6ZvvgcNTIPWOMNXjiLhmPGDB80yjcGhTE3nYWX8iSn/ 2isqr30XU+4H4ED1OMGQtz/dqpeuUZy5KWmyQapyguX6KfYR9bWPcHtZs4fL1o1OWOQ7 2WaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VpFi9ia1qLZ3xYtg0o1IQedP9GIh+OffzPSN9uWqPKI=; b=PWJlL3QjNj2pwA9Db3Axwe0Y5oFGCcjFC1qvpY9nFOzE2eWwUSxtxNSw2ipcIHfvXO Dz29rIO3XBMUUdjElteOQqZW7mLvJEavgB8l7JSyyqOJbxkpURJMle4yELKqNPYTrmVP bW/ORwrkDt/5QVn2ZOqirFSdz7H/g2E0ESPb/w+d1bD7b4tXOvU+UJkIWaf1MIwtP5kr T2Wr+R3Morzi58ba0I+cMQiYAeTU1DL+OzhtvAFzkc6JMScpDGQm09vIXgBivIJ+1jux L2f7nSzBFdDQUqjC6cwYl2YvoZA6DRe0WwAMWcG5xUaV0VTdwl5orFXg8WHDpo1ClzPn sD3A== X-Gm-Message-State: APjAAAU/GqnQ7GWingrJSNmjSTbHzAjiq7EatBRq897emBcj6FIgbf7s nWck+51pJWjdlwxy5Xvkn4WMlsQmGFMFLw== X-Google-Smtp-Source: APXvYqxzlPczsDuYAk4VVMRP1w+5gbUMN5M/hyJUIQhf+nXlxosNtPmxap0L6CoWyXqknrJ94XGptA== X-Received: by 2002:a7b:cd1a:: with SMTP id f26mr3618095wmj.184.1582290502618; Fri, 21 Feb 2020 05:08:22 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 33/52] target/arm: Use FIELD_EX32 for testing 32-bit fields Date: Fri, 21 Feb 2020 13:07:21 +0000 Message-Id: <20200221130740.7583-34-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::335 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Cut-and-paste errors mean we're using FIELD_EX64() to extract fields from some 32-bit ID register fields. Use FIELD_EX32() instead. (This makes no difference in behaviour, it's just more consistent.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200214175116.9164-21-peter.maydell@linaro.org --- target/arm/cpu.h | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 276030a5cf3..c6af3290caf 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3453,18 +3453,18 @@ static inline bool isar_feature_aa32_fp16_arith(con= st ARMISARegisters *id) static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id) { /* Return true if D16-D31 are implemented */ - return FIELD_EX64(id->mvfr0, MVFR0, SIMDREG) >=3D 2; + return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >=3D 2; } =20 static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0; + return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; } =20 static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id) { /* Return true if CPU supports double precision floating point */ - return FIELD_EX64(id->mvfr0, MVFR0, FPDP) > 0; + return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; } =20 /* @@ -3474,32 +3474,32 @@ static inline bool isar_feature_aa32_fpdp(const ARM= ISARegisters *id) */ static inline bool isar_feature_aa32_fp16_spconv(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 0; + return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 0; } =20 static inline bool isar_feature_aa32_fp16_dpconv(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr1, MVFR1, FPHP) > 1; + return FIELD_EX32(id->mvfr1, MVFR1, FPHP) > 1; } =20 static inline bool isar_feature_aa32_vsel(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 1; + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 1; } =20 static inline bool isar_feature_aa32_vcvt_dr(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 2; + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 2; } =20 static inline bool isar_feature_aa32_vrint(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 3; + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 3; } =20 static inline bool isar_feature_aa32_vminmaxnm(const ARMISARegisters *id) { - return FIELD_EX64(id->mvfr2, MVFR2, FPMISC) >=3D 4; + return FIELD_EX32(id->mvfr2, MVFR2, FPMISC) >=3D 4; } =20 static inline bool isar_feature_aa32_pan(const ARMISARegisters *id) --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582291781; cv=none; d=zohomail.com; s=zohoarc; b=J2YFQAEDNVN3t1cbRVii69Z36xzB3JoGipdKPuAyNr8h2Hr3RIEfk2i0KaguwOiHRU+Ng5ZPuH1kiF9Ft5OqI8pUOKq+rTL1HOpWWcS+2lA+aQI44I42ZCMRopH/xx0HYI9iLrAx5F0S2q3cb+IjYqCYzG14uq0GbDK2mJogrZM= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bB3JhtGyxiZSnQrMH3G4ul64IiYEPWbc6FcCjlU/wjY=; b=QSgF97U4BSdNF6VMo6tCZt0e9VHNduJgwOQPGwc+0QGo8rtGxOe5XVuvFqZmGNJ0Si X6PT4IhNVwllk6z72l97E6w8WbUKZqJE+VyIY/+uka2T5kGLdv4gKlwi4D4oMy5HDM63 XzBW0QVkSCbQyXx6xq3AcADp1SNjp1Pv2jsIBButA77aH22MRXayDZv3kcAocbD9POo0 xJbDpzVKHtR5WndKfxGl5iaBB07na7YL6WihlP+semyZoim4noX4bbuV0solvBAS+tCP HzKTjR5ucTJkKpuVk45yPUEjvYkEviuciMhDj7aABp1nX/O9vq5CxdxEmdQHy185Wk4J h9tQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bB3JhtGyxiZSnQrMH3G4ul64IiYEPWbc6FcCjlU/wjY=; b=c3WAXXMf9x1DSkVuVSLPfchb9j+am7FeyRIVoaKo3ZZN+Q6dDSEYSbMJ+QruFhTVrk fB+bnsYrNBJtQaXHY7CRP5WVWHtFKK0sQIhv5V/IWhrKFJvBKaGt2o0DGZgx4Pd2u+VT gWbVwhPLyVZQNdbbCrst6OrH7udVaq/8sAzYrjr2lqLA0gpj/HZstpxUQMDKtHb7Ckhn 1mGs/FB6IaZ5UJOOZovMmUfwYtlMUSTAeh/BmTm/tfKd7Llvs5JR0ARNwXVczy64XPq9 jO2J//QbEzoZKyR66qTflr5/FNj4DsUyK8aoggivaBDTh2vHjAUpx5ef6Bi2oWEm17vC 2sNw== X-Gm-Message-State: APjAAAVtrMmUqBGMui/zrZ7cSaXxHvqmjgJI/cXIvcwSVnWGDfgHBx+S covWk+ly+KbvBS4wn079gBFflfoskopBbw== X-Google-Smtp-Source: APXvYqwKKa1DubV8VKFejEVNwsHEjrKQJIUHWajQ49HwhJ3ivFbzyv7l+YtuTVaz9leRhvOOqgVLxQ== X-Received: by 2002:a5d:6987:: with SMTP id g7mr47294765wru.422.1582290504068; Fri, 21 Feb 2020 05:08:24 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 34/52] target/arm: Correctly implement ACTLR2, HACTLR2 Date: Fri, 21 Feb 2020 13:07:22 +0000 Message-Id: <20200221130740.7583-35-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The ACTLR2 and HACTLR2 AArch32 system registers didn't exist in ARMv7 or the original ARMv8. They were later added as optional registers, whose presence is signaled by the ID_MMFR4.AC2 field. From ARMv8.2 they are mandatory (ie ID_MMFR4.AC2 must be non-zero). We implemented HACTLR2 in commit 0e0456ab8895a5e85, but we incorrectly made it exist for all v8 CPUs, and we didn't implement ACTLR2 at all. Sort this out by implementing both registers only when they are supposed to exist, and setting the ID_MMFR4 bit for -cpu max. Note that this removes HACTLR2 from our Cortex-A53, -A47 and -A72 CPU models; this is correct, because those CPUs do not implement this register. Fixes: 0e0456ab8895a5e85 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20200214175116.9164-22-peter.maydell@linaro.org --- target/arm/cpu.h | 5 +++++ target/arm/cpu.c | 1 + target/arm/cpu64.c | 4 ++++ target/arm/helper.c | 32 +++++++++++++++++++++++--------- 4 files changed, 33 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c6af3290caf..b4c83a1cb52 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3531,6 +3531,11 @@ static inline bool isar_feature_aa32_hpd(const ARMIS= ARegisters *id) return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) !=3D 0; } =20 +static inline bool isar_feature_aa32_ac2(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_mmfr4, ID_MMFR4, AC2) !=3D 0; +} + /* * 64-bit feature tests via id registers. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c46bb5a5c09..9f618e120aa 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2718,6 +2718,7 @@ static void arm_max_initfn(Object *obj) =20 t =3D cpu->isar.id_mmfr4; t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ cpu->isar.id_mmfr4 =3D t; } #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 8430d432943..0929401a4dd 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -703,6 +703,10 @@ static void aarch64_max_initfn(Object *obj) u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ cpu->isar.id_mmfr3 =3D u; =20 + u =3D cpu->isar.id_mmfr4; + u =3D FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + cpu->isar.id_mmfr4 =3D u; + u =3D cpu->isar.id_aa64dfr0; u =3D FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ cpu->isar.id_aa64dfr0 =3D u; diff --git a/target/arm/helper.c b/target/arm/helper.c index 19d749a1913..1ac09f387ed 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6862,6 +6862,27 @@ static const ARMCPRegInfo ats1cp_reginfo[] =3D { }; #endif =20 +/* + * ACTLR2 and HACTLR2 map to ACTLR_EL1[63:32] and + * ACTLR_EL2[63:32]. They exist only if the ID_MMFR4.AC2 field + * is non-zero, which is never for ARMv7, optionally in ARMv8 + * and mandatorily for ARMv8.2 and up. + * ACTLR2 is banked for S and NS if EL3 is AArch32. Since QEMU's + * implementation is RAZ/WI we can ignore this detail, as we + * do for ACTLR. + */ +static const ARMCPRegInfo actlr2_hactlr2_reginfo[] =3D { + { .name =3D "ACTLR2", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + { .name =3D "HACTLR2", .state =3D ARM_CP_STATE_AA32, + .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 3, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, + .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -7623,15 +7644,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) REGINFO_SENTINEL }; define_arm_cp_regs(cpu, auxcr_reginfo); - if (arm_feature(env, ARM_FEATURE_V8)) { - /* HACTLR2 maps to ACTLR_EL2[63:32] and is not in ARMv7 */ - ARMCPRegInfo hactlr2_reginfo =3D { - .name =3D "HACTLR2", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D= 3, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 - }; - define_one_arm_cp_reg(cpu, &hactlr2_reginfo); + if (cpu_isar_feature(aa32_ac2, cpu)) { + define_arm_cp_regs(cpu, actlr2_hactlr2_reginfo); } } =20 --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582291783; cv=none; d=zohomail.com; s=zohoarc; b=Tpno552eWJsCMIeNRcKwR3pHvn201v8xzuwSglQG1er960Fkz8MM/kAOOKgWux09+5jSdvShYXiCDMZAtDya4ROfTf3taQSAI7FWO22XK5H3TUkE3eTBDHZHiK+OPfAc8y8yqKH5sScZO19cEyoytQ4B2ZFqA5H2/Qnv7mlIQFM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582291783; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PHKV1/R69DUOQ2y2kHNeixniaxNyfpVfww+ZCelTAL0=; b=nbQRd+1wyKYOqIerrfdyILccTzC2K/v6B0sJjLWyFcFn4VesNmzCec1CaszhEncve6+tZT8RNryure/ggqUJ07i79aGB1I+EUMLvFguWfHC3wV16atrdo1mTcXalWqOh+OVyWGP46J77yYX21DSk2AKSti25QtjHGduDQ0tnWWQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582291783311672.0826201455183; Fri, 21 Feb 2020 05:29:43 -0800 (PST) Received: from localhost ([::1]:57690 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58NC-0007I4-9h for importer@patchew.org; Fri, 21 Feb 2020 08:29:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56966) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582d-0007rj-L7 for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582c-0003Fp-HY for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:27 -0500 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:34886) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582c-0003Ej-AS for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:26 -0500 Received: by mail-wr1-x436.google.com with SMTP id w12so2011193wrt.2 for ; Fri, 21 Feb 2020 05:08:26 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.24 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=PHKV1/R69DUOQ2y2kHNeixniaxNyfpVfww+ZCelTAL0=; b=x4oHyZGDZVnko1eCtADM64LHcHWwujVvendAfE/oeBRyMJh8bvixA79FV6uvEI6/T1 m+yRI6RUoCA/91LiNr3ecyZ3BYgwikG8ULWNWjNfIhvc+6lx10KdDh1Kmv9RQZ548h8/ Vylth1PcPh0vtmlGJXi3ozuVfjsuwcDaK+Dx6FTvg6J9H4JxqwresHdwSEF9FceAIrC0 lrpIVJ4HJ/0PFcdGc8S9T3aADcXVB8ocqOoAqWmx59E12U4O5dbLbw903nKV5rhavXdg gaq73HcLqqJt6yo3M7Jn2gXHSNJ6Qa174tn2Pqakuyq11l8+4AJAyqPpwSV/tgNqOQIa WW3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PHKV1/R69DUOQ2y2kHNeixniaxNyfpVfww+ZCelTAL0=; b=bi6zPY74abh/eQdkQkS5U4INJ0ylhrU+e68vVd9v65x3ifedNL7vnysUez1O85l7lN /JnEd2pBMg/okeRbSzV5Iz98Dk26B28KioGnCN5HzQJyMLrgpEJShCvuxWqGjnNDho76 d/iV6aiPMi9ATPfpilTMGdkiR+YxTwOiI33Su86l/B6ZCl+rK6gzPjtrdbIE/9iIIgDD 49gZ9SWSBGCJ5qR9K5JrOkQK3NScvxMfFqs9yyumruA6Xrki52qBJimzebNoqWPGbbrn 1y9OIntbH87dltqXeZcIFHgK5MVZeTIbm6yTw6b4i17IGoZyD16/VPPPiC7KB6UVfyEy Nlxg== X-Gm-Message-State: APjAAAWhN7h3ak6bDNf+2afFpgEUsv1IhyauNVi9uahBnVWW5O+rGlSv bVZ6S8D7ui1dG1WRqbXgX4txQcZJhSDvvw== X-Google-Smtp-Source: APXvYqzzb2W2rwDPxNPWXQQPYdDws37F88a1o220sAazavrFUuKGKIrh2AEgY4h0sVuBf5kGSs3QHw== X-Received: by 2002:adf:f802:: with SMTP id s2mr51597258wrp.201.1582290505068; Fri, 21 Feb 2020 05:08:25 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 35/52] hw: usb: hcd-ohci: Move OHCISysBusState and TYPE_SYSBUS_OHCI to include file Date: Fri, 21 Feb 2020 13:07:23 +0000 Message-Id: <20200221130740.7583-36-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::436 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Guenter Roeck We need to be able to use OHCISysBusState outside hcd-ohci.c, so move it to its include file. Reviewed-by: Gerd Hoffmann Signed-off-by: Guenter Roeck Tested-by: Niek Linnenbank Message-id: 20200217204812.9857-2-linux@roeck-us.net Signed-off-by: Peter Maydell --- hw/usb/hcd-ohci.h | 16 ++++++++++++++++ hw/usb/hcd-ohci.c | 15 --------------- 2 files changed, 16 insertions(+), 15 deletions(-) diff --git a/hw/usb/hcd-ohci.h b/hw/usb/hcd-ohci.h index 16e3f1e13a3..5c8819aedf9 100644 --- a/hw/usb/hcd-ohci.h +++ b/hw/usb/hcd-ohci.h @@ -22,6 +22,7 @@ #define HCD_OHCI_H =20 #include "sysemu/dma.h" +#include "hw/usb.h" =20 /* Number of Downstream Ports on the root hub: */ #define OHCI_MAX_PORTS 15 @@ -90,6 +91,21 @@ typedef struct OHCIState { void (*ohci_die)(struct OHCIState *ohci); } OHCIState; =20 +#define TYPE_SYSBUS_OHCI "sysbus-ohci" +#define SYSBUS_OHCI(obj) OBJECT_CHECK(OHCISysBusState, (obj), TYPE_SYSBUS_= OHCI) + +typedef struct { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + OHCIState ohci; + char *masterbus; + uint32_t num_ports; + uint32_t firstport; + dma_addr_t dma_offset; +} OHCISysBusState; + extern const VMStateDescription vmstate_ohci_state; =20 void usb_ohci_init(OHCIState *ohci, DeviceState *dev, uint32_t num_ports, diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c index 8a94bd004a9..1e6e85e86a8 100644 --- a/hw/usb/hcd-ohci.c +++ b/hw/usb/hcd-ohci.c @@ -1870,21 +1870,6 @@ void ohci_sysbus_die(struct OHCIState *ohci) ohci_bus_stop(ohci); } =20 -#define TYPE_SYSBUS_OHCI "sysbus-ohci" -#define SYSBUS_OHCI(obj) OBJECT_CHECK(OHCISysBusState, (obj), TYPE_SYSBUS_= OHCI) - -typedef struct { - /*< private >*/ - SysBusDevice parent_obj; - /*< public >*/ - - OHCIState ohci; - char *masterbus; - uint32_t num_ports; - uint32_t firstport; - dma_addr_t dma_offset; -} OHCISysBusState; - static void ohci_realize_pxa(DeviceState *dev, Error **errp) { OHCISysBusState *s =3D SYSBUS_OHCI(dev); --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582291924; cv=none; d=zohomail.com; s=zohoarc; b=MDhQoldtD4APCFtK9F4s+BDiBpzq6CHVkOTXS9//S5bkVhgtGcI3yLemxyfHPbOdQMPi1BFLtrYj7EN5j8yK6ERUK/J823mwblQF2XZ/6M2DDUYWlEUTra8FkUg5UShTHwWDUxTlj8Iplig301O0wXFYtIUq7uocyJZBsfLPqlg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582291924; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=t9tzjIw7N1XSr73asGVBDssmnE7SvvmIcOpn2v7YIf0=; b=CYHyHTbRBrp3KDWsLi39smoYqv/80ZscWhJNgBBzpgdMDKlV3xZqdpKzxgZT7I05C96PCy8YP8t2XatkcQOz4QATueOsSKVba7wYjlFogzUdiYuebykceZPVwWE+mLn+H2wI33uiaoF+XI8GY4KqI4yJ/zcZuHCINiFAI0TlqDM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582291924888871.4046410676071; Fri, 21 Feb 2020 05:32:04 -0800 (PST) Received: from localhost ([::1]:57758 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58PS-0002Xo-Nl for importer@patchew.org; Fri, 21 Feb 2020 08:32:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:56990) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582e-0007ua-NJ for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582d-0003Hw-Mr for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:28 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:46965) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582d-0003GV-GU for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:27 -0500 Received: by mail-wr1-x435.google.com with SMTP id z7so1969081wrl.13 for ; Fri, 21 Feb 2020 05:08:27 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=t9tzjIw7N1XSr73asGVBDssmnE7SvvmIcOpn2v7YIf0=; b=pYgqCxHezS+bau4Uy2dCB/kdEHpdBTpGWw7LN21n53skMgZDXegbAEJJuX04zW/O8k jZ8bIaHbosJPn1etS5bhDxrPyqe1h5tCFxG15K05MuXQ3T33sd2MXFlumuDFeqNSprrZ J6J7uikWIHZSJM5fnJkMKZTq9eHwjRqvnHjqK86nOEkKO6v7WFkpBuiyWkgkuHKk7vYE cr01YsvDeE3vuoM71hncxeDOuBLw9A0VMdPmEjSmKa9Xn85pmxGZ6umgtOht5FIBYDQk k3PRvZ3AYMaqvLbUu5Tv5T/R8q8/ZtWmrPtJ/x4Sv8cf4vy+nN8NBQ364sSr/0qaCJDy UYVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t9tzjIw7N1XSr73asGVBDssmnE7SvvmIcOpn2v7YIf0=; b=JFE2wgoJQhAIez0hbbnUCogKcgDnrjBnVr7AM3gKb7wgBTPBXqEUAJFIsojGSYS1vs RJ4RlMXfBWkpqE/X0zaqBAiHV5HYaYnB/XWaiZ0wRsfRxFvhH4nBK40HWb5F17n3dpxs Rp+/sl/fUYSINf62nqdpLwlhuLJD+ZAGvwZekFdlecKK/1ju5o33khkYXKvLtkHcqZIW Yi2TTYB9q52sLGKtAMaUCycefa/NMmj+2oqR7sV5+Wl/IEP5bsW3fIp+VVktDnudIqA9 iDESWDwVSwuH4k6+FLTvzfXSB9qycnoa14I4UT6APeoXuj8zbZpYnnvDa5ftUz6qCksv AzRw== X-Gm-Message-State: APjAAAWJiDlc1lcc3olrKpdQ6q3zwXf9rGz/v0cWMkrEEETFKYq9TPwE ldoVkTCpD4R78xjPs3sVSMMVF3AhEFBz0Q== X-Google-Smtp-Source: APXvYqwBJ3SNO1TXs9p7aO+hm5weDGJo1uV9jBq/0aO+cerqbTqkQ/FWDQO64m5y9QpKBG+1FBsLnA== X-Received: by 2002:adf:ea88:: with SMTP id s8mr48553137wrm.293.1582290506138; Fri, 21 Feb 2020 05:08:26 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 36/52] hcd-ehci: Introduce "companion-enable" sysbus property Date: Fri, 21 Feb 2020 13:07:24 +0000 Message-Id: <20200221130740.7583-37-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::435 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Guenter Roeck We'll use this property in a follow-up patch to insantiate an EHCI bus with companion support. Reviewed-by: Gerd Hoffmann Signed-off-by: Guenter Roeck Tested-by: Niek Linnenbank Message-id: 20200217204812.9857-3-linux@roeck-us.net Signed-off-by: Peter Maydell --- hw/usb/hcd-ehci-sysbus.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c index 8d4738565e5..b22fb258be7 100644 --- a/hw/usb/hcd-ehci-sysbus.c +++ b/hw/usb/hcd-ehci-sysbus.c @@ -33,6 +33,8 @@ static const VMStateDescription vmstate_ehci_sysbus =3D { =20 static Property ehci_sysbus_properties[] =3D { DEFINE_PROP_UINT32("maxframes", EHCISysBusState, ehci.maxframes, 128), + DEFINE_PROP_BOOL("companion-enable", EHCISysBusState, ehci.companion_e= nable, + false), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582292134; cv=none; d=zohomail.com; s=zohoarc; b=PwlKpoAvFtWyyGeYVST6ArPBa717P1wmM00wOQUnMBp/vY4+8g6ZzZLisAwZH5L8vXYZT8fxDAZZws2Wt2/2MybY4nbEL0fD/+M55rhimFIPi2yE8g6l6iBCeKz62jjZIFFQRs0+cdE3LEFS2bcc20dB38XKAt16cWcrChUSvw4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582292134; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=H0G7hXnYvNjV+3hg2JTTqmpRPLVuBfK7HJumeWhX01g=; b=fpnIeSKfi4lNwUIJgCldqZKgKkB+JvCcDfmCc8VyZBeCRJSS8xobPXoxYUZC8aB8iV8VgkX21w80XMcNRAcqrDjbS61A9y80fMv+LRGcaipmQ4JvrdFymkI6zTpUlNCb+kYWVJIU3OJVa/AG4I9dqnqbwbuXEG7L4tSqzlKtadY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582292134539418.09574753947606; Fri, 21 Feb 2020 05:35:34 -0800 (PST) Received: from localhost ([::1]:57854 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58Sr-0007Q1-Gg for importer@patchew.org; Fri, 21 Feb 2020 08:35:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57013) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582g-0007z0-Ao for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582e-0003LI-T6 for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:30 -0500 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:45255) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582e-0003J2-M1 for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:28 -0500 Received: by mail-wr1-x435.google.com with SMTP id g3so1979405wrs.12 for ; Fri, 21 Feb 2020 05:08:28 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=H0G7hXnYvNjV+3hg2JTTqmpRPLVuBfK7HJumeWhX01g=; b=meTFDMpHcmCtVdBg/0lVITSarUn7N2NIPdPgMrLfRzBB68GnBLA6U0nw7b/8W17h2t srkuzT5CW1ezBH6rDwA9XOniRqkoqiI8HS4SvGkCPucNm/K6wImd7Cq+FKUO2XgzPNwC o3lmRjDzpugjJqCoXCDRs44GNX2RnaJr3T1Z9KIdBvygsEutsyOc0Ttn09hX1HBMhhmh UL/6XLCHniHrZP1ukwKrAvCYaUcwCCqML4VOvS8ZjeOuV3gokoLrD1p1teUTVvhI2n3b Y5BAUIJNkocakokyo73+sypMjqQe9+8OvsG4t/wfUVG3suVfQ37s9mHILAwRTnEm9gr7 dAHA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=H0G7hXnYvNjV+3hg2JTTqmpRPLVuBfK7HJumeWhX01g=; b=J7vnQg5AXrpLXdQSH/fgcNlkKWMjYQcZ/RkDU/aeyCFm31TjUFxjnpuWFEp8aPZXxb ESwiS8bNn3t2w7sQ+EF+WBr33lhv87as9eo8oR7EfPhRxMFTe0/j1zDqI5fvNQ4MPyeF VjKtLqWkAsSU2TjDfAgvfY/8vi1i8J8MPonMP4glKhDmnMcZNe6SZjiLR3l/z3WE4p2k Z7yNKtrz3A1sxI83NqSNBIwh2SwCBX0mZ/txNjyK93TymgYkbqJjy6WOPd6FAhF+Gzk6 yJFiIIi5yPTlTADuOr3xKe5oN/B58i0B7IYf7L4x2UjrbT3JkGYEJCXQJ072N5VzHJt6 4CIQ== X-Gm-Message-State: APjAAAVtf1NS9LkJxJ4QFm5dyclcqeFVufrj1zB0FucZWcQVsP/FGSDO VNJ/84ylqK7khRtwq98QcJqYJxMTmul+7w== X-Google-Smtp-Source: APXvYqzomLCJYx/cL2Y3xPl6H+nCgLDgGY1Dpcl3zg/Gy0QiI2KGkeC0vp4hL3w58VtjseA/gvieEg== X-Received: by 2002:a5d:6703:: with SMTP id o3mr46559849wru.235.1582290507235; Fri, 21 Feb 2020 05:08:27 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 37/52] arm: allwinner: Wire up USB ports Date: Fri, 21 Feb 2020 13:07:25 +0000 Message-Id: <20200221130740.7583-38-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::435 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Guenter Roeck Instantiate EHCI and OHCI controllers on Allwinner A10. OHCI ports are modeled as companions of the respective EHCI ports. With this patch applied, USB controllers are discovered and instantiated when booting the cubieboard machine with a recent Linux kernel. ehci-platform 1c14000.usb: EHCI Host Controller ehci-platform 1c14000.usb: new USB bus registered, assigned bus number 1 ehci-platform 1c14000.usb: irq 26, io mem 0x01c14000 ehci-platform 1c14000.usb: USB 2.0 started, EHCI 1.00 ehci-platform 1c1c000.usb: EHCI Host Controller ehci-platform 1c1c000.usb: new USB bus registered, assigned bus number 2 ehci-platform 1c1c000.usb: irq 31, io mem 0x01c1c000 ehci-platform 1c1c000.usb: USB 2.0 started, EHCI 1.00 ohci-platform 1c14400.usb: Generic Platform OHCI controller ohci-platform 1c14400.usb: new USB bus registered, assigned bus number 3 ohci-platform 1c14400.usb: irq 27, io mem 0x01c14400 ohci-platform 1c1c400.usb: Generic Platform OHCI controller ohci-platform 1c1c400.usb: new USB bus registered, assigned bus number 4 ohci-platform 1c1c400.usb: irq 32, io mem 0x01c1c400 usb 2-1: new high-speed USB device number 2 using ehci-platform usb-storage 2-1:1.0: USB Mass Storage device detected scsi host1: usb-storage 2-1:1.0 usb 3-1: new full-speed USB device number 2 using ohci-platform input: QEMU QEMU USB Mouse as /devices/platform/soc/1c14400.usb/usb3/3-1/3-= 1:1.0/0003:0627:0001.0001/input/input0 Reviewed-by: Gerd Hoffmann Signed-off-by: Guenter Roeck Tested-by: Niek Linnenbank Message-id: 20200217204812.9857-4-linux@roeck-us.net Signed-off-by: Peter Maydell --- include/hw/arm/allwinner-a10.h | 6 +++++ hw/arm/allwinner-a10.c | 43 ++++++++++++++++++++++++++++++++++ 2 files changed, 49 insertions(+) diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h index 40d0b1d9c05..8af724548f0 100644 --- a/include/hw/arm/allwinner-a10.h +++ b/include/hw/arm/allwinner-a10.h @@ -8,12 +8,16 @@ #include "hw/intc/allwinner-a10-pic.h" #include "hw/net/allwinner_emac.h" #include "hw/ide/ahci.h" +#include "hw/usb/hcd-ohci.h" +#include "hw/usb/hcd-ehci.h" =20 #include "target/arm/cpu.h" =20 =20 #define AW_A10_SDRAM_BASE 0x40000000 =20 +#define AW_A10_NUM_USB 2 + #define TYPE_AW_A10 "allwinner-a10" #define AW_A10(obj) OBJECT_CHECK(AwA10State, (obj), TYPE_AW_A10) =20 @@ -28,6 +32,8 @@ typedef struct AwA10State { AwEmacState emac; AllwinnerAHCIState sata; MemoryRegion sram_a; + EHCISysBusState ehci[AW_A10_NUM_USB]; + OHCISysBusState ohci[AW_A10_NUM_USB]; } AwA10State; =20 #endif diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index 1cde1656116..2ae9c15311c 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -24,11 +24,15 @@ #include "hw/arm/allwinner-a10.h" #include "hw/misc/unimp.h" #include "sysemu/sysemu.h" +#include "hw/boards.h" +#include "hw/usb/hcd-ohci.h" =20 #define AW_A10_PIC_REG_BASE 0x01c20400 #define AW_A10_PIT_REG_BASE 0x01c20c00 #define AW_A10_UART0_REG_BASE 0x01c28000 #define AW_A10_EMAC_BASE 0x01c0b000 +#define AW_A10_EHCI_BASE 0x01c14000 +#define AW_A10_OHCI_BASE 0x01c14400 #define AW_A10_SATA_BASE 0x01c18000 =20 static void aw_a10_init(Object *obj) @@ -49,6 +53,17 @@ static void aw_a10_init(Object *obj) =20 sysbus_init_child_obj(obj, "sata", &s->sata, sizeof(s->sata), TYPE_ALLWINNER_AHCI); + + if (machine_usb(current_machine)) { + int i; + + for (i =3D 0; i < AW_A10_NUM_USB; i++) { + sysbus_init_child_obj(obj, "ehci[*]", OBJECT(&s->ehci[i]), + sizeof(s->ehci[i]), TYPE_PLATFORM_EHCI); + sysbus_init_child_obj(obj, "ohci[*]", OBJECT(&s->ohci[i]), + sizeof(s->ohci[i]), TYPE_SYSBUS_OHCI); + } + } } =20 static void aw_a10_realize(DeviceState *dev, Error **errp) @@ -121,6 +136,34 @@ static void aw_a10_realize(DeviceState *dev, Error **e= rrp) serial_mm_init(get_system_memory(), AW_A10_UART0_REG_BASE, 2, qdev_get_gpio_in(dev, 1), 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); + + if (machine_usb(current_machine)) { + int i; + + for (i =3D 0; i < AW_A10_NUM_USB; i++) { + char bus[16]; + + sprintf(bus, "usb-bus.%d", i); + + object_property_set_bool(OBJECT(&s->ehci[i]), true, + "companion-enable", &error_fatal); + object_property_set_bool(OBJECT(&s->ehci[i]), true, "realized", + &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ehci[i]), 0, + AW_A10_EHCI_BASE + i * 0x8000); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0, + qdev_get_gpio_in(dev, 39 + i)); + + object_property_set_str(OBJECT(&s->ohci[i]), bus, "masterbus", + &error_fatal); + object_property_set_bool(OBJECT(&s->ohci[i]), true, "realized", + &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->ohci[i]), 0, + AW_A10_OHCI_BASE + i * 0x8000); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->ohci[i]), 0, + qdev_get_gpio_in(dev, 64 + i)); + } + } } =20 static void aw_a10_class_init(ObjectClass *oc, void *data) --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582291337; cv=none; d=zohomail.com; s=zohoarc; b=kmAa1WhSnnP/CeitQfBQqlwOW2Gv39hm13tbBuQuME/OpuybsE9x3ZNGY2i9PU1J2wHlHMWJ8wjC20WKQgTmo6JuF6P0a3AmghJGZ+Dn3UEiU4c+/hHrdvaAcbXJdc6/LgIFlLvtELC5wOv7D5nmStV81VlP92tNM6pn85GoJnI= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hN4UH3X9JNvxb1NnYu91jhQ7eMwZKKpYApAth0WQOEE=; b=l7Erx8rjnwzNmAmsvJit67E3GsN2UQR8MnRsFLmUPuVNe7x5C17IBMUmS9WMVEhOpq QsnN0XtmUFxBIFfrcZohxYZ2EO7tymqlTYFpqhboohJ6NdOEnMlUETgvnvA83YJQfU5W itoKw9eHDtevDwk7S6X5qXXiFGybZ+JSpj5xE3oVFw/wu9SG51rFTZ335IYpjjUkWygg lGlTHJwX8aCaeQ7XFnFlFhBDXtFVdoMiuC8u2/SdAn/kWtuPCVjhWJpmgj/6PQGRgF+A dFHoMSumZgeaWRZ9IMqnQBKPeolbUXUudhh3cV6NviVadrG4Gs2tK5MrYLqIim925Ixa +5jQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hN4UH3X9JNvxb1NnYu91jhQ7eMwZKKpYApAth0WQOEE=; b=QCxEld/xkcWVsapBt9pHFNQo+spIcmnuX3OpApdJWr5Lo4XFuSD49VIirqhtsnBfVY /Cp7iiPJl4RG8F8H3c6OBc/ERDGlF8w7sgjuYDLEN1UOcZ73dzz/9X0T3rhFR796mc9i hgjGl3KaharRHfrrH/J3YZ89IckE+8s1ZroDIBmj7i8JacmTafou2ln80w0pI2mZJIDN UOmhe5UQgfGixSHR+P1Vt/bjh1declLWCLHCu3KKjN8hFcQYlRIk9mzLwLRS89RFWvi3 Euvuhag+GiUNvIISqR3zBoMAneE9MWkFcpB8uSfjRd7liZ9j0/VS2Xj1crIbhu0M53f3 uuGw== X-Gm-Message-State: APjAAAVtEMYC3KANlTiTVN8d/1sx0fHxjZwjnDLKFP4gxpMVALTTVJxb KEevYsecnC33COQPLY9JmbOzk1btUwqWzw== X-Google-Smtp-Source: APXvYqycChn84kWGbUrnCi6dTrd8t7AUdOmtGB4GqJ6em5tWID+gMiSlv2MgwHtYFWlZip2T7gqByA== X-Received: by 2002:a5d:560d:: with SMTP id l13mr22512898wrv.222.1582290508530; Fri, 21 Feb 2020 05:08:28 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 38/52] target/arm: Vectorize USHL and SSHL Date: Fri, 21 Feb 2020 13:07:26 +0000 Message-Id: <20200221130740.7583-39-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson These instructions shift left or right depending on the sign of the input, and 7 bits are significant to the shift. This requires several masks and selects in addition to the actual shifts to form the complete answer. That said, the operation is still a small improvement even for two 64-bit elements -- 13 vector operations instead of 2 * 7 integer operations. Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20200216214232.4230-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.h | 11 +- target/arm/translate.h | 6 + target/arm/neon_helper.c | 33 ---- target/arm/translate-a64.c | 18 +-- target/arm/translate.c | 299 +++++++++++++++++++++++++++++++++++-- target/arm/vec_helper.c | 88 +++++++++++ 6 files changed, 389 insertions(+), 66 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index aa3d8cd08fa..459a278b5c4 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -303,14 +303,8 @@ DEF_HELPER_2(neon_abd_s16, i32, i32, i32) DEF_HELPER_2(neon_abd_u32, i32, i32, i32) DEF_HELPER_2(neon_abd_s32, i32, i32, i32) =20 -DEF_HELPER_2(neon_shl_u8, i32, i32, i32) -DEF_HELPER_2(neon_shl_s8, i32, i32, i32) DEF_HELPER_2(neon_shl_u16, i32, i32, i32) DEF_HELPER_2(neon_shl_s16, i32, i32, i32) -DEF_HELPER_2(neon_shl_u32, i32, i32, i32) -DEF_HELPER_2(neon_shl_s32, i32, i32, i32) -DEF_HELPER_2(neon_shl_u64, i64, i64, i64) -DEF_HELPER_2(neon_shl_s64, i64, i64, i64) DEF_HELPER_2(neon_rshl_u8, i32, i32, i32) DEF_HELPER_2(neon_rshl_s8, i32, i32, i32) DEF_HELPER_2(neon_rshl_u16, i32, i32, i32) @@ -697,6 +691,11 @@ DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f3= 2, ptr) DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, ptr) =20 +DEF_HELPER_FLAGS_4(gvec_sshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_ushl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_ushl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/translate.h b/target/arm/translate.h index 5b167c416a2..d9ea0c99cc8 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -278,6 +278,8 @@ uint64_t vfp_expand_imm(int size, uint8_t imm8); extern const GVecGen3 mla_op[4]; extern const GVecGen3 mls_op[4]; extern const GVecGen3 cmtst_op[4]; +extern const GVecGen3 sshl_op[4]; +extern const GVecGen3 ushl_op[4]; extern const GVecGen2i ssra_op[4]; extern const GVecGen2i usra_op[4]; extern const GVecGen2i sri_op[4]; @@ -287,6 +289,10 @@ extern const GVecGen4 sqadd_op[4]; extern const GVecGen4 uqsub_op[4]; extern const GVecGen4 sqsub_op[4]; void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); +void gen_ushl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); +void gen_sshl_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); +void gen_ushl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); +void gen_sshl_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); =20 /* * Forward to the isar_feature_* tests given a DisasContext pointer. diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c index 42590567236..c581ffb7d3c 100644 --- a/target/arm/neon_helper.c +++ b/target/arm/neon_helper.c @@ -615,24 +615,9 @@ NEON_VOP(abd_u32, neon_u32, 1) } else { \ dest =3D src1 << tmp; \ }} while (0) -NEON_VOP(shl_u8, neon_u8, 4) NEON_VOP(shl_u16, neon_u16, 2) -NEON_VOP(shl_u32, neon_u32, 1) #undef NEON_FN =20 -uint64_t HELPER(neon_shl_u64)(uint64_t val, uint64_t shiftop) -{ - int8_t shift =3D (int8_t)shiftop; - if (shift >=3D 64 || shift <=3D -64) { - val =3D 0; - } else if (shift < 0) { - val >>=3D -shift; - } else { - val <<=3D shift; - } - return val; -} - #define NEON_FN(dest, src1, src2) do { \ int8_t tmp; \ tmp =3D (int8_t)src2; \ @@ -645,27 +630,9 @@ uint64_t HELPER(neon_shl_u64)(uint64_t val, uint64_t s= hiftop) } else { \ dest =3D src1 << tmp; \ }} while (0) -NEON_VOP(shl_s8, neon_s8, 4) NEON_VOP(shl_s16, neon_s16, 2) -NEON_VOP(shl_s32, neon_s32, 1) #undef NEON_FN =20 -uint64_t HELPER(neon_shl_s64)(uint64_t valop, uint64_t shiftop) -{ - int8_t shift =3D (int8_t)shiftop; - int64_t val =3D valop; - if (shift >=3D 64) { - val =3D 0; - } else if (shift <=3D -64) { - val >>=3D 63; - } else if (shift < 0) { - val >>=3D -shift; - } else { - val <<=3D shift; - } - return val; -} - #define NEON_FN(dest, src1, src2) do { \ int8_t tmp; \ tmp =3D (int8_t)src2; \ diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index bd68588a710..9fbcf7d2f95 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -8744,9 +8744,9 @@ static void handle_3same_64(DisasContext *s, int opco= de, bool u, break; case 0x8: /* SSHL, USHL */ if (u) { - gen_helper_neon_shl_u64(tcg_rd, tcg_rn, tcg_rm); + gen_ushl_i64(tcg_rd, tcg_rn, tcg_rm); } else { - gen_helper_neon_shl_s64(tcg_rd, tcg_rn, tcg_rm); + gen_sshl_i64(tcg_rd, tcg_rn, tcg_rm); } break; case 0x9: /* SQSHL, UQSHL */ @@ -11141,6 +11141,10 @@ static void disas_simd_3same_int(DisasContext *s, = uint32_t insn) is_q ? 16 : 8, vec_full_reg_size(s), (u ? uqsub_op : sqsub_op) + size); return; + case 0x08: /* SSHL, USHL */ + gen_gvec_op3(s, is_q, rd, rn, rm, + u ? &ushl_op[size] : &sshl_op[size]); + return; case 0x0c: /* SMAX, UMAX */ if (u) { gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size); @@ -11256,16 +11260,6 @@ static void disas_simd_3same_int(DisasContext *s, = uint32_t insn) genfn =3D fns[size][u]; break; } - case 0x8: /* SSHL, USHL */ - { - static NeonGenTwoOpFn * const fns[3][2] =3D { - { gen_helper_neon_shl_s8, gen_helper_neon_shl_u8 }, - { gen_helper_neon_shl_s16, gen_helper_neon_shl_u16 }, - { gen_helper_neon_shl_s32, gen_helper_neon_shl_u32 }, - }; - genfn =3D fns[size][u]; - break; - } case 0x9: /* SQSHL, UQSHL */ { static NeonGenTwoOpEnvFn * const fns[3][2] =3D { diff --git a/target/arm/translate.c b/target/arm/translate.c index 93f028f256b..a96104d6b42 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3575,13 +3575,13 @@ static inline void gen_neon_shift_narrow(int size, = TCGv_i32 var, TCGv_i32 shift, if (u) { switch (size) { case 1: gen_helper_neon_shl_u16(var, var, shift); break; - case 2: gen_helper_neon_shl_u32(var, var, shift); break; + case 2: gen_ushl_i32(var, var, shift); break; default: abort(); } } else { switch (size) { case 1: gen_helper_neon_shl_s16(var, var, shift); break; - case 2: gen_helper_neon_shl_s32(var, var, shift); break; + case 2: gen_sshl_i32(var, var, shift); break; default: abort(); } } @@ -4384,6 +4384,280 @@ const GVecGen3 cmtst_op[4] =3D { .vece =3D MO_64 }, }; =20 +void gen_ushl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift) +{ + TCGv_i32 lval =3D tcg_temp_new_i32(); + TCGv_i32 rval =3D tcg_temp_new_i32(); + TCGv_i32 lsh =3D tcg_temp_new_i32(); + TCGv_i32 rsh =3D tcg_temp_new_i32(); + TCGv_i32 zero =3D tcg_const_i32(0); + TCGv_i32 max =3D tcg_const_i32(32); + + /* + * Rely on the TCG guarantee that out of range shifts produce + * unspecified results, not undefined behaviour (i.e. no trap). + * Discard out-of-range results after the fact. + */ + tcg_gen_ext8s_i32(lsh, shift); + tcg_gen_neg_i32(rsh, lsh); + tcg_gen_shl_i32(lval, src, lsh); + tcg_gen_shr_i32(rval, src, rsh); + tcg_gen_movcond_i32(TCG_COND_LTU, dst, lsh, max, lval, zero); + tcg_gen_movcond_i32(TCG_COND_LTU, dst, rsh, max, rval, dst); + + tcg_temp_free_i32(lval); + tcg_temp_free_i32(rval); + tcg_temp_free_i32(lsh); + tcg_temp_free_i32(rsh); + tcg_temp_free_i32(zero); + tcg_temp_free_i32(max); +} + +void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift) +{ + TCGv_i64 lval =3D tcg_temp_new_i64(); + TCGv_i64 rval =3D tcg_temp_new_i64(); + TCGv_i64 lsh =3D tcg_temp_new_i64(); + TCGv_i64 rsh =3D tcg_temp_new_i64(); + TCGv_i64 zero =3D tcg_const_i64(0); + TCGv_i64 max =3D tcg_const_i64(64); + + /* + * Rely on the TCG guarantee that out of range shifts produce + * unspecified results, not undefined behaviour (i.e. no trap). + * Discard out-of-range results after the fact. + */ + tcg_gen_ext8s_i64(lsh, shift); + tcg_gen_neg_i64(rsh, lsh); + tcg_gen_shl_i64(lval, src, lsh); + tcg_gen_shr_i64(rval, src, rsh); + tcg_gen_movcond_i64(TCG_COND_LTU, dst, lsh, max, lval, zero); + tcg_gen_movcond_i64(TCG_COND_LTU, dst, rsh, max, rval, dst); + + tcg_temp_free_i64(lval); + tcg_temp_free_i64(rval); + tcg_temp_free_i64(lsh); + tcg_temp_free_i64(rsh); + tcg_temp_free_i64(zero); + tcg_temp_free_i64(max); +} + +static void gen_ushl_vec(unsigned vece, TCGv_vec dst, + TCGv_vec src, TCGv_vec shift) +{ + TCGv_vec lval =3D tcg_temp_new_vec_matching(dst); + TCGv_vec rval =3D tcg_temp_new_vec_matching(dst); + TCGv_vec lsh =3D tcg_temp_new_vec_matching(dst); + TCGv_vec rsh =3D tcg_temp_new_vec_matching(dst); + TCGv_vec msk, max; + + tcg_gen_neg_vec(vece, rsh, shift); + if (vece =3D=3D MO_8) { + tcg_gen_mov_vec(lsh, shift); + } else { + msk =3D tcg_temp_new_vec_matching(dst); + tcg_gen_dupi_vec(vece, msk, 0xff); + tcg_gen_and_vec(vece, lsh, shift, msk); + tcg_gen_and_vec(vece, rsh, rsh, msk); + tcg_temp_free_vec(msk); + } + + /* + * Rely on the TCG guarantee that out of range shifts produce + * unspecified results, not undefined behaviour (i.e. no trap). + * Discard out-of-range results after the fact. + */ + tcg_gen_shlv_vec(vece, lval, src, lsh); + tcg_gen_shrv_vec(vece, rval, src, rsh); + + max =3D tcg_temp_new_vec_matching(dst); + tcg_gen_dupi_vec(vece, max, 8 << vece); + + /* + * The choice of LT (signed) and GEU (unsigned) are biased toward + * the instructions of the x86_64 host. For MO_8, the whole byte + * is significant so we must use an unsigned compare; otherwise we + * have already masked to a byte and so a signed compare works. + * Other tcg hosts have a full set of comparisons and do not care. + */ + if (vece =3D=3D MO_8) { + tcg_gen_cmp_vec(TCG_COND_GEU, vece, lsh, lsh, max); + tcg_gen_cmp_vec(TCG_COND_GEU, vece, rsh, rsh, max); + tcg_gen_andc_vec(vece, lval, lval, lsh); + tcg_gen_andc_vec(vece, rval, rval, rsh); + } else { + tcg_gen_cmp_vec(TCG_COND_LT, vece, lsh, lsh, max); + tcg_gen_cmp_vec(TCG_COND_LT, vece, rsh, rsh, max); + tcg_gen_and_vec(vece, lval, lval, lsh); + tcg_gen_and_vec(vece, rval, rval, rsh); + } + tcg_gen_or_vec(vece, dst, lval, rval); + + tcg_temp_free_vec(max); + tcg_temp_free_vec(lval); + tcg_temp_free_vec(rval); + tcg_temp_free_vec(lsh); + tcg_temp_free_vec(rsh); +} + +static const TCGOpcode ushl_list[] =3D { + INDEX_op_neg_vec, INDEX_op_shlv_vec, + INDEX_op_shrv_vec, INDEX_op_cmp_vec, 0 +}; + +const GVecGen3 ushl_op[4] =3D { + { .fniv =3D gen_ushl_vec, + .fno =3D gen_helper_gvec_ushl_b, + .opt_opc =3D ushl_list, + .vece =3D MO_8 }, + { .fniv =3D gen_ushl_vec, + .fno =3D gen_helper_gvec_ushl_h, + .opt_opc =3D ushl_list, + .vece =3D MO_16 }, + { .fni4 =3D gen_ushl_i32, + .fniv =3D gen_ushl_vec, + .opt_opc =3D ushl_list, + .vece =3D MO_32 }, + { .fni8 =3D gen_ushl_i64, + .fniv =3D gen_ushl_vec, + .opt_opc =3D ushl_list, + .vece =3D MO_64 }, +}; + +void gen_sshl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i32 shift) +{ + TCGv_i32 lval =3D tcg_temp_new_i32(); + TCGv_i32 rval =3D tcg_temp_new_i32(); + TCGv_i32 lsh =3D tcg_temp_new_i32(); + TCGv_i32 rsh =3D tcg_temp_new_i32(); + TCGv_i32 zero =3D tcg_const_i32(0); + TCGv_i32 max =3D tcg_const_i32(31); + + /* + * Rely on the TCG guarantee that out of range shifts produce + * unspecified results, not undefined behaviour (i.e. no trap). + * Discard out-of-range results after the fact. + */ + tcg_gen_ext8s_i32(lsh, shift); + tcg_gen_neg_i32(rsh, lsh); + tcg_gen_shl_i32(lval, src, lsh); + tcg_gen_umin_i32(rsh, rsh, max); + tcg_gen_sar_i32(rval, src, rsh); + tcg_gen_movcond_i32(TCG_COND_LEU, lval, lsh, max, lval, zero); + tcg_gen_movcond_i32(TCG_COND_LT, dst, lsh, zero, rval, lval); + + tcg_temp_free_i32(lval); + tcg_temp_free_i32(rval); + tcg_temp_free_i32(lsh); + tcg_temp_free_i32(rsh); + tcg_temp_free_i32(zero); + tcg_temp_free_i32(max); +} + +void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift) +{ + TCGv_i64 lval =3D tcg_temp_new_i64(); + TCGv_i64 rval =3D tcg_temp_new_i64(); + TCGv_i64 lsh =3D tcg_temp_new_i64(); + TCGv_i64 rsh =3D tcg_temp_new_i64(); + TCGv_i64 zero =3D tcg_const_i64(0); + TCGv_i64 max =3D tcg_const_i64(63); + + /* + * Rely on the TCG guarantee that out of range shifts produce + * unspecified results, not undefined behaviour (i.e. no trap). + * Discard out-of-range results after the fact. + */ + tcg_gen_ext8s_i64(lsh, shift); + tcg_gen_neg_i64(rsh, lsh); + tcg_gen_shl_i64(lval, src, lsh); + tcg_gen_umin_i64(rsh, rsh, max); + tcg_gen_sar_i64(rval, src, rsh); + tcg_gen_movcond_i64(TCG_COND_LEU, lval, lsh, max, lval, zero); + tcg_gen_movcond_i64(TCG_COND_LT, dst, lsh, zero, rval, lval); + + tcg_temp_free_i64(lval); + tcg_temp_free_i64(rval); + tcg_temp_free_i64(lsh); + tcg_temp_free_i64(rsh); + tcg_temp_free_i64(zero); + tcg_temp_free_i64(max); +} + +static void gen_sshl_vec(unsigned vece, TCGv_vec dst, + TCGv_vec src, TCGv_vec shift) +{ + TCGv_vec lval =3D tcg_temp_new_vec_matching(dst); + TCGv_vec rval =3D tcg_temp_new_vec_matching(dst); + TCGv_vec lsh =3D tcg_temp_new_vec_matching(dst); + TCGv_vec rsh =3D tcg_temp_new_vec_matching(dst); + TCGv_vec tmp =3D tcg_temp_new_vec_matching(dst); + + /* + * Rely on the TCG guarantee that out of range shifts produce + * unspecified results, not undefined behaviour (i.e. no trap). + * Discard out-of-range results after the fact. + */ + tcg_gen_neg_vec(vece, rsh, shift); + if (vece =3D=3D MO_8) { + tcg_gen_mov_vec(lsh, shift); + } else { + tcg_gen_dupi_vec(vece, tmp, 0xff); + tcg_gen_and_vec(vece, lsh, shift, tmp); + tcg_gen_and_vec(vece, rsh, rsh, tmp); + } + + /* Bound rsh so out of bound right shift gets -1. */ + tcg_gen_dupi_vec(vece, tmp, (8 << vece) - 1); + tcg_gen_umin_vec(vece, rsh, rsh, tmp); + tcg_gen_cmp_vec(TCG_COND_GT, vece, tmp, lsh, tmp); + + tcg_gen_shlv_vec(vece, lval, src, lsh); + tcg_gen_sarv_vec(vece, rval, src, rsh); + + /* Select in-bound left shift. */ + tcg_gen_andc_vec(vece, lval, lval, tmp); + + /* Select between left and right shift. */ + if (vece =3D=3D MO_8) { + tcg_gen_dupi_vec(vece, tmp, 0); + tcg_gen_cmpsel_vec(TCG_COND_LT, vece, dst, lsh, tmp, rval, lval); + } else { + tcg_gen_dupi_vec(vece, tmp, 0x80); + tcg_gen_cmpsel_vec(TCG_COND_LT, vece, dst, lsh, tmp, lval, rval); + } + + tcg_temp_free_vec(lval); + tcg_temp_free_vec(rval); + tcg_temp_free_vec(lsh); + tcg_temp_free_vec(rsh); + tcg_temp_free_vec(tmp); +} + +static const TCGOpcode sshl_list[] =3D { + INDEX_op_neg_vec, INDEX_op_umin_vec, INDEX_op_shlv_vec, + INDEX_op_sarv_vec, INDEX_op_cmp_vec, INDEX_op_cmpsel_vec, 0 +}; + +const GVecGen3 sshl_op[4] =3D { + { .fniv =3D gen_sshl_vec, + .fno =3D gen_helper_gvec_sshl_b, + .opt_opc =3D sshl_list, + .vece =3D MO_8 }, + { .fniv =3D gen_sshl_vec, + .fno =3D gen_helper_gvec_sshl_h, + .opt_opc =3D sshl_list, + .vece =3D MO_16 }, + { .fni4 =3D gen_sshl_i32, + .fniv =3D gen_sshl_vec, + .opt_opc =3D sshl_list, + .vece =3D MO_32 }, + { .fni8 =3D gen_sshl_i64, + .fniv =3D gen_sshl_vec, + .opt_opc =3D sshl_list, + .vece =3D MO_64 }, +}; + static void gen_uqadd_vec(unsigned vece, TCGv_vec t, TCGv_vec sat, TCGv_vec a, TCGv_vec b) { @@ -4787,6 +5061,12 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) vec_size, vec_size); } return 0; + + case NEON_3R_VSHL: + /* Note the operation is vshl vd,vm,vn */ + tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size, + u ? &ushl_op[size] : &sshl_op[size]); + return 0; } =20 if (size =3D=3D 3) { @@ -4795,13 +5075,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) neon_load_reg64(cpu_V0, rn + pass); neon_load_reg64(cpu_V1, rm + pass); switch (op) { - case NEON_3R_VSHL: - if (u) { - gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0); - } else { - gen_helper_neon_shl_s64(cpu_V0, cpu_V1, cpu_V0); - } - break; case NEON_3R_VQSHL: if (u) { gen_helper_neon_qshl_u64(cpu_V0, cpu_env, @@ -4836,7 +5109,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) } pairwise =3D 0; switch (op) { - case NEON_3R_VSHL: case NEON_3R_VQSHL: case NEON_3R_VRSHL: case NEON_3R_VQRSHL: @@ -4916,9 +5188,6 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) case NEON_3R_VHSUB: GEN_NEON_INTEGER_OP(hsub); break; - case NEON_3R_VSHL: - GEN_NEON_INTEGER_OP(shl); - break; case NEON_3R_VQSHL: GEN_NEON_INTEGER_OP_ENV(qshl); break; @@ -5327,9 +5596,9 @@ static int disas_neon_data_insn(DisasContext *s, uint= 32_t insn) } } else { if (input_unsigned) { - gen_helper_neon_shl_u64(cpu_V0, in, tmp64); + gen_ushl_i64(cpu_V0, in, tmp64); } else { - gen_helper_neon_shl_s64(cpu_V0, in, tmp64); + gen_sshl_i64(cpu_V0, in, tmp64); } } tmp =3D tcg_temp_new_i32(); diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index dedef62403a..fcb36639036 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -1046,3 +1046,91 @@ void HELPER(gvec_fmlal_idx_a64)(void *vd, void *vn, = void *vm, do_fmlal_idx(vd, vn, vm, &env->vfp.fp_status, desc, get_flush_inputs_to_zero(&env->vfp.fp_status_f16)); } + +void HELPER(gvec_sshl_b)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc); + int8_t *d =3D vd, *n =3D vn, *m =3D vm; + + for (i =3D 0; i < opr_sz; ++i) { + int8_t mm =3D m[i]; + int8_t nn =3D n[i]; + int8_t res =3D 0; + if (mm >=3D 0) { + if (mm < 8) { + res =3D nn << mm; + } + } else { + res =3D nn >> (mm > -8 ? -mm : 7); + } + d[i] =3D res; + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + +void HELPER(gvec_sshl_h)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc); + int16_t *d =3D vd, *n =3D vn, *m =3D vm; + + for (i =3D 0; i < opr_sz / 2; ++i) { + int8_t mm =3D m[i]; /* only 8 bits of shift are significant */ + int16_t nn =3D n[i]; + int16_t res =3D 0; + if (mm >=3D 0) { + if (mm < 16) { + res =3D nn << mm; + } + } else { + res =3D nn >> (mm > -16 ? -mm : 15); + } + d[i] =3D res; + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + +void HELPER(gvec_ushl_b)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc); + uint8_t *d =3D vd, *n =3D vn, *m =3D vm; + + for (i =3D 0; i < opr_sz; ++i) { + int8_t mm =3D m[i]; + uint8_t nn =3D n[i]; + uint8_t res =3D 0; + if (mm >=3D 0) { + if (mm < 8) { + res =3D nn << mm; + } + } else { + if (mm > -8) { + res =3D nn >> -mm; + } + } + d[i] =3D res; + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} + +void HELPER(gvec_ushl_h)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, opr_sz =3D simd_oprsz(desc); + uint16_t *d =3D vd, *n =3D vn, *m =3D vm; + + for (i =3D 0; i < opr_sz / 2; ++i) { + int8_t mm =3D m[i]; /* only 8 bits of shift are significant */ + uint16_t nn =3D n[i]; + uint16_t res =3D 0; + if (mm >=3D 0) { + if (mm < 16) { + res =3D nn << mm; + } + } else { + if (mm > -16) { + res =3D nn >> -mm; + } + } + d[i] =3D res; + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=pMcXx100DJsU2s8kjjPiWFATTF6GUFEH9VSiVRyHDeM=; b=o7qNCOsYq9h+nQE0rcozEZGuq3JvdecZrjzzVW/Jx5ZRccnSmzSd7MWYVyj+skPSa1 qcVHFt6MqTLOb65iVgbO7kv+6YeXWljmYsuFrB1m3JKPRigOL2ZZtGTV0j8UzKfJivg0 Dv/oMl485MurfARdQgsz5Lu8zog0i1p6NuNKBxvA2vF1BpWtqSnRh2hepu/mxbhpOgjR utTcv5RoEZF5IQvkgVSljG76wRW4e0m4Ijy9WGYSBd5JslYnqVdjkqDcnF4NaeO2ulxQ GKOFNaZ6NcgIUtflsk/RUuNLIOoDo9ifOhHNuDveq/V2t/ZoKpj4CnkT8m02yRO0WCk7 LmOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pMcXx100DJsU2s8kjjPiWFATTF6GUFEH9VSiVRyHDeM=; b=Fkx01UzFP/CVlUSTb8GbCKzUDA/DMnthpNf6j1PqeQRZIx/dsyGYIiK2wqWgp1awSg uKfqvyv1QuDgLYMqnkPzI00RBSMd9NRk+5pgDZ7TWnbirdUnri+AQmONA5XTN42v1Wow 9bsDcB83gIKfFGY9QRsezWywnB4IeeIzc5xuXAhEb4RNIN+wk7yG1wPpVZSiyji3C3q8 kqavbqnjjhy11V+LQiFQVCjn99iOCEB3baxVFNXnqukWPWZxFLglZJZg9C0E0TrBXOZO KaF3FzaovfG9RH4tp3e4KZ791BLT1s0tt9ArNyDYZH7JvnX79rz6Ff2AAgC3yMIxCZCG L5xQ== X-Gm-Message-State: APjAAAWGgwEHokenwSVzdUu+IFGgFi0sL+KekKyn/MEj1wNFNXC/9Yra Aol9D6qYnj1hRnJSvAgNSoBu0POlNsZgmA== X-Google-Smtp-Source: APXvYqw80m60BTJnKeKmGrX/5gbJI0sLvis2WA546nCzri/vRoc3STwop5FQlsIk3ozpX5rN9OOgiA== X-Received: by 2002:a5d:6a52:: with SMTP id t18mr46751935wrw.335.1582290510277; Fri, 21 Feb 2020 05:08:30 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 39/52] target/arm: Convert PMUL.8 to gvec Date: Fri, 21 Feb 2020 13:07:27 +0000 Message-Id: <20200221130740.7583-40-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::432 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson The gvec form will be needed for implementing SVE2. Extend the implementation to operate on uint64_t instead of uint32_t. Use a counted inner loop instead of terminating when op1 goes to zero, looking toward the required implementation for ARMv8.4-DIT. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20200216214232.4230-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.h | 3 ++- target/arm/neon_helper.c | 22 ---------------------- target/arm/translate-a64.c | 10 +++------- target/arm/translate.c | 11 ++++------- target/arm/vec_helper.c | 30 ++++++++++++++++++++++++++++++ 5 files changed, 39 insertions(+), 37 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 459a278b5c4..82450a3f965 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -342,7 +342,6 @@ DEF_HELPER_2(neon_sub_u8, i32, i32, i32) DEF_HELPER_2(neon_sub_u16, i32, i32, i32) DEF_HELPER_2(neon_mul_u8, i32, i32, i32) DEF_HELPER_2(neon_mul_u16, i32, i32, i32) -DEF_HELPER_2(neon_mul_p8, i32, i32, i32) DEF_HELPER_2(neon_mull_p8, i64, i32, i32) =20 DEF_HELPER_2(neon_tst_u8, i32, i32, i32) @@ -696,6 +695,8 @@ DEF_HELPER_FLAGS_4(gvec_sshl_h, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_ushl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_ushl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(gvec_pmul_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c index c581ffb7d3c..9e7a9a1ac54 100644 --- a/target/arm/neon_helper.c +++ b/target/arm/neon_helper.c @@ -1131,28 +1131,6 @@ NEON_VOP(mul_u16, neon_u16, 2) =20 /* Polynomial multiplication is like integer multiplication except the partial products are XORed, not added. */ -uint32_t HELPER(neon_mul_p8)(uint32_t op1, uint32_t op2) -{ - uint32_t mask; - uint32_t result; - result =3D 0; - while (op1) { - mask =3D 0; - if (op1 & 1) - mask |=3D 0xff; - if (op1 & (1 << 8)) - mask |=3D (0xff << 8); - if (op1 & (1 << 16)) - mask |=3D (0xff << 16); - if (op1 & (1 << 24)) - mask |=3D (0xff << 24); - result ^=3D op2 & mask; - op1 =3D (op1 >> 1) & 0x7f7f7f7f; - op2 =3D (op2 << 1) & 0xfefefefe; - } - return result; -} - uint64_t HELPER(neon_mull_p8)(uint32_t op1, uint32_t op2) { uint64_t result =3D 0; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9fbcf7d2f95..a4fbb18a535 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11169,9 +11169,10 @@ static void disas_simd_3same_int(DisasContext *s, = uint32_t insn) case 0x13: /* MUL, PMUL */ if (!u) { /* MUL */ gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_mul, size); - return; + } else { /* PMUL */ + gen_gvec_op3_ool(s, is_q, rd, rn, rm, 0, gen_helper_gvec_pmul_= b); } - break; + return; case 0x12: /* MLA, MLS */ if (u) { gen_gvec_op3(s, is_q, rd, rn, rm, &mls_op[size]); @@ -11301,11 +11302,6 @@ static void disas_simd_3same_int(DisasContext *s, = uint32_t insn) genfn =3D fns[size][u]; break; } - case 0x13: /* MUL, PMUL */ - assert(u); /* PMUL */ - assert(size =3D=3D 0); - genfn =3D gen_helper_neon_mul_p8; - break; case 0x16: /* SQDMULH, SQRDMULH */ { static NeonGenTwoOpEnvFn * const fns[2][2] =3D { diff --git a/target/arm/translate.c b/target/arm/translate.c index a96104d6b42..e8f79899ca7 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5007,16 +5007,17 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) =20 case NEON_3R_VMUL: /* VMUL */ if (u) { - /* Polynomial case allows only P8 and is handled below. */ + /* Polynomial case allows only P8. */ if (size !=3D 0) { return 1; } + tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_s= ize, + 0, gen_helper_gvec_pmul_b); } else { tcg_gen_gvec_mul(size, rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size); - return 0; } - break; + return 0; =20 case NEON_3R_VML: /* VMLA, VMLS */ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size, @@ -5206,10 +5207,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) tmp2 =3D neon_load_reg(rd, pass); gen_neon_add(size, tmp, tmp2); break; - case NEON_3R_VMUL: - /* VMUL.P8; other cases already eliminated. */ - gen_helper_neon_mul_p8(tmp, tmp, tmp2); - break; case NEON_3R_VPMAX: GEN_NEON_INTEGER_OP(pmax); break; diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index fcb36639036..854de0e2795 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -1134,3 +1134,33 @@ void HELPER(gvec_ushl_h)(void *vd, void *vn, void *v= m, uint32_t desc) } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +/* + * 8x8->8 polynomial multiply. + * + * Polynomial multiplication is like integer multiplication except the + * partial products are XORed, not added. + * + * TODO: expose this as a generic vector operation, as it is a common + * crypto building block. + */ +void HELPER(gvec_pmul_b)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, j, opr_sz =3D simd_oprsz(desc); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + + for (i =3D 0; i < opr_sz / 8; ++i) { + uint64_t nn =3D n[i]; + uint64_t mm =3D m[i]; + uint64_t rr =3D 0; + + for (j =3D 0; j < 8; ++j) { + uint64_t mask =3D (nn & 0x0101010101010101ull) * 0xff; + rr ^=3D mm & mask; + mm =3D (mm << 1) & 0xfefefefefefefefeull; + nn >>=3D 1; + } + d[i] =3D rr; + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582292230; cv=none; d=zohomail.com; s=zohoarc; b=kTodbQqVJrm3/M6vMeu/gb6S6QFXMFgwSaLGPhT7iebQ7HbA/5Y6W0tP1OMX5Yvem2TYhzvB8P45Pe1zcMivQpaom7dsPsqiFSiCN5WwXjBljFfBFUjr0cBNJrK++EMXn/z6/52yYdo64k3axmF4Rnw6Mz7/VjXUD7rEwaj/8k8= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.30 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=iUVU/+ftsP0eFe2/eddKC3VG38It06fh6nIBl+/TJ9M=; b=CXOU+qDsVUuFWnX2gXCGJdBXOv8oHczxGWwXC8wknPFb3HjNs4emOvIZecVvmUfvK6 4mcRnwu1H+XsLeNYo3BvddWdT2q4mCqXDCh5PHk5mRwZ0oVUaeWKo+6Qt8OtJib0qd5T E0Z2M93gf7hGAqxxpdoZ4Jn93ZXj7spP2lfo+8EXicrwD9NgLj5J6CpITEpy36FbToQm ECfI6ZnechQhQR0Ez1vWUNcp3zSkljfDHWt9Xto/naV4z5Os7+R68MolYYxZa5rAmPc4 0AglEEvzMTizVPygHjukGUNb31tOhoyZU977o+5R3pT/325izTjyV8R+34JHlTuB1f4m 7VyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iUVU/+ftsP0eFe2/eddKC3VG38It06fh6nIBl+/TJ9M=; b=IffTSmbbdFonMiQ9L1fnXQ4s6B2r+LmA/nkbjjcuAJKW6+46RRerjSZReSxf4m6OT7 Dx/B/HSqzONdhr3Cm3L+2EP3zxmHMSYc6o4NbGEhJPVldVWRUgf6ptjDWlRYHwd3ltFN 0uR0e41luo1h/x/QEKgk0djshH264fOG5XW1s/N7NDT4uD2DJerN7HQaQxdHlaCXhvNn SrdW6rizA2dXKi2uAlacfryyJlQof7qYdXRqixDv8QOyXX5Nh0tHIySRoB7DdXbG4/4i 0A05iVlnJSfPuNuOB74sCYxyVbBhRmClA+L49FLKoQPp0XOx3IZC3BiZN9Umatd4dEwu whcQ== X-Gm-Message-State: APjAAAWc8vHdaro3S2+2+5KoTD2pepJV3MYEcPQb1Ik++vUTGuxsvU0H lnOgNLDr4EzKOBPh6UWLXvNPdULCWuhxUQ== X-Google-Smtp-Source: APXvYqz6ObGoJmfcfLlxPmepuxjKBO5ATVpyWQSEVBiErsG7RdaZ3XKhfh7OtsRG0ZDR4nqiVI6FqQ== X-Received: by 2002:a1c:16:: with SMTP id 22mr3902326wma.8.1582290511497; Fri, 21 Feb 2020 05:08:31 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 40/52] target/arm: Convert PMULL.64 to gvec Date: Fri, 21 Feb 2020 13:07:28 +0000 Message-Id: <20200221130740.7583-41-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32b X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson The gvec form will be needed for implementing SVE2. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20200216214232.4230-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.h | 4 +--- target/arm/neon_helper.c | 30 ------------------------------ target/arm/translate-a64.c | 28 +++------------------------- target/arm/translate.c | 16 ++-------------- target/arm/vec_helper.c | 33 +++++++++++++++++++++++++++++++++ 5 files changed, 39 insertions(+), 72 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 82450a3f965..4352fae3dbf 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -562,9 +562,6 @@ DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32,= i32, i32) DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_2(dc_zva, void, env, i64) =20 -DEF_HELPER_FLAGS_2(neon_pmull_64_lo, TCG_CALL_NO_RWG_SE, i64, i64, i64) -DEF_HELPER_FLAGS_2(neon_pmull_64_hi, TCG_CALL_NO_RWG_SE, i64, i64, i64) - DEF_HELPER_FLAGS_5(gvec_qrdmlah_s16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s16, TCG_CALL_NO_RWG, @@ -696,6 +693,7 @@ DEF_HELPER_FLAGS_4(gvec_ushl_b, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_ushl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 DEF_HELPER_FLAGS_4(gvec_pmul_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_pmull_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 #ifdef TARGET_AARCH64 #include "helper-a64.h" diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c index 9e7a9a1ac54..6a107da0e11 100644 --- a/target/arm/neon_helper.c +++ b/target/arm/neon_helper.c @@ -2152,33 +2152,3 @@ void HELPER(neon_zip16)(void *vd, void *vm) rm[0] =3D m0; rd[0] =3D d0; } - -/* Helper function for 64 bit polynomial multiply case: - * perform PolynomialMult(op1, op2) and return either the top or - * bottom half of the 128 bit result. - */ -uint64_t HELPER(neon_pmull_64_lo)(uint64_t op1, uint64_t op2) -{ - int bitnum; - uint64_t res =3D 0; - - for (bitnum =3D 0; bitnum < 64; bitnum++) { - if (op1 & (1ULL << bitnum)) { - res ^=3D op2 << bitnum; - } - } - return res; -} -uint64_t HELPER(neon_pmull_64_hi)(uint64_t op1, uint64_t op2) -{ - int bitnum; - uint64_t res =3D 0; - - /* bit 0 of op1 can't influence the high 64 bits at all */ - for (bitnum =3D 1; bitnum < 64; bitnum++) { - if (op1 & (1ULL << bitnum)) { - res ^=3D op2 >> (64 - bitnum); - } - } - return res; -} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a4fbb18a535..03ce879497d 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10657,30 +10657,6 @@ static void handle_3rd_narrowing(DisasContext *s, = int is_q, int is_u, int size, clear_vec_high(s, is_q, rd); } =20 -static void handle_pmull_64(DisasContext *s, int is_q, int rd, int rn, int= rm) -{ - /* PMULL of 64 x 64 -> 128 is an odd special case because it - * is the only three-reg-diff instruction which produces a - * 128-bit wide result from a single operation. However since - * it's possible to calculate the two halves more or less - * separately we just use two helper calls. - */ - TCGv_i64 tcg_op1 =3D tcg_temp_new_i64(); - TCGv_i64 tcg_op2 =3D tcg_temp_new_i64(); - TCGv_i64 tcg_res =3D tcg_temp_new_i64(); - - read_vec_element(s, tcg_op1, rn, is_q, MO_64); - read_vec_element(s, tcg_op2, rm, is_q, MO_64); - gen_helper_neon_pmull_64_lo(tcg_res, tcg_op1, tcg_op2); - write_vec_element(s, tcg_res, rd, 0, MO_64); - gen_helper_neon_pmull_64_hi(tcg_res, tcg_op1, tcg_op2); - write_vec_element(s, tcg_res, rd, 1, MO_64); - - tcg_temp_free_i64(tcg_op1); - tcg_temp_free_i64(tcg_op2); - tcg_temp_free_i64(tcg_res); -} - /* AdvSIMD three different * 31 30 29 28 24 23 22 21 20 16 15 12 11 10 9 5 4 0 * +---+---+---+-----------+------+---+------+--------+-----+------+------+ @@ -10745,7 +10721,9 @@ static void disas_simd_three_reg_diff(DisasContext = *s, uint32_t insn) if (!fp_access_check(s)) { return; } - handle_pmull_64(s, is_q, rd, rn, rm); + /* The Q field specifies lo/hi half input for this insn. */ + gen_gvec_op3_ool(s, true, rd, rn, rm, is_q, + gen_helper_gvec_pmull_q); return; } goto is_widening; diff --git a/target/arm/translate.c b/target/arm/translate.c index e8f79899ca7..57d61c4aa57 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5870,23 +5870,11 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) * outside the loop below as it only performs a single pas= s. */ if (op =3D=3D 14 && size =3D=3D 2) { - TCGv_i64 tcg_rn, tcg_rm, tcg_rd; - if (!dc_isar_feature(aa32_pmull, s)) { return 1; } - tcg_rn =3D tcg_temp_new_i64(); - tcg_rm =3D tcg_temp_new_i64(); - tcg_rd =3D tcg_temp_new_i64(); - neon_load_reg64(tcg_rn, rn); - neon_load_reg64(tcg_rm, rm); - gen_helper_neon_pmull_64_lo(tcg_rd, tcg_rn, tcg_rm); - neon_store_reg64(tcg_rd, rd); - gen_helper_neon_pmull_64_hi(tcg_rd, tcg_rn, tcg_rm); - neon_store_reg64(tcg_rd, rd + 1); - tcg_temp_free_i64(tcg_rn); - tcg_temp_free_i64(tcg_rm); - tcg_temp_free_i64(tcg_rd); + tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, 16, 16, + 0, gen_helper_gvec_pmull_q); return 0; } =20 diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 854de0e2795..79d2624f7b1 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -1164,3 +1164,36 @@ void HELPER(gvec_pmul_b)(void *vd, void *vn, void *v= m, uint32_t desc) } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +/* + * 64x64->128 polynomial multiply. + * Because of the lanes are not accessed in strict columns, + * this probably cannot be turned into a generic helper. + */ +void HELPER(gvec_pmull_q)(void *vd, void *vn, void *vm, uint32_t desc) +{ + intptr_t i, j, opr_sz =3D simd_oprsz(desc); + intptr_t hi =3D simd_data(desc); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + + for (i =3D 0; i < opr_sz / 8; i +=3D 2) { + uint64_t nn =3D n[i + hi]; + uint64_t mm =3D m[i + hi]; + uint64_t rhi =3D 0; + uint64_t rlo =3D 0; + + /* Bit 0 can only influence the low 64-bit result. */ + if (nn & 1) { + rlo =3D mm; + } + + for (j =3D 1; j < 64; ++j) { + uint64_t mask =3D -((nn >> j) & 1); + rlo ^=3D (mm << j) & mask; + rhi ^=3D (mm >> (64 - j)) & mask; + } + d[i] =3D rlo; + d[i + 1] =3D rhi; + } + clear_tail(d, opr_sz, simd_maxsz(desc)); +} --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.31 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=N2CqiOBafoAQTHmhaY96Iclyx2NNEgn6MWbHgGdY59o=; b=GNbFM9MYYTQPZyvNGhKWjn1llBgEaUsFapHZcOGo/v4VAnC/2v9RAJ2StFEr3M6+PK KRki88ZxBNOBsjcFQuC9zxdpuvIiA5QrxmLExMXEUV2TBV8kp2fyP+0+Fv6LG0dnGmZb aI76+8sTM70e1YiZzj0eaP+RubjUd4tkBPKygk/LBckT/sRTZtXMItvA7EnYl5UPG6lD 2dF5iZ5mj37RlwDIkjmjxixHRM6gU7Um7uYaTyxlV8WVrp7hne8ng1sMQNvgfcA6fa1Y m0suyMFGmEbzO/sNEenPp5w+jtYo2RY2vswWze+Woxz01wd2SAmknvwUpJl/3MzB+5fJ A/Xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N2CqiOBafoAQTHmhaY96Iclyx2NNEgn6MWbHgGdY59o=; b=nbOdszRM7ZDrDHw916JI11ejW1efLNFZ21G7sac8z8Qd8YzYnh5KARbWxcyb3WKVFN e0hIIQa5kttMZPDHz0zrdP3cGF+EFwpF1M1AGqR+78Omchpg8yFWMojawCaPAsQHIL+Q Y70JqZagGkGHfTcmuVapRCVYzSpaoujZ1MXQpiQIHYSBKpjt12QdYoH/lhLV9iFoDoVP y1b2JV/4NA9bzOg3lfO4cG9QDmt2HPZQKcsxL/UQOlo2nwkIrWXjt7HlJIMW23k3vzXe x3jbkvVUv0H+W6jBP5iZh04OUQ3VWrkXBgmiZachnb62gjXdxQjidpA0feWRjj5bUY8O +0qg== X-Gm-Message-State: APjAAAWzKVR5cG+PPfagDIcav+SFP9JF0wTZNAYGV3wHFysvdfvG/upk lXpNPFuSfnUlRKh+ymBvgDZJApUXRVxApQ== X-Google-Smtp-Source: APXvYqxTXkv8JwZSS/qoLmGgLFLKtF8ABZJYIE8TMa9tALWpWmIAfsrIKk4XJ87saCCk/2oCEWf+nw== X-Received: by 2002:a7b:cf39:: with SMTP id m25mr3803729wmg.146.1582290512714; Fri, 21 Feb 2020 05:08:32 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 41/52] target/arm: Convert PMULL.8 to gvec Date: Fri, 21 Feb 2020 13:07:29 +0000 Message-Id: <20200221130740.7583-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::336 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson We still need two different helpers, since NEON and SVE2 get the inputs from different locations within the source vector. However, we can convert both to the same internal form for computation. The sve2 helper is not used yet, but adding it with this patch helps illustrate why the neon changes are helpful. Tested-by: Alex Benn=C3=A9e Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson Message-id: 20200216214232.4230-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper-sve.h | 2 ++ target/arm/helper.h | 3 +- target/arm/neon_helper.c | 32 -------------------- target/arm/translate-a64.c | 27 +++++++++++------ target/arm/translate.c | 26 ++++++++--------- target/arm/vec_helper.c | 60 ++++++++++++++++++++++++++++++++++++++ 6 files changed, 95 insertions(+), 55 deletions(-) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 9e79182ab46..2f472791558 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -1574,3 +1574,5 @@ DEF_HELPER_FLAGS_6(sve_stdd_le_zd, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr, tl, i32) DEF_HELPER_FLAGS_6(sve_stdd_be_zd, TCG_CALL_NO_WG, void, env, ptr, ptr, ptr, tl, i32) + +DEF_HELPER_FLAGS_4(sve2_pmull_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/target/arm/helper.h b/target/arm/helper.h index 4352fae3dbf..fcbf5041213 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -342,7 +342,6 @@ DEF_HELPER_2(neon_sub_u8, i32, i32, i32) DEF_HELPER_2(neon_sub_u16, i32, i32, i32) DEF_HELPER_2(neon_mul_u8, i32, i32, i32) DEF_HELPER_2(neon_mul_u16, i32, i32, i32) -DEF_HELPER_2(neon_mull_p8, i64, i32, i32) =20 DEF_HELPER_2(neon_tst_u8, i32, i32, i32) DEF_HELPER_2(neon_tst_u16, i32, i32, i32) @@ -695,6 +694,8 @@ DEF_HELPER_FLAGS_4(gvec_ushl_h, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_pmul_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_pmull_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) =20 +DEF_HELPER_FLAGS_4(neon_pmull_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c index 6a107da0e11..c7a8438b42a 100644 --- a/target/arm/neon_helper.c +++ b/target/arm/neon_helper.c @@ -1129,38 +1129,6 @@ NEON_VOP(mul_u8, neon_u8, 4) NEON_VOP(mul_u16, neon_u16, 2) #undef NEON_FN =20 -/* Polynomial multiplication is like integer multiplication except the - partial products are XORed, not added. */ -uint64_t HELPER(neon_mull_p8)(uint32_t op1, uint32_t op2) -{ - uint64_t result =3D 0; - uint64_t mask; - uint64_t op2ex =3D op2; - op2ex =3D (op2ex & 0xff) | - ((op2ex & 0xff00) << 8) | - ((op2ex & 0xff0000) << 16) | - ((op2ex & 0xff000000) << 24); - while (op1) { - mask =3D 0; - if (op1 & 1) { - mask |=3D 0xffff; - } - if (op1 & (1 << 8)) { - mask |=3D (0xffffU << 16); - } - if (op1 & (1 << 16)) { - mask |=3D (0xffffULL << 32); - } - if (op1 & (1 << 24)) { - mask |=3D (0xffffULL << 48); - } - result ^=3D op2ex & mask; - op1 =3D (op1 >> 1) & 0x7f7f7f7f; - op2ex <<=3D 1; - } - return result; -} - #define NEON_FN(dest, src1, src2) dest =3D (src1 & src2) ? -1 : 0 NEON_VOP(tst_u8, neon_u8, 4) NEON_VOP(tst_u16, neon_u16, 2) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 03ce879497d..596bf4cf734 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10542,10 +10542,6 @@ static void handle_3rd_widening(DisasContext *s, i= nt is_q, int is_u, int size, gen_helper_neon_addl_saturate_s32(tcg_passres, cpu_env, tcg_passres, tcg_passres= ); break; - case 14: /* PMULL */ - assert(size =3D=3D 0); - gen_helper_neon_mull_p8(tcg_passres, tcg_op1, tcg_op2); - break; default: g_assert_not_reached(); } @@ -10709,11 +10705,21 @@ static void disas_simd_three_reg_diff(DisasContex= t *s, uint32_t insn) handle_3rd_narrowing(s, is_q, is_u, size, opcode, rd, rn, rm); break; case 14: /* PMULL, PMULL2 */ - if (is_u || size =3D=3D 1 || size =3D=3D 2) { + if (is_u) { unallocated_encoding(s); return; } - if (size =3D=3D 3) { + switch (size) { + case 0: /* PMULL.P8 */ + if (!fp_access_check(s)) { + return; + } + /* The Q field specifies lo/hi half input for this insn. */ + gen_gvec_op3_ool(s, true, rd, rn, rm, is_q, + gen_helper_neon_pmull_h); + break; + + case 3: /* PMULL.P64 */ if (!dc_isar_feature(aa64_pmull, s)) { unallocated_encoding(s); return; @@ -10724,9 +10730,13 @@ static void disas_simd_three_reg_diff(DisasContext= *s, uint32_t insn) /* The Q field specifies lo/hi half input for this insn. */ gen_gvec_op3_ool(s, true, rd, rn, rm, is_q, gen_helper_gvec_pmull_q); - return; + break; + + default: + unallocated_encoding(s); + break; } - goto is_widening; + return; case 9: /* SQDMLAL, SQDMLAL2 */ case 11: /* SQDMLSL, SQDMLSL2 */ case 13: /* SQDMULL, SQDMULL2 */ @@ -10747,7 +10757,6 @@ static void disas_simd_three_reg_diff(DisasContext = *s, uint32_t insn) unallocated_encoding(s); return; } - is_widening: if (!fp_access_check(s)) { return; } diff --git a/target/arm/translate.c b/target/arm/translate.c index 57d61c4aa57..ea6e984da65 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5866,15 +5866,20 @@ static int disas_neon_data_insn(DisasContext *s, ui= nt32_t insn) return 1; } =20 - /* Handle VMULL.P64 (Polynomial 64x64 to 128 bit multiply) - * outside the loop below as it only performs a single pas= s. - */ - if (op =3D=3D 14 && size =3D=3D 2) { - if (!dc_isar_feature(aa32_pmull, s)) { - return 1; + /* Handle polynomial VMULL in a single pass. */ + if (op =3D=3D 14) { + if (size =3D=3D 0) { + /* VMULL.P8 */ + tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, 16, 16, + 0, gen_helper_neon_pmull_h); + } else { + /* VMULL.P64 */ + if (!dc_isar_feature(aa32_pmull, s)) { + return 1; + } + tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, 16, 16, + 0, gen_helper_gvec_pmull_q); } - tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, 16, 16, - 0, gen_helper_gvec_pmull_q); return 0; } =20 @@ -5952,11 +5957,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) /* VMLAL, VQDMLAL, VMLSL, VQDMLSL, VMULL, VQDMULL = */ gen_neon_mull(cpu_V0, tmp, tmp2, size, u); break; - case 14: /* Polynomial VMULL */ - gen_helper_neon_mull_p8(cpu_V0, tmp, tmp2); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp); - break; default: /* 15 is RESERVED: caught earlier */ abort(); } diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 79d2624f7b1..8017bd88c4c 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -1197,3 +1197,63 @@ void HELPER(gvec_pmull_q)(void *vd, void *vn, void *= vm, uint32_t desc) } clear_tail(d, opr_sz, simd_maxsz(desc)); } + +/* + * 8x8->16 polynomial multiply. + * + * The byte inputs are expanded to (or extracted from) half-words. + * Note that neon and sve2 get the inputs from different positions. + * This allows 4 bytes to be processed in parallel with uint64_t. + */ + +static uint64_t expand_byte_to_half(uint64_t x) +{ + return (x & 0x000000ff) + | ((x & 0x0000ff00) << 8) + | ((x & 0x00ff0000) << 16) + | ((x & 0xff000000) << 24); +} + +static uint64_t pmull_h(uint64_t op1, uint64_t op2) +{ + uint64_t result =3D 0; + int i; + + for (i =3D 0; i < 8; ++i) { + uint64_t mask =3D (op1 & 0x0001000100010001ull) * 0xffff; + result ^=3D op2 & mask; + op1 >>=3D 1; + op2 <<=3D 1; + } + return result; +} + +void HELPER(neon_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc) +{ + int hi =3D simd_data(desc); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + uint64_t nn =3D n[hi], mm =3D m[hi]; + + d[0] =3D pmull_h(expand_byte_to_half(nn), expand_byte_to_half(mm)); + nn >>=3D 32; + mm >>=3D 32; + d[1] =3D pmull_h(expand_byte_to_half(nn), expand_byte_to_half(mm)); + + clear_tail(d, 16, simd_maxsz(desc)); +} + +#ifdef TARGET_AARCH64 +void HELPER(sve2_pmull_h)(void *vd, void *vn, void *vm, uint32_t desc) +{ + int shift =3D simd_data(desc) * 8; + intptr_t i, opr_sz =3D simd_oprsz(desc); + uint64_t *d =3D vd, *n =3D vn, *m =3D vm; + + for (i =3D 0; i < opr_sz / 8; ++i) { + uint64_t nn =3D (n[i] >> shift) & 0x00ff00ff00ff00ffull; + uint64_t mm =3D (m[i] >> shift) & 0x00ff00ff00ff00ffull; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=xSiTZ3bbGCGd/uM9CAsKu9wKQwmjm99/Hgqy9CM1+t4=; b=sece08w/bOhVfcwMb3/YlVpUDibrQtTEizvqPiiDMaUO1UlQ0dzdCalD7ia4F/d+GR daaD/7FvqHJyQ704yQwPEuwcY27faVOKtxzSwbkcVaXP5W6uh4niGiErRWMwnBID5jJJ OZqyo0xkRIL1VJy6+7NgtuhXbbpH9UJlMeg6FCPIjUiP0W0+LDbIAKj0FPwtH13zvoBg c3tfmMiXybj7vIBAhCQg5gAutxVHrUQcKbWdcxMARn3QFIk1rEWWIFQj1Rg3pheercTT 09vAjRzW/k3j8z53fmSH3FWJOBZrK3GsOu6xliRIPX3xulpezohBsilitV6hZ5Z5Zodv WBeQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xSiTZ3bbGCGd/uM9CAsKu9wKQwmjm99/Hgqy9CM1+t4=; b=qEHTZEviocLOcvifWtBqUjpJ946MqdTBwAtOjgfhTus44EDW3eYA2ruO99BBFMq3+0 Ch+JnwQMHlIRA8HZIxnBFDM49GO080m/DeGKQaliZlLg+tosgi42nR5VlkCafHwOoVas 39SaXTD7CH7M6g9sNIfVvIZzxit5lTQ52r+Tj0uJ/diHmv6ei0TrmCNJGtMDXzWNvtyM gxkvxHEbQAuOD3Msbj/HzYZLgQosSx1DLyCeDSy6/mwb6nAQt+B/SrD+eSrCTbh0v/Nm 3xqsCdPgpEVTNoRfPHTQnUM5ZooJEiNQn3pk/5NSXVWXxNPXwiX6AXDvOLzvBq9Fl9qH DZSg== X-Gm-Message-State: APjAAAUHKMLK7pp7TCKpsnKbpTk83hJvnCvNr6xLFL7LSA6dUx8WpeDP VrphToUDFGlPQ49GomAGwbs0T+91QL0iyg== X-Google-Smtp-Source: APXvYqw2tMfTk1f5N4RvatMFZ4VgSrxGSPD1F0FNqzRRLgOsT2j4E/w+ppMtZ3ymsAlnyYusvN98ZQ== X-Received: by 2002:adf:b605:: with SMTP id f5mr46479361wre.383.1582290514004; Fri, 21 Feb 2020 05:08:34 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 42/52] xilinx_spips: Correct the number of dummy cycles for the FAST_READ_4 cmd Date: Fri, 21 Feb 2020 13:07:30 +0000 Message-Id: <20200221130740.7583-43-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42e X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Francisco Iglesias Correct the number of dummy cycles required by the FAST_READ_4 command (to be eight, one dummy byte). Fixes: ef06ca3946 ("xilinx_spips: Add support for RX discard and RX drain") Suggested-by: C=C3=A9dric Le Goater Signed-off-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Message-id: 20200218113350.6090-1-frasse.iglesias@gmail.com Signed-off-by: Peter Maydell --- hw/ssi/xilinx_spips.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 6c9ef597796..c57850a5051 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -576,11 +576,11 @@ static int xilinx_spips_num_dummies(XilinxQSPIPS *qs,= uint8_t command) case FAST_READ: case DOR: case QOR: + case FAST_READ_4: case DOR_4: case QOR_4: return 1; case DIOR: - case FAST_READ_4: case DIOR_4: return 2; case QIOR: --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582291467; cv=none; d=zohomail.com; s=zohoarc; b=AAGlT3wCOSPdty5d0Sx5ZJVZFve0mkwmFNV0PDP3zn50NcXvbD4/+8d25mcgNQ8swIq28eXe9snofQO1+PvangRcGZBa/cKv87m+fTMeep6An4d64uoj+3dKFCEiooinEKi+hrN1LIB9IjZjF0bAW9UzfiYKIUNGWNA7fP8JjLs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582291467; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=O5FrGw//Kf20i1r0SXQ2jfWdoET0BPsu80ZZ6EIsSSg=; b=EgeUdOwd/3mpOQX2MIlO5DZR+qb5ac4Iq4TYsFxSpA5LipPoB2PfdKF/SxFopiwKjiDh6kvNWrokBfbvn6LyavWq9vvyc4/TKJlcorzSzZB5q8onsNZ/qQKVGYr2UGXubbrP7VX2sfk0UADg9eRIu0TxaWpmmmog50HBTn5LdHk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582291467582698.6128796007305; Fri, 21 Feb 2020 05:24:27 -0800 (PST) Received: from localhost ([::1]:57552 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58I6-00087f-2Q for importer@patchew.org; Fri, 21 Feb 2020 08:24:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57216) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582v-00007J-8l for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582t-00042w-TA for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:45 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:46943) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582t-00041B-MV for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:43 -0500 Received: by mail-wr1-x444.google.com with SMTP id z7so1970138wrl.13 for ; Fri, 21 Feb 2020 05:08:43 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=O5FrGw//Kf20i1r0SXQ2jfWdoET0BPsu80ZZ6EIsSSg=; b=kcE0vzAagzRnaipCDzWZc44m78pxWviB+VPBzHHLept3XhAsWpdidQC9jScO0SeYw5 m/g5/H4GmmrTqyoVSSc6/D5yodn+8VLOYgZ6nOCzGcjWpQdzAKSGT/2N8mAa/HJkTgY4 N0+9SdBG4El4OcqKzvI8cNw/oZp9ah0k9ARh6Cmy0UChnHga3wMFn+upgJikswD0enPr hPLJIhuSB0clNPb/MTWwYqFzl1pzQq+/pBT3DVzm6G2BWoPRV/bkHIOVqHuEp8/ms37w 93pktYqh61Be1E6mC2grTtZxqVhl7aox9n7ElVhEvRgLUPNuZFNpEVWA8qeTwYkEZXHQ cUog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O5FrGw//Kf20i1r0SXQ2jfWdoET0BPsu80ZZ6EIsSSg=; b=jmZXNDWt2eXZ7lqBn2/O/WwIGrG1rLAlaVUepkWRpbidOVuYZcQ7/qHWG4eLXjkIy8 h/roZcy08+JmwbaQeWGqd/3Bm8XqgNsI8Ms3gO4HqGhTW9xKz22R3WiyOAl3KfLaj4Sh 2eXmr211XtCjOqs5DdG3UeVGsY54330wCUybHxaeOz3aD2PAaUnHfo5boyKCj5lWbEvk 2r3jxyZh6IJO6Tk4npP3aztKendc7BNKEyvKWAwVAbpnms0TNN97cGbRnXViIMWTKJFK otlYGB4oQLj+L2o39Sx6/pyU/odBOo60vZt70lCDgslKq7E8X5Md0KWWdQfNWhIvxyjN bLmQ== X-Gm-Message-State: APjAAAVmCeBLT1DjWt6nTIr0XdvLZfMLJnZwCvToBDtTOCn4uV/rktJt fi+qWpOrEZsAZ3u6XBJdv5VROChZ0MIWVA== X-Google-Smtp-Source: APXvYqxp377UelAni/CcZYK8NQmbYfq7yaWa+qNzk8f6U8yyqvUoySkyklzB40dt6r0rQ/0LthZfsw== X-Received: by 2002:adf:f744:: with SMTP id z4mr43958210wrp.318.1582290515175; Fri, 21 Feb 2020 05:08:35 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 43/52] sh4: Fix PCI ISA IO memory subregion Date: Fri, 21 Feb 2020 13:07:31 +0000 Message-Id: <20200221130740.7583-44-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Guenter Roeck Booting the r2d machine from flash fails because flash is not discovered. Looking at the flattened memory tree, we see the following. FlatView #1 AS "memory", root: system AS "cpu-memory-0", root: system AS "sh_pci_host", root: bus master container Root memory region: system 0000000000000000-000000000000ffff (prio 0, i/o): io 0000000000010000-0000000000ffffff (prio 0, i/o): r2d.flash @0000000000010= 000 The overlapping memory region is sh_pci.isa, ie the ISA I/O region bridge. This region is initially assigned to address 0xfe240000, but overwritten with a write into the PCIIOBR register. This write is expected to adjust the PCI memory window, but not to change the region's base adddress. Peter Maydell provided the following detailed explanation. "Section 22.3.7 and in particular figure 22.3 (of "SSH7751R user's manual: hardware") are clear about how this is supposed to work: there is a window at 0xfe240000 in the system register space for PCI I/O space. When the CPU makes an access into that area, the PCI controller calculates the PCI address to use by combining bits 0..17 of the system address with the bits 31..18 value that the guest has put into the PCIIOBR. That is, writing to the PCIIOBR changes which section of the IO address space is visible in the 0xfe240000 window. Instead what QEMU's implementation does is move the window to whatever value the guest writes to the PCIIOBR register -- so if the guest writes 0 we put the window at 0 in system address space." Fix the problem by calling memory_region_set_alias_offset() instead of removing and re-adding the PCI ISA subregion on writes into PCIIOBR. At the same time, in sh_pci_device_realize(), don't set iobr since it is overwritten later anyway. Instead, pass the base address to memory_region_add_subregion() directly. Many thanks to Peter Maydell for the detailed problem analysis, and for providing suggestions on how to fix the problem. Signed-off-by: Guenter Roeck Message-id: 20200218201050.15273-1-linux@roeck-us.net Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/sh4/sh_pci.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/hw/sh4/sh_pci.c b/hw/sh4/sh_pci.c index 71afd23b679..08f2fc1ddee 100644 --- a/hw/sh4/sh_pci.c +++ b/hw/sh4/sh_pci.c @@ -67,12 +67,8 @@ static void sh_pci_reg_write (void *p, hwaddr addr, uint= 64_t val, pcic->mbr =3D val & 0xff000001; break; case 0x1c8: - if ((val & 0xfffc0000) !=3D (pcic->iobr & 0xfffc0000)) { - memory_region_del_subregion(get_system_memory(), &pcic->isa); - pcic->iobr =3D val & 0xfffc0001; - memory_region_add_subregion(get_system_memory(), - pcic->iobr & 0xfffc0000, &pcic->is= a); - } + pcic->iobr =3D val & 0xfffc0001; + memory_region_set_alias_offset(&pcic->isa, val & 0xfffc0000); break; case 0x220: pci_data_write(phb->bus, pcic->par, val, 4); @@ -147,8 +143,7 @@ static void sh_pci_device_realize(DeviceState *dev, Err= or **errp) get_system_io(), 0, 0x40000); sysbus_init_mmio(sbd, &s->memconfig_p4); sysbus_init_mmio(sbd, &s->memconfig_a7); - s->iobr =3D 0xfe240000; - memory_region_add_subregion(get_system_memory(), s->iobr, &s->isa); + memory_region_add_subregion(get_system_memory(), 0xfe240000, &s->isa); =20 s->dev =3D pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "sh_pci_host"); } --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582292492; cv=none; d=zohomail.com; s=zohoarc; b=J2Zl8CP4X9xe07Q55iCxrWE4vbbFLCyLutPGFtV0gvlHsDyWHSF2yWat8+tUWaz/R2ZlrNsdlnc88Qqfzf4Wm8qCsqSUa3uvwTznVCZleKYfzcvyvJgLEw/LCeVBflaKL8OpZJVm4GOiN7p0PxDPHXbeAQI/KzmQquXE+7bpH+o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582292492; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Z1Y6b6ExQtNuRQRhurbCAkV6WfKuu4Z4DVqSKk6+08k=; b=LOit6wbNUFGIOHG+/vITh61LKuwzhxpFhnPUdF4pCLF4Rw5RC9sqEzWlnqArsH0FaovCO1ggtc74GS6KT5l6Js/ejFaMW/LBNRuZUyzfm4MPGLa6ykGCeCsQ+N9foKO8OcBSqeV1Lthc8cH143gBRMQ/G3cmjlnEZALa0MdECao= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582292492527841.3417142263075; Fri, 21 Feb 2020 05:41:32 -0800 (PST) Received: from localhost ([::1]:58030 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58Yd-0001hL-EN for importer@patchew.org; Fri, 21 Feb 2020 08:41:31 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57139) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582q-0008OH-4D for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582o-0003tj-Bq for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:40 -0500 Received: from mail-wr1-x444.google.com ([2a00:1450:4864:20::444]:43580) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582o-0003t4-3f for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:38 -0500 Received: by mail-wr1-x444.google.com with SMTP id r11so1988611wrq.10 for ; Fri, 21 Feb 2020 05:08:38 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Z1Y6b6ExQtNuRQRhurbCAkV6WfKuu4Z4DVqSKk6+08k=; b=HOPTAA/2/eQsX1TqGrNXo8mE1ZdMUm55Ah4PNrs2x4Y0Una1aWJgohlOFXljy/SF3l FL+CBmmlQAQcVb33KeTh95dxGkBUiDOvx+G6nSFmQ+n2Shm52Cun/dOPuVslv/Bnozvm RDEUTLm4IzmjaHlElQbWOrmcGJ+fu5/uHZxxj3lMYRxKEYy0OQqJxYjDG/6n0HXDpy3v CD1yi4hxOEzOQmhcTw/xPdGhdsUT8IjF1asERxmlSrEcVDrF6NWBdmx+dVhm4jkTbFNE fWsp9U0sX8CiDP+hr0DEcz+0BBnoCDYkLUL9A2H5sUC4nqWIElLesTVF6y04b0jw8kyg k/5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z1Y6b6ExQtNuRQRhurbCAkV6WfKuu4Z4DVqSKk6+08k=; b=dT1Ae6al6aKOXyuJXFwdyoV4uUoi0uEN/vFLPeXjrmIA+UdSTMdJJwogv+S0zm6dK4 AvTJ+K6y1e5ah6Z47RLFK8Jv9eTEBH2d+CYLm5mweypJ7xtM0BrSuIcQzz9jWC6lgkxc socyQqS5X/a8CXrt2vP5X5xHHL3dv8hhHDs4FDXdZ0T/spsoJpghM5k48+vOX+EQRFtQ dR0qBmDJU5S4+em8TzXMDxyh4TN4WcI24NOdTMcK0hZSMVSRFNVhIH0q2w4bBR71B2q4 +nvaM/Ym6GSheZCgSo/pjRGyBIgrbDOxCQFAL9A+n6Jx6Wh1TJKqoEl/2ovgCBulemCd 8YCg== X-Gm-Message-State: APjAAAW1u/EAzMo1wlZbRuFHRZsYBrNGnqv7FnHcdJE1d5zO/8z3B/zs Mk6z85IutBf+6mu9JLBd6lWs6sByPxrGfQ== X-Google-Smtp-Source: APXvYqx+ofTxlaKn9fC4etbJmcI02I+tPfuG+gcXA11tmEEs6l//7MIiAjh+gF4haqL2V2ZrRq9Abg== X-Received: by 2002:adf:a1d9:: with SMTP id v25mr47786645wrv.160.1582290516502; Fri, 21 Feb 2020 05:08:36 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 44/52] target/arm: Rename isar_feature_aa32_simd_r32 Date: Fri, 21 Feb 2020 13:07:32 +0000 Message-Id: <20200221130740.7583-45-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson The old name, isar_feature_aa32_fp_d32, does not reflect the MVFR0 field name, SIMDReg. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200214181547.21408-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell [PMM: wrapped one long line] Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 +- target/arm/translate-vfp.inc.c | 53 +++++++++++++++++----------------- 2 files changed, 28 insertions(+), 27 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b4c83a1cb52..65171cb30ee 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3450,7 +3450,7 @@ static inline bool isar_feature_aa32_fp16_arith(const= ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) =3D=3D 1; } =20 -static inline bool isar_feature_aa32_fp_d32(const ARMISARegisters *id) +static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) { /* Return true if D16-D31 are implemented */ return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) >=3D 2; diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index bf90ac0e5b7..ba46e2557a1 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -201,7 +201,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_fp_d32, s) && + if (dp && !dc_isar_feature(aa32_simd_r32, s) && ((a->vm | a->vn | a->vd) & 0x10)) { return false; } @@ -334,7 +334,7 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMA= XNM *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_fp_d32, s) && + if (dp && !dc_isar_feature(aa32_simd_r32, s) && ((a->vm | a->vn | a->vd) & 0x10)) { return false; } @@ -420,7 +420,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_fp_d32, s) && + if (dp && !dc_isar_feature(aa32_simd_r32, s) && ((a->vm | a->vd) & 0x10)) { return false; } @@ -484,7 +484,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { + if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 @@ -556,7 +556,7 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV_= to_gp *a) uint32_t offset; =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { return false; } =20 @@ -615,7 +615,7 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VMO= V_from_gp *a) uint32_t offset; =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { return false; } =20 @@ -662,7 +662,7 @@ static bool trans_VDUP(DisasContext *s, arg_VDUP *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vn & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { return false; } =20 @@ -912,7 +912,7 @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV_= 64_dp *a) */ =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 @@ -978,7 +978,7 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_VLD= R_VSTR_dp *a) TCGv_i64 tmp; =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; } =20 @@ -1101,7 +1101,7 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_V= LDM_VSTM_dp *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd + n) > 16) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd + n) > 16) { return false; } =20 @@ -1309,7 +1309,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpD= PFn *fn, TCGv_ptr fpst; =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_fp_d32, s) && ((vd | vn | vm) & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) { return false; } =20 @@ -1458,7 +1458,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpD= PFn *fn, int vd, int vm) TCGv_i64 f0, fd; =20 /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_fp_d32, s) && ((vd | vm) & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) { return false; } =20 @@ -1822,7 +1822,8 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp = *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vn | a->vm) & 0x1= 0)) { + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { return false; } =20 @@ -1921,7 +1922,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VM= OV_imm_dp *a) vd =3D a->vd; =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && (vd & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) { return false; } =20 @@ -2065,7 +2066,7 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_d= p *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { return false; } =20 @@ -2138,7 +2139,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_V= CVT_f64_f16 *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; } =20 @@ -2204,7 +2205,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_V= CVT_f16_f64 *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 @@ -2264,7 +2265,7 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRIN= TR_dp *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { return false; } =20 @@ -2325,7 +2326,7 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRIN= TZ_dp *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { return false; } =20 @@ -2384,7 +2385,7 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRIN= TX_dp *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && ((a->vd | a->vm) & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && ((a->vd | a->vm) & 0x10)) { return false; } =20 @@ -2412,7 +2413,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_s= p *a) TCGv_i32 vm; =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; } =20 @@ -2440,7 +2441,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_d= p *a) TCGv_i32 vd; =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 @@ -2494,7 +2495,7 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VC= VT_int_dp *a) TCGv_ptr fpst; =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; } =20 @@ -2534,7 +2535,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 @@ -2627,7 +2628,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VC= VT_fix_dp *a) } =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vd & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; } =20 @@ -2723,7 +2724,7 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VC= VT_dp_int *a) TCGv_ptr fpst; =20 /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) { + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=lZW5fWoykryTlZydn2qsBAZbMdQAuH2IlE0NMzkYoxo=; b=UPhK4mvbVdgdJyzUg4GXrcs2LpeYxYqRHQKCInWWnAze3CJJxS694x7smWL6HvKypD xTQ8p1OrOv8lTHSN7i5/v1uFoWP6SKFbdjyFfP4zfL/e5m2hAuLRIuK62uQLrj3Cqj9Q TeTfQ3xjNKDdxR/4I/AL9LcDTZfNgf3tx8lb6GCx8CazZQfu6+Ajz2jQNbvEGmxxSQp+ 4xaElV5ip6C7mp8mFgWR4HAXnzOIiqzTfdAvbI0fLP+00blisEl6HPfWGAJQKAflYD53 V5RPGgDGziF729e7nP0TX7rUtpzslW8mmzjehnKpe0401cGq74RXs66Q9LIG2AYFXnYy MnIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lZW5fWoykryTlZydn2qsBAZbMdQAuH2IlE0NMzkYoxo=; b=rBcK6jFlrbcdykCdV1Mav7p6Ad7ctfYfy6N0tbXgTJWImMPuq61qfm7k1oVvo1isee ot0XiXQeJ0LdYxjarWrDuI+av3URtqAyAlxzWYjLI+ZJYoBW4r3kt/QeWSVmVEFQKswS 62zdabYmUkVeYFC+z/cgn6Fo+zcIit/YbG0od6r67c65AoVaTDhlpsk5s6CVrZSQu09Q jkmD+ND4u12D3j3F4ZAIYAmqDFfn+Ejl3ZCOv1XVsWiwNBHPNexZH8Qo1cnmShV0uwPa 6teZ5T/YVoMYfZydx+pAAjkgFOS3ZLKBHdY61ZK0V6A4f96D8aLmK1GqpD/Vwzl5KmNg NHlg== X-Gm-Message-State: APjAAAW6PG9xlrx8PF/ZeZ1I5yYgy1Feh3EVXCH1esg2iw6ll3MD+bnh 1aecDbaXzUC4M/ztaVm+GJFs2mjrwGolAg== X-Google-Smtp-Source: APXvYqxmY55aOoQB7Shl8XAQLuabCU3devn0W6wItchx7L5yRzXuUq8cRWUC0xeBPupd0NX3TmAxKQ== X-Received: by 2002:a1c:9849:: with SMTP id a70mr3722500wme.76.1582290517687; Fri, 21 Feb 2020 05:08:37 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 45/52] target/arm: Use isar_feature_aa32_simd_r32 more places Date: Fri, 21 Feb 2020 13:07:33 +0000 Message-Id: <20200221130740.7583-46-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Many uses of ARM_FEATURE_VFP3 are testing for the number of simd registers implemented. Use the proper test vs MVFR0.SIMDReg. Signed-off-by: Richard Henderson Message-id: 20200214181547.21408-4-richard.henderson@linaro.org [PMM: fix typo in commit message] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.c | 9 ++++----- target/arm/helper.c | 13 ++++++------- target/arm/translate.c | 2 +- 3 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9f618e120aa..8085268a539 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1009,11 +1009,10 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *= f, int flags) =20 if (flags & CPU_DUMP_FPU) { int numvfpregs =3D 0; - if (arm_feature(env, ARM_FEATURE_VFP)) { - numvfpregs +=3D 16; - } - if (arm_feature(env, ARM_FEATURE_VFP3)) { - numvfpregs +=3D 16; + if (cpu_isar_feature(aa32_simd_r32, cpu)) { + numvfpregs =3D 32; + } else if (arm_feature(env, ARM_FEATURE_VFP)) { + numvfpregs =3D 16; } for (i =3D 0; i < numvfpregs; i++) { uint64_t v =3D *aa32_vfp_dreg(env, i); diff --git a/target/arm/helper.c b/target/arm/helper.c index 1ac09f387ed..79db169e046 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -50,10 +50,10 @@ static void switch_mode(CPUARMState *env, int mode); =20 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) { - int nregs; + ARMCPU *cpu =3D env_archcpu(env); + int nregs =3D cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; =20 /* VFP data registers are always little-endian. */ - nregs =3D arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; if (reg < nregs) { stq_le_p(buf, *aa32_vfp_dreg(env, reg)); return 8; @@ -78,9 +78,9 @@ static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf= , int reg) =20 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) { - int nregs; + ARMCPU *cpu =3D env_archcpu(env); + int nregs =3D cpu_isar_feature(aa32_simd_r32, cpu) ? 32 : 16; =20 - nregs =3D arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; if (reg < nregs) { *aa32_vfp_dreg(env, reg) =3D ldq_le_p(buf); return 8; @@ -906,8 +906,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, /* VFPv3 and upwards with NEON implement 32 double precision * registers (D0-D31). */ - if (!arm_feature(env, ARM_FEATURE_NEON) || - !arm_feature(env, ARM_FEATURE_VFP3)) { + if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) { /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ value |=3D (1 << 30); } @@ -7812,7 +7811,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) } else if (arm_feature(env, ARM_FEATURE_NEON)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 51, "arm-neon.xml", 0); - } else if (arm_feature(env, ARM_FEATURE_VFP3)) { + } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 35, "arm-vfp3.xml", 0); } else if (arm_feature(env, ARM_FEATURE_VFP)) { diff --git a/target/arm/translate.c b/target/arm/translate.c index ea6e984da65..79880adaad2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -2612,7 +2612,7 @@ static int disas_dsp_insn(DisasContext *s, uint32_t i= nsn) #define VFP_SREG(insn, bigbit, smallbit) \ ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1)) #define VFP_DREG(reg, insn, bigbit, smallbit) do { \ - if (arm_dc_feature(s, ARM_FEATURE_VFP3)) { \ + if (dc_isar_feature(aa32_simd_r32, s)) { \ reg =3D (((insn) >> (bigbit)) & 0x0f) \ | (((insn) >> ((smallbit) - 4)) & 0x10); \ } else { \ --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582292100; cv=none; d=zohomail.com; s=zohoarc; b=I1wEOo1a4eRc6JMqUvEYiV95rA28mTMJmacJWmM34sP3CKiRga0cVERywZ1z0T8nSZW9Z2gGG6twWUOUO712q8FxMcag/vSItJyNLbLNnwEHnX6AGYJKhzCQlUiC3vOV71nZ1vzRrCZCDcbgIOWVdSFbhS6KDgLtrws2F9QAvFk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582292100; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qNihTLJediBrpCJBoB3GKxR0uHRMJ0laKIeFV/sWBeE=; b=edxHS0k0eqI947foPN3JzTgoQ01lFcU/HH7oEVwSzFDNoxe17f0uHZZ5OsIzfIW5ZkOp/c9hi3Sez05KBPMMEy1raYM3SKkBTj9Eqr++GMqvMQM/8e5nPYK4v2Q0x4RJvXLRBpkfvFjD+LIR+S5es8OjMxaXcoBAvnTM5J3Vr4w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582292100113502.184782181841; Fri, 21 Feb 2020 05:35:00 -0800 (PST) Received: from localhost ([::1]:57840 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58SI-0006Gq-3j for importer@patchew.org; Fri, 21 Feb 2020 08:34:58 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57160) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582s-0008RX-Fw for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582q-0003vt-9K for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:42 -0500 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:36716) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582q-0003uq-1q for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:40 -0500 Received: by mail-wm1-x335.google.com with SMTP id p17so1779882wma.1 for ; Fri, 21 Feb 2020 05:08:39 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qNihTLJediBrpCJBoB3GKxR0uHRMJ0laKIeFV/sWBeE=; b=MQNFbY16pR61Fbjdgajdp8bn+FGLccb/PkMZWosIdY4SAadvddq0jIdAPHDKdDy+Ql v7Gtlem7iRujBC/wKzSY28U7cYtJ7CbLldih9Zdp1piKVtnLoGO75YbzHoT/CDC5UEbc 0d/oJRFrbKGAxk6E5k9LEOzx5ak8pv5NAZl+/9AxRZJ0c1rma2VUWin2qU/tXrdECyWF QPJYErNG97d4Og9fRDEdIiMgCj2nYOEwAMjuEvncDQU+a7PdunvlGQGrmQEoFegO6BG9 csZkDAl/9w8pnPAh/drWm/0ebXF2SeHQSqFSlFm8OTuqCdsQmgq+dwBOkIyCmFIFVKvF 0Lkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qNihTLJediBrpCJBoB3GKxR0uHRMJ0laKIeFV/sWBeE=; b=FbzFj8ZvdyDCRIbPrzExBs6+vSFNxZt057YIFHWNmgTpKX9gCOXtef+pYzIM5OSBOd WXaVcbQWeHR4cfcKqrBjIwHhqeN00uGIbs191ZDlFUKc7exjYeHLTOWNxDGk2tHCRmAC OK8ZFWqa1VJXlt4zPJhuME6ndsSfY9f03zX+1mcJKGOHBY5PFmh0j5GXz+Mq1AyMv8+B KCMz0IlDZLLfSA9qLcoljKlGVYOcn0Q9taLOd+mmhgy4I6wT/zMEIzyPQay3ptcFy9mB S4uA5TAgCJzXqUEtrULRho+GPjGZYjOqL/lUtX5H0u3AWCHgk63IsJKqg/o+s5GjjY6Q msVw== X-Gm-Message-State: APjAAAUBdOsKmHiDgG4HCmF6jtqHldNm11GinNBTjDSkOCXUlIW9m3ef 7bv24z80F+J1Aq2HbZU/7PrGx9dpkdAWGA== X-Google-Smtp-Source: APXvYqx5egBCnPoTjWD6En80pTQKzB770C5vu20n5DldSuDJ7IhqZB7tabP5lZR0LhOmETT2K4Y1EQ== X-Received: by 2002:a1c:2093:: with SMTP id g141mr3778986wmg.142.1582290518683; Fri, 21 Feb 2020 05:08:38 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 46/52] target/arm: Set MVFR0.FPSP for ARMv5 cpus Date: Fri, 21 Feb 2020 13:07:34 +0000 Message-Id: <20200221130740.7583-47-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::335 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We are going to convert FEATURE tests to ISAR tests, so FPSP needs to be set for these cpus, like we have already for FPDP. Signed-off-by: Richard Henderson Message-id: 20200214181547.21408-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 8085268a539..2eadf4dcb8b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1872,10 +1872,11 @@ static void arm926_initfn(Object *obj) */ cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); /* - * Similarly, we need to set MVFR0 fields to enable double precision - * and short vector support even though ARMv5 doesn't have this regist= er. + * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or + * support even though ARMv5 doesn't have this register. */ cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); } =20 @@ -1914,10 +1915,11 @@ static void arm1026_initfn(Object *obj) */ cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); /* - * Similarly, we need to set MVFR0 fields to enable double precision - * and short vector support even though ARMv5 doesn't have this regist= er. + * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or + * support even though ARMv5 doesn't have this register. */ cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); =20 { --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582292205; cv=none; d=zohomail.com; s=zohoarc; b=Qz3zylN5CkqEpwWCign5dbVvzHGgpGiL5thnzD6SQRMyNHt9EutUCutVvL5BH/YUkOi05qJKOj2c+wzaQc5zdvd4DfigyK+/hBjm8lF2hOFQz3hpLMpVvrt/Uwfom+L0bxfhis0LUcwePJrKqOnj0YUo3oyjPnayxK4XGPTs+8c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582292205; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XOZCmV/LRRvs4SHMu0PR/HJGYRQoHyJpDUcGa+N8A1M=; b=mFxQ6T1gI0ez8rg6uvINlr3x4rYubBNBVFrzd9aNmL7I5MNYYUY+quMMPKLHcy52oeGjdGqjxAu5twnHbzbO4ua55o8enj4VrI+s/PRInWP6ayU+W3aKNy74BJraHN5qZ8k5j63KFVVzfe6YMbRZ0DmbUyeW2xPCCF6ZjqnYhoc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582292205276782.2927501574464; Fri, 21 Feb 2020 05:36:45 -0800 (PST) Received: from localhost ([::1]:57902 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58U0-0001Ma-39 for importer@patchew.org; Fri, 21 Feb 2020 08:36:44 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57210) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582u-00006a-W1 for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582s-0003zq-Rs for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:44 -0500 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:50647) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582s-0003xG-Jp for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:42 -0500 Received: by mail-wm1-x32b.google.com with SMTP id a5so1737089wmb.0 for ; Fri, 21 Feb 2020 05:08:42 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XOZCmV/LRRvs4SHMu0PR/HJGYRQoHyJpDUcGa+N8A1M=; b=isA+TSRJrhE5N3Gn0g1afjqJK1oVlwqvlAvqwOje/33xFzxM7ffnwMLivtkYUglIHH g29jhUnUqsxSsM39tBfE90jyhWj/WlpIMzrZKl5f3g3EnAWt9Xj/a9xp+KGsM7hFzIpx FQPJ1EV1iz0pcJkSPisRLkI/UgK7knwhnlOX1DiRPLXN9ggkYOBOvuQeGORdOvYyREKv 2qu/+yAd3BeMp7VwmRxSin2wIzpqNei+y6dW1Rn098tDMmu41rpHVqXrgmv3L8EiiBXE SS4CTmFbUpu9894Zhi5aFD/6AwNyxfgulP8e/hSea0eevLFc5qHhKaRV/39eaeu2A12I wWdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XOZCmV/LRRvs4SHMu0PR/HJGYRQoHyJpDUcGa+N8A1M=; b=eU0/OwnWEspL0ZMVZKkYPUFeUhYDGKhF0oikfICRhOUUuxpiuukxENe0ObVSz+M9D1 Wbc8KHqj6p019m5y58xJU1hlVuEvC3xno9ZQK2QojmOPd9Tf6xDHL2vcRUX8UFVNNEsG 93tmTsqVq6kypGSoxgJCCnrz5w2pxtVcCs+RjJDRWtF6690LHFPyf7/axPQWCoQV7WWN KT8ex5X/mSogZd3jtv6CcFDmGi+qmtXAxossYOO0oN0rRZiDJr6Oi1PgyCTLm9Z89RaF EpV0A1ff/QGA2a3m2gEwXDqJ6d+rc0tC62Cp88qEPVAA5hVmRQPhlEXMZzwpYnPeaaTq ASww== X-Gm-Message-State: APjAAAVjOOEbq8EopgGNH+usk/pixY/uFjnG3ZYJ1rlA2WslmjecR/H7 dyDnZoJq5lg4JlOURo28ErMUKVY+2QuDmQ== X-Google-Smtp-Source: APXvYqx9kRK75/VCGAm/UsL8eY4aF860uIm5SFFKgnRzwFcESiyzGluw7BPNpDLCPuiIufDVJE+M6g== X-Received: by 2002:a1c:2089:: with SMTP id g131mr3621569wmg.63.1582290519919; Fri, 21 Feb 2020 05:08:39 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 47/52] target/arm: Add isar_feature_aa32_simd_r16 Date: Fri, 21 Feb 2020 13:07:35 +0000 Message-Id: <20200221130740.7583-48-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32b X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use this in the places that were checking ARM_FEATURE_VFP, and are obviously testing for the existance of the register set as opposed to testing for some particular instruction extension. Signed-off-by: Richard Henderson Message-id: 20200214181547.21408-6-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 6 ++++++ hw/intc/armv7m_nvic.c | 20 ++++++++++---------- linux-user/arm/signal.c | 4 ++-- target/arm/arch_dump.c | 11 ++++++----- target/arm/cpu.c | 8 ++++---- target/arm/helper.c | 4 ++-- target/arm/m_helper.c | 11 ++++++----- target/arm/machine.c | 3 +-- 8 files changed, 37 insertions(+), 30 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 65171cb30ee..5a62586dd29 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3450,6 +3450,12 @@ static inline bool isar_feature_aa32_fp16_arith(cons= t ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, FP) =3D=3D 1; } =20 +static inline bool isar_feature_aa32_simd_r16(const ARMISARegisters *id) +{ + /* Return true if D0-D15 are implemented */ + return FIELD_EX32(id->mvfr0, MVFR0, SIMDREG) > 0; +} + static inline bool isar_feature_aa32_simd_r32(const ARMISARegisters *id) { /* Return true if D16-D31 are implemented */ diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 22a43e49847..78cde4ed237 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1262,12 +1262,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) case 0xd84: /* CSSELR */ return cpu->env.v7m.csselr[attrs.secure]; case 0xd88: /* CPACR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_simd_r16, cpu)) { return 0; } return cpu->env.v7m.cpacr[attrs.secure]; case 0xd8c: /* NSACR */ - if (!attrs.secure || !arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!attrs.secure || !cpu_isar_feature(aa32_simd_r16, cpu)) { return 0; } return cpu->env.v7m.nsacr; @@ -1417,7 +1417,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t off= set, MemTxAttrs attrs) } return cpu->env.v7m.sfar; case 0xf34: /* FPCCR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_simd_r16, cpu)) { return 0; } if (attrs.secure) { @@ -1444,12 +1444,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t o= ffset, MemTxAttrs attrs) return value; } case 0xf38: /* FPCAR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_simd_r16, cpu)) { return 0; } return cpu->env.v7m.fpcar[attrs.secure]; case 0xf3c: /* FPDSCR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_simd_r16, cpu)) { return 0; } return cpu->env.v7m.fpdscr[attrs.secure]; @@ -1711,13 +1711,13 @@ static void nvic_writel(NVICState *s, uint32_t offs= et, uint32_t value, } break; case 0xd88: /* CPACR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, cpu)) { /* We implement only the Floating Point extension's CP10/CP11 = */ cpu->env.v7m.cpacr[attrs.secure] =3D value & (0xf << 20); } break; case 0xd8c: /* NSACR */ - if (attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (attrs.secure && cpu_isar_feature(aa32_simd_r16, cpu)) { /* We implement only the Floating Point extension's CP10/CP11 = */ cpu->env.v7m.nsacr =3D value & (3 << 10); } @@ -1951,7 +1951,7 @@ static void nvic_writel(NVICState *s, uint32_t offset= , uint32_t value, break; } case 0xf34: /* FPCCR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, cpu)) { /* Not all bits here are banked. */ uint32_t fpccr_s; =20 @@ -2005,13 +2005,13 @@ static void nvic_writel(NVICState *s, uint32_t offs= et, uint32_t value, } break; case 0xf38: /* FPCAR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, cpu)) { value &=3D ~7; cpu->env.v7m.fpcar[attrs.secure] =3D value; } break; case 0xf3c: /* FPDSCR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, cpu)) { value &=3D 0x07c00000; cpu->env.v7m.fpdscr[attrs.secure] =3D value; } diff --git a/linux-user/arm/signal.c b/linux-user/arm/signal.c index b0e753801b6..2871a7cc21d 100644 --- a/linux-user/arm/signal.c +++ b/linux-user/arm/signal.c @@ -346,7 +346,7 @@ static void setup_sigframe_v2(struct target_ucontext_v2= *uc, setup_sigcontext(&uc->tuc_mcontext, env, set->sig[0]); /* Save coprocessor signal frame. */ regspace =3D uc->tuc_regspace; - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, env_archcpu(env))) { regspace =3D setup_sigframe_v2_vfp(regspace, env); } if (arm_feature(env, ARM_FEATURE_IWMMXT)) { @@ -671,7 +671,7 @@ static int do_sigframe_return_v2(CPUARMState *env, =20 /* Restore coprocessor signal frame */ regspace =3D uc->tuc_regspace; - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, env_archcpu(env))) { regspace =3D restore_sigframe_v2_vfp(env, regspace); if (!regspace) { return 1; diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 2345dec3c2c..a5a4f4e1f8f 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -363,9 +363,11 @@ int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, = CPUState *cs, int cpuid, void *opaque) { struct arm_note note; - CPUARMState *env =3D &ARM_CPU(cs)->env; + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; DumpState *s =3D opaque; - int ret, i, fpvalid =3D !!arm_feature(env, ARM_FEATURE_VFP); + int ret, i; + bool fpvalid =3D cpu_isar_feature(aa32_simd_r16, cpu); =20 arm_note_init(¬e, s, "CORE", 5, NT_PRSTATUS, sizeof(note.prstatus)); =20 @@ -444,7 +446,6 @@ int cpu_get_dump_info(ArchDumpInfo *info, ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) { ARMCPU *cpu =3D ARM_CPU(first_cpu); - CPUARMState *env =3D &cpu->env; size_t note_size; =20 if (class =3D=3D ELFCLASS64) { @@ -452,12 +453,12 @@ ssize_t cpu_get_note_size(int class, int machine, int= nr_cpus) note_size +=3D AARCH64_PRFPREG_NOTE_SIZE; #ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_sve, cpu)) { - note_size +=3D AARCH64_SVE_NOTE_SIZE(env); + note_size +=3D AARCH64_SVE_NOTE_SIZE(&cpu->env); } #endif } else { note_size =3D ARM_PRSTATUS_NOTE_SIZE; - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, cpu)) { note_size +=3D ARM_VFP_NOTE_SIZE; } } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2eadf4dcb8b..d5a75c265ac 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -293,7 +293,7 @@ static void arm_cpu_reset(CPUState *s) env->v7m.ccr[M_REG_S] |=3D R_V7M_CCR_UNALIGN_TRP_MASK; } =20 - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, cpu)) { env->v7m.fpccr[M_REG_NS] =3D R_V7M_FPCCR_ASPEN_MASK; env->v7m.fpccr[M_REG_S] =3D R_V7M_FPCCR_ASPEN_MASK | R_V7M_FPCCR_LSPEN_MASK | R_V7M_FPCCR_S_MASK; @@ -1011,7 +1011,7 @@ static void arm_cpu_dump_state(CPUState *cs, FILE *f,= int flags) int numvfpregs =3D 0; if (cpu_isar_feature(aa32_simd_r32, cpu)) { numvfpregs =3D 32; - } else if (arm_feature(env, ARM_FEATURE_VFP)) { + } else if (cpu_isar_feature(aa32_simd_r16, cpu)) { numvfpregs =3D 16; } for (i =3D 0; i < numvfpregs; i++) { @@ -1260,7 +1260,7 @@ void arm_cpu_post_init(Object *obj) * KVM does not currently allow us to lie to the guest about its * ID/feature registers, so the guest always sees what the host has. */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, cpu)) { cpu->has_vfp =3D true; if (!kvm_enabled()) { qdev_property_add_static(DEVICE(obj), &arm_cpu_has_vfp_propert= y); @@ -1636,7 +1636,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * We rely on no XScale CPU having VFP so we can use the same bits in = the * TB flags field for VECSTRIDE and XSCALE_CPAR. */ - assert(!(arm_feature(env, ARM_FEATURE_VFP) && + assert(!(cpu_isar_feature(aa32_simd_r16, cpu) && arm_feature(env, ARM_FEATURE_XSCALE))); =20 if (arm_feature(env, ARM_FEATURE_V7) && diff --git a/target/arm/helper.c b/target/arm/helper.c index 79db169e046..402f9ffab9b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -894,7 +894,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, * ASEDIS [31] and D32DIS [30] are both UNK/SBZP without VFP. * TRCDIS [28] is RAZ/WI since we do not implement a trace macroce= ll. */ - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, env_archcpu(env))) { /* VFP coprocessor: cp10 & cp11 [23:20] */ mask |=3D (1 << 31) | (1 << 30) | (0xf << 20); =20 @@ -7814,7 +7814,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *c= pu) } else if (cpu_isar_feature(aa32_simd_r32, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 35, "arm-vfp3.xml", 0); - } else if (arm_feature(env, ARM_FEATURE_VFP)) { + } else if (cpu_isar_feature(aa32_simd_r16, cpu)) { gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg, 19, "arm-vfp.xml", 0); } diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index 33d414a684b..c0249702212 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -738,7 +738,8 @@ static uint32_t v7m_integrity_sig(CPUARMState *env, uin= t32_t lr) */ uint32_t sig =3D 0xfefa125a; =20 - if (!arm_feature(env, ARM_FEATURE_VFP) || (lr & R_V7M_EXCRET_FTYPE_MAS= K)) { + if (!cpu_isar_feature(aa32_simd_r16, env_archcpu(env)) + || (lr & R_V7M_EXCRET_FTYPE_MASK)) { sig |=3D 1; } return sig; @@ -841,7 +842,7 @@ static void v7m_exception_taken(ARMCPU *cpu, uint32_t l= r, bool dotailchain, =20 if (dotailchain) { /* Sanitize LR FType and PREFIX bits */ - if (!arm_feature(env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_simd_r16, cpu)) { lr |=3D R_V7M_EXCRET_FTYPE_MASK; } lr =3D deposit32(lr, 24, 8, 0xff); @@ -1373,7 +1374,7 @@ static void do_v7m_exception_exit(ARMCPU *cpu) =20 ftype =3D excret & R_V7M_EXCRET_FTYPE_MASK; =20 - if (!arm_feature(env, ARM_FEATURE_VFP) && !ftype) { + if (!ftype && !cpu_isar_feature(aa32_simd_r16, cpu)) { qemu_log_mask(LOG_GUEST_ERROR, "M profile: zero FTYPE in exception= " "exit PC value 0x%" PRIx32 " is UNPREDICTABLE " "if FPU not present\n", @@ -2450,7 +2451,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskr= eg, uint32_t val) * SFPA is RAZ/WI from NS. FPCA is RO if NSACR.CP10 =3D=3D 0, * RES0 if the FPU is not present, and is stored in the S bank */ - if (arm_feature(env, ARM_FEATURE_VFP) && + if (cpu_isar_feature(aa32_simd_r16, env_archcpu(env)) && extract32(env->v7m.nsacr, 10, 1)) { env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_FPCA_MASK; env->v7m.control[M_REG_S] |=3D val & R_V7M_CONTROL_FPCA_MA= SK; @@ -2565,7 +2566,7 @@ void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskr= eg, uint32_t val) env->v7m.control[env->v7m.secure] &=3D ~R_V7M_CONTROL_NPRIV_MA= SK; env->v7m.control[env->v7m.secure] |=3D val & R_V7M_CONTROL_NPR= IV_MASK; } - if (arm_feature(env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_simd_r16, env_archcpu(env))) { /* * SFPA is RAZ/WI from NS or if no FPU. * FPCA is RO if NSACR.CP10 =3D=3D 0, RES0 if the FPU is not p= resent. diff --git a/target/arm/machine.c b/target/arm/machine.c index 241890ac8cf..7050bde459a 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -9,9 +9,8 @@ static bool vfp_needed(void *opaque) { ARMCPU *cpu =3D opaque; - CPUARMState *env =3D &cpu->env; =20 - return arm_feature(env, ARM_FEATURE_VFP); + return cpu_isar_feature(aa32_simd_r16, cpu); } =20 static int get_fpscr(QEMUFile *f, void *opaque, size_t size, --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582292668; cv=none; d=zohomail.com; s=zohoarc; b=QA5zcV6m7luairNV67hmK7AYQTRs4FUZ3A9b2luK3qFvy0IeGi8zzoZeD2WGOS9xwv9aAoTY3YhRfRa+Y3KPg2LVNAS/qryuz9YXiOdQ4grFJEVlToko1Cce2R9Hs6gYExBldoHhGVoYKnbZDL9KzVUpUVyIQwvqLX1ZsAR72hQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582292668; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MIWznLdnWE1pFMfHWxMiE6FxWKUgvMpAlD3wW7jfjds=; b=bExdHkTFNGxy7F3XH64Z71rVgXPN2LQu15YmrFdPkRepoLr+okOM4sBfMlJJHbA+OCOUs2LG+6Enh9OaJ5pVmXwybWS81Elvzzdy9tAGdg5f5nib64Sn9x2TnR4a8Mg7stjakFND4+JTBQyH3riK0DmiSKskOmi9lAlml9fgezU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582292668933702.6135272259369; Fri, 21 Feb 2020 05:44:28 -0800 (PST) Received: from localhost ([::1]:58084 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58bT-0006tt-G1 for importer@patchew.org; Fri, 21 Feb 2020 08:44:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57213) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582v-000076-6V for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582t-00042K-JG for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:45 -0500 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:37815) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582t-0003zN-CC for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:43 -0500 Received: by mail-wm1-x32d.google.com with SMTP id a6so1779846wme.2 for ; Fri, 21 Feb 2020 05:08:43 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=MIWznLdnWE1pFMfHWxMiE6FxWKUgvMpAlD3wW7jfjds=; b=is/PFaW8zGweogkPvLVDAlK23Sq+QlNGBClHztcIvNP/nwuxVe1PJDMHuqLXXB+Bai ur1hX3zM8jm4Lv79tHysw78gzr8vt/lrhh9yrbVWCtbIpu44hLczkGv64ssk1/9osPj1 oQjz4Wg5Ysg2qTt0RVbV0JpVgq1O0k1t9k0xluME8s0Alb4Xc9m6U9NNkAfd90SsNgKP kSeWxFFikZwLnBA5sBTWfRpn56vL3uaQqJUsOP7Tgz8NL7Kn70Jmd+x4eFU5WEN4kinL yu69krCbBZmm+FoEt3EQQ+yY5f1ogfqVqtAJPO9B4b3YsUN8oAxTeXawyssi255EDflU l3/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MIWznLdnWE1pFMfHWxMiE6FxWKUgvMpAlD3wW7jfjds=; b=MobHtLO6gl2Xz+3iMO0CjjbNvfwXPreGmfwzYQp9LuWgHLsd2IsKCW9sbCvIefle6G fFnIy4COYGhY+xpKS9sUz1TJJ1mIx+CN0PFxcTcQxgjdBTRZarj+tQq1U4L4TrkajTAf d9dWxyWa7IiJLf1jXzbiWGUkENzQqLY/51mn6uQVQZiaEJpO8LnoqD8oRPbGRc2yg41K tLK9YXBipyPGrTWc2Ru86Ltn7Z3F26uuFggrlBYRd4Z9ZL55w+k7Feyupg3Ur7zr/G6X y53vgpGdcw/TgewrVeBvKF6X9MPEh0Myc7dfIInOczQgpd7rwN1GCBrnEaydrxQVQptw r4BA== X-Gm-Message-State: APjAAAUM/DLaXyKeUBAjK/RFHPj0CacoeTgUi3Brg+UGscqXKlBest6Z +MsyeNNNW2lX5Y2KIY6YPAK/UvvqsJ1BwQ== X-Google-Smtp-Source: APXvYqyjWXtgfwSpxOjyHl4sJfhL37PvL/N4KL60vpe57In8ttnzC6wigYBj/zibd9TK1yu10+61Lg== X-Received: by 2002:a1c:7712:: with SMTP id t18mr3982364wmi.32.1582290521168; Fri, 21 Feb 2020 05:08:41 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 48/52] target/arm: Rename isar_feature_aa32_fpdp_v2 Date: Fri, 21 Feb 2020 13:07:36 +0000 Message-Id: <20200221130740.7583-49-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Richard Henderson The old name, isar_feature_aa32_fpdp, does not reflect that the test includes VFPv2. We will introduce further feature tests for VFPv3. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200214181547.21408-7-richard.henderson@linaro.org [PMM: fixed grammar in commit message] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 4 ++-- target/arm/translate-vfp.inc.c | 40 +++++++++++++++++----------------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5a62586dd29..1e2aae276bf 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3467,9 +3467,9 @@ static inline bool isar_feature_aa32_fpshvec(const AR= MISARegisters *id) return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; } =20 -static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id) +static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) { - /* Return true if CPU supports double precision floating point */ + /* Return true if CPU supports double precision floating point, VFPv2 = */ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; } =20 diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index ba46e2557a1..e94876c30ca 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -206,7 +206,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -339,7 +339,7 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMA= XNM *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -425,7 +425,7 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -488,7 +488,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp, s)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1313,7 +1313,7 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpD= PFn *fn, return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1462,7 +1462,7 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpD= PFn *fn, int vd, int vm) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1827,7 +1827,7 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_dp = *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -1926,7 +1926,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VM= OV_imm_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2070,7 +2070,7 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_d= p *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2143,7 +2143,7 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_V= CVT_f64_f16 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2209,7 +2209,7 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_V= CVT_f16_f64 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2269,7 +2269,7 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRIN= TR_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2330,7 +2330,7 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRIN= TZ_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2389,7 +2389,7 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRIN= TX_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2417,7 +2417,7 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_s= p *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2445,7 +2445,7 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_d= p *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2499,7 +2499,7 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VC= VT_int_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2539,7 +2539,7 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2632,7 +2632,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VC= VT_fix_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 @@ -2728,7 +2728,7 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VC= VT_dp_int *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp, s)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582292591; cv=none; d=zohomail.com; s=zohoarc; b=KPD95cJ2jr5Wr5ULjXf4ZFJwojvnO2SH4qlwXSFzgc1DJA7N/W+5fUYgO2RQGKM0aUmWflWkQJR+5tYRdtR9I7gxfa0e6P/EkZCfgDlt8aSzsYIgNVjk/mPgx4MpK6H94/gGRadVF4INybutYGyWJ6gxnNT5o5dJ7/oINifPihA= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=OE8kMh53THu/LOHp2dUI69ASdc4neCkr/cEZCIA4G00=; b=x7c21t0/ASt5sQMjtnq9eFH6tgbzKMhFX7BmwGOHHwzp3w8W8pMqE4qwarKRrzQg1t aMQGdlgCQGZgCyQWL7lUdJpQ+SPQuCnWtDRVXgUOA9PabRedUXdWeB1McfwfAF/je6Rp DBQbm8aP3+h15iqnsTL7J+Fvz/mXyA09yoJk7axQkuNgGf4BVwwLQ4XjGUbwqxP9IGu1 qr60hWLg8HRTU5owXu3fpOwOtVYarrNCi4zGeiT1TuBJrsDfXWRjG1ANo2nVkldvGa5n kZT5MiKPjMEjHaOm8jG294a4D0kx/eOmmmjh/fdkHJFet88LxxXPqbvHtX+gb5Bw60fE K2hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OE8kMh53THu/LOHp2dUI69ASdc4neCkr/cEZCIA4G00=; b=PPY1km17qrQVnEZntKlGNraahh5xuEHk/R+3FHbkx9gIQV8Pl1n/5UjkQPpwzlXNZr XFRz5TYLlOkoAO4YIpwHoVO2XzoE1887eC9avn49F2Hu3bFqKPLaT30UDWpfBrWfLOms qCxBrFPEZVcZYVkggClmy9WQLLbtIQuz7LFyx8NglzN7s2bmyYEAgBO7htdIv4Z5lIxC 4H7A830K7xMLV4MoNDfuR3RPGii2f2w+LW5Ra9/BQwheWMczB7LUV4rLRz4iOSnqjP1y fYS9v/03o70RzNyKaO29XPepMjjJmvW6cJqVEC53HLOaYNAynUX2CDs57w6hKQIZ66X7 fnEQ== X-Gm-Message-State: APjAAAUND0g1zha4x16V3tXSpdudal622ijxoUwOn0XyG0hIu5X3egwD yVwHOFAMROmsLwXQoCwSKUoZamLZxik41w== X-Google-Smtp-Source: APXvYqwd6bUFm1HvedTFDKg4NPAZLVBj626COG8/BduzWhgtlZrm0rUu7VDmrE8V3ZcmcdDTJ2bcHA== X-Received: by 2002:a5d:4fce:: with SMTP id h14mr52714383wrw.60.1582290522540; Fri, 21 Feb 2020 05:08:42 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 49/52] target/arm: Add isar_feature_aa32_{fpsp_v2, fpsp_v3, fpdp_v3} Date: Fri, 21 Feb 2020 13:07:37 +0000 Message-Id: <20200221130740.7583-50-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::431 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We will shortly use these to test for VFPv2 and VFPv3 in different situations. Signed-off-by: Richard Henderson Message-id: 20200214181547.21408-8-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.h | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1e2aae276bf..a7fc86c23cf 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3467,12 +3467,30 @@ static inline bool isar_feature_aa32_fpshvec(const = ARMISARegisters *id) return FIELD_EX32(id->mvfr0, MVFR0, FPSHVEC) > 0; } =20 +static inline bool isar_feature_aa32_fpsp_v2(const ARMISARegisters *id) +{ + /* Return true if CPU supports single precision floating point, VFPv2 = */ + return FIELD_EX32(id->mvfr0, MVFR0, FPSP) > 0; +} + +static inline bool isar_feature_aa32_fpsp_v3(const ARMISARegisters *id) +{ + /* Return true if CPU supports single precision floating point, VFPv3 = */ + return FIELD_EX32(id->mvfr0, MVFR0, FPSP) >=3D 2; +} + static inline bool isar_feature_aa32_fpdp_v2(const ARMISARegisters *id) { /* Return true if CPU supports double precision floating point, VFPv2 = */ return FIELD_EX32(id->mvfr0, MVFR0, FPDP) > 0; } =20 +static inline bool isar_feature_aa32_fpdp_v3(const ARMISARegisters *id) +{ + /* Return true if CPU supports double precision floating point, VFPv3 = */ + return FIELD_EX32(id->mvfr0, MVFR0, FPDP) >=3D 2; +} + /* * We always set the FP and SIMD FP16 fields to indicate identical * levels of support (assuming SIMD is implemented at all), so --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582292795; cv=none; d=zohomail.com; s=zohoarc; b=axocPUxjj0y4W9yE+VN+SZ/l0wq5rkSAryXBuscqsFQhHXzL5yGEsU8f9brYuYhfB2x+qOGOWhkJfYOFhXr1uwXJVwe5U7IlT/v/vxjFe7PQWte179Hm9CGPXoXfSiUD8BgIecFeZTkal3HLw2tO9msa7KqP3Saxh30JH/f6F98= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582292795; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=o70TLclVtljlg7/9KQCzXuefdakLjZMqljQvUwUXHGo=; b=FiRn6bYO/wWfVhd7QjfkINsu7aCOKh0gAqiNUtigt8i+J89Cf7Sn3iBLukJYI92ajfl8nwlLyZhYIq1ev7TrERZGT6if8QQ+ruhFz5t0YmhmyGoht6gLyylMaJGFttXzSZbDh2Ub2+3vvcewtcEUrc75RDTqxWGF5QBJBA5s8kw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582292795761819.6417310031441; Fri, 21 Feb 2020 05:46:35 -0800 (PST) Received: from localhost ([::1]:58162 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j58dW-0001Bo-RL for importer@patchew.org; Fri, 21 Feb 2020 08:46:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57266) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j582x-0000Ea-MX for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j582v-0004AO-RS for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:47 -0500 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:34916) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1j582v-00047r-Ip for qemu-devel@nongnu.org; Fri, 21 Feb 2020 08:08:45 -0500 Received: by mail-wr1-x441.google.com with SMTP id w12so2012500wrt.2 for ; Fri, 21 Feb 2020 05:08:45 -0800 (PST) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.42 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=o70TLclVtljlg7/9KQCzXuefdakLjZMqljQvUwUXHGo=; b=AjrI6/hOiCLrgWDC0YOwxOFtCJUKz1hirHOAoDmtRlgKG4fZgCyumiRuM5a2LlpWeU Z1JaOwQ5LCukfrOU4kWS8IwKEI8W23a3RbwUIfX1eFJD/2b2MSs7V40zrZs3vpcjno8o o66dKkeUh6Yl2MT88lSPOTj0h89ZDXUXoUFnDv9RzuGCpfVN8ro8TlAsm7yXh0CJ5mjI WCmbp6Y4js2Zn2D7OZTjyfDLCb5YwLdf78yAImBauAM/V1QK4i0trdkdX0w8SK6tMksC HxKkUHaEtZStTLt47qy6FlZW4HcJ158oAOFx/JM2CDFcr+EiTM7ryLanhMiDL4+sDjOb 5c1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=o70TLclVtljlg7/9KQCzXuefdakLjZMqljQvUwUXHGo=; b=X/Vg5Ria5TGRlWF55wcHEhDFX6WI6u0wVQhbLXMONPpPnntMqLwKSBz2xNoteBWplD ZdXG9r5B/Rp1UjLDOPiH16fSOKiFwnoOa8W+1UUU8N41dT+51I2lvLPB8mCZr3l+LCiy 5Zovu2lOgjqtuPIhKj7cTHnNQdi7kCdnFmBI7LVo6DphWPw2z+IolQwlF2fIndC6hZHM 2JFFnfO5YKruB/ursI8+rsbFCJcbl91MeDQ47kY2cAXQCtEKsskvcAjr7HKF2LzhNE7y YrHB9Nya1HWG3/uu/TKJyEeqCOZsBe741tnIGkncGeo2/1prjyhABm22THa/rHglwiDr sbcw== X-Gm-Message-State: APjAAAWI5fSq9ql2Z1rySYwUpuMNOgWrJCfGXCBwvoBiwf9j96FbuKt/ IwUwPT1zQJVvTDeIncPdAsn2fpOCFILamw== X-Google-Smtp-Source: APXvYqw8wodvLyqB4cZq3gdysHWrq9iN0zmzOjQYry5i3GNHIYs79GZWVcIKCLWYH+VxZDdaj38HmQ== X-Received: by 2002:a5d:560d:: with SMTP id l13mr22514211wrv.222.1582290524024; Fri, 21 Feb 2020 05:08:44 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 50/52] target/arm: Perform fpdp_v2 check first Date: Fri, 21 Feb 2020 13:07:38 +0000 Message-Id: <20200221130740.7583-51-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Shuffle the order of the checks so that we test the ISA before we test anything else, such as the register arguments. Signed-off-by: Richard Henderson Message-id: 20200214181547.21408-9-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-vfp.inc.c | 144 ++++++++++++++++----------------- 1 file changed, 72 insertions(+), 72 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index e94876c30ca..0c551401273 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -200,13 +200,13 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vn | a->vd) & 0x10)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && + ((a->vm | a->vn | a->vd) & 0x10)) { return false; } =20 @@ -333,13 +333,13 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMIN= MAXNM *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vn | a->vd) & 0x10)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && + ((a->vm | a->vn | a->vd) & 0x10)) { return false; } =20 @@ -419,13 +419,13 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && - ((a->vm | a->vd) & 0x10)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && + ((a->vm | a->vd) & 0x10)) { return false; } =20 @@ -483,12 +483,12 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (dp && !dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (dp && !dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 @@ -1308,12 +1308,12 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3O= pDPFn *fn, TCGv_i64 f0, f1, fd; TCGv_ptr fpst; =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vn | vm) & 0x10)) { return false; } =20 @@ -1457,12 +1457,12 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2O= pDPFn *fn, int vd, int vm) int veclen =3D s->vec_len; TCGv_i64 f0, fd; =20 - /* UNDEF accesses to D16-D31 if they don't exist */ - if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist */ + if (!dc_isar_feature(aa32_simd_r32, s) && ((vd | vm) & 0x10)) { return false; } =20 @@ -1821,13 +1821,13 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_d= p *a) return false; } =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && - ((a->vd | a->vn | a->vm) & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && + ((a->vd | a->vn | a->vm) & 0x10)) { return false; } =20 @@ -1921,12 +1921,12 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_= VMOV_imm_dp *a) =20 vd =3D a->vd; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (vd & 0x10)) { return false; } =20 @@ -2060,6 +2060,10 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_= dp *a) { TCGv_i64 vd, vm; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + /* Vm/M bits must be zero for the Z variant */ if (a->z && a->vm !=3D 0) { return false; @@ -2070,10 +2074,6 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_= dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2134,6 +2134,10 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_= VCVT_f64_f16 *a) TCGv_i32 tmp; TCGv_i64 vd; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_fp16_dpconv, s)) { return false; } @@ -2143,10 +2147,6 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_= VCVT_f64_f16 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2200,6 +2200,10 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_= VCVT_f16_f64 *a) TCGv_i32 tmp; TCGv_i64 vm; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_fp16_dpconv, s)) { return false; } @@ -2209,10 +2213,6 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_= VCVT_f16_f64 *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2260,6 +2260,10 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRI= NTR_dp *a) TCGv_ptr fpst; TCGv_i64 tmp; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_vrint, s)) { return false; } @@ -2269,10 +2273,6 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRI= NTR_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2321,6 +2321,10 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRI= NTZ_dp *a) TCGv_i64 tmp; TCGv_i32 tcg_rmode; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_vrint, s)) { return false; } @@ -2330,10 +2334,6 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRI= NTZ_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2380,6 +2380,10 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRI= NTX_dp *a) TCGv_ptr fpst; TCGv_i64 tmp; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_vrint, s)) { return false; } @@ -2389,10 +2393,6 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRI= NTX_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2412,12 +2412,12 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT= _sp *a) TCGv_i64 vd; TCGv_i32 vm; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; } =20 @@ -2440,12 +2440,12 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT= _dp *a) TCGv_i64 vm; TCGv_i32 vd; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 @@ -2494,12 +2494,12 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_= VCVT_int_dp *a) TCGv_i64 vd; TCGv_ptr fpst; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; } =20 @@ -2530,6 +2530,10 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *= a) TCGv_i32 vd; TCGv_i64 vm; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_jscvt, s)) { return false; } @@ -2539,10 +2543,6 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *= a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2623,6 +2623,10 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_V= CVT_fix_dp *a) TCGv_ptr fpst; int frac_bits; =20 + if (!dc_isar_feature(aa32_fpdp_v2, s)) { + return false; + } + if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { return false; } @@ -2632,10 +2636,6 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_V= CVT_fix_dp *a) return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2723,12 +2723,12 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_= VCVT_dp_int *a) TCGv_i64 vm; TCGv_ptr fpst; =20 - /* UNDEF accesses to D16-D31 if they don't exist. */ - if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { + if (!dc_isar_feature(aa32_fpdp_v2, s)) { return false; } =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { return false; } =20 --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=81QiuxFnI/2n9UAjb2neO09HEKDLboGr1Lbfkl3Yhyw=; b=AtrZtE2SDaB6Z7hRDalZ2iSpfqYdejY6tXwoah+8JlSM12NO1PwXiZ0oxs+Rhrqrkq 0mkJC4jiE3rjuUBVAGKYB48wKJ7/OF2zSoqqtxnd2QlIfqFRb29Xkf+8DBzKieCsZ0O5 ssaII7XPlktm3Fvr8NOx9wkAxH8vaTbJf5c9v5rFyOw4paMMSo73vBGsAbccbtSetO65 QQYR+NSvPcbJ2dcW0gvxLNg+67tp0pDn4L+49Q09u0Yv/PUBnPhBj+RUDpuDHBX+ih+j TNBoSJjDE33vLeNOv7ShNN0p9t8Gq7BeJls7ZRU5RELIbMWYAI528VSvX6cV2QCdwWkp +hgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=81QiuxFnI/2n9UAjb2neO09HEKDLboGr1Lbfkl3Yhyw=; b=IhSzBk49mIhMu6M/+dTC6CRfa1QO2D9X5fadZOEHpOUfZFNwzcwzxp8TW5nmElpfGC gV2AFjl0aU8NBopX2RTFqw5xo7BAfBW1x4Xl/3Z3ZOv60MSx8ZeRV2iz8+o8cRTElu9G ZLc2MZzx1OpjTGbyODFm0lkgVVJl2w3htmnzrQxQ6bMw2BDEtT3VUivnH9z8yVUjhMsz yZfFJWgUEr5dIWClQqcv0WvPqvK8QkGLbENVHmsvLhEbW4cajGURuJk/qKcJ5X1pDzbY tot3BNGLQ/Uh8t9iwdXPuXYCdZH4KDob31a1cH0S01pua18UXWKo1YlbkPv7hLEaLPfZ LwwQ== X-Gm-Message-State: APjAAAX0Xos942ner8e1ZYIxbdNGnQBK5wiHI5rymY4zLLDxVhnNX/MF ApsYDMFHflK2a0BIDFPt83Q6RGyDxUYtNw== X-Google-Smtp-Source: APXvYqzTht2iBDy6qAxMZMw7eXegGteO3KnQdKlG4zFNqQGFUNJKelUlnM4+X/y8tn2ekzj3hl4PDA== X-Received: by 2002:adf:d850:: with SMTP id k16mr47831546wrl.216.1582290525353; Fri, 21 Feb 2020 05:08:45 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 51/52] target/arm: Replace ARM_FEATURE_VFP3 checks with fp{sp, dp}_v3 Date: Fri, 21 Feb 2020 13:07:39 +0000 Message-Id: <20200221130740.7583-52-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson Sort this check to the start of a trans_* function. Merge this with any existing test for fpdp_v2. Signed-off-by: Richard Henderson Message-id: 20200214181547.21408-10-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-vfp.inc.c | 24 ++++++++---------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 0c551401273..9e5516f208b 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -717,7 +717,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_V= MRS *a) * VFPv2 allows access to FPSID from userspace; VFPv3 restricts * all ID registers to privileged access only. */ - if (IS_USER(s) && arm_dc_feature(s, ARM_FEATURE_VFP3)) { + if (IS_USER(s) && dc_isar_feature(aa32_fpsp_v3, s)) { return false; } ignore_vfp_enabled =3D true; @@ -746,7 +746,7 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_V= MRS *a) case ARM_VFP_FPINST: case ARM_VFP_FPINST2: /* Not present in VFPv3 */ - if (IS_USER(s) || arm_dc_feature(s, ARM_FEATURE_VFP3)) { + if (IS_USER(s) || dc_isar_feature(aa32_fpsp_v3, s)) { return false; } break; @@ -1871,12 +1871,12 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_= VMOV_imm_sp *a) =20 vd =3D a->vd; =20 - if (!dc_isar_feature(aa32_fpshvec, s) && - (veclen !=3D 0 || s->vec_stride !=3D 0)) { + if (!dc_isar_feature(aa32_fpsp_v3, s)) { return false; } =20 - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { + if (!dc_isar_feature(aa32_fpshvec, s) && + (veclen !=3D 0 || s->vec_stride !=3D 0)) { return false; } =20 @@ -1921,7 +1921,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VM= OV_imm_dp *a) =20 vd =3D a->vd; =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { + if (!dc_isar_feature(aa32_fpdp_v3, s)) { return false; } =20 @@ -1935,10 +1935,6 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_V= MOV_imm_dp *a) return false; } =20 - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -2563,7 +2559,7 @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VC= VT_fix_sp *a) TCGv_ptr fpst; int frac_bits; =20 - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { + if (!dc_isar_feature(aa32_fpsp_v3, s)) { return false; } =20 @@ -2623,11 +2619,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_V= CVT_fix_dp *a) TCGv_ptr fpst; int frac_bits; =20 - if (!dc_isar_feature(aa32_fpdp_v2, s)) { - return false; - } - - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { + if (!dc_isar_feature(aa32_fpdp_v3, s)) { return false; } =20 --=20 2.20.1 From nobody Wed May 8 20:22:04 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1582292904; cv=none; d=zohomail.com; s=zohoarc; b=kGw0pX9ASL1c3vkO3KajvVcM3OgD9njWdOx/hYgkBNG92fh5ay3p3Pf7dadT0kQZ/7k+5DZA4ZpBwn288QPbtPBqHTDqudBm+O6a0h2nzRhgEFIBYTE+sSddr2H1B15i5E86UcYkvhkVdrfG4kEenR4hzm5rHpNGwoxmWndoZrE= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id p15sm3598892wma.40.2020.02.21.05.08.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 21 Feb 2020 05:08:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Iz5SxgRp9AmsPyanvIiNpsW+vmai2Z4aR3Ygzd1pADY=; b=iOLaaStUh43kskC+45LRVwBoDHwTrL+GKx0yi/1e7qICF2OdtmQc9WNxclg529p8QO pw9hBf6nBTvucD6tJ76YfzCG7IyN8F9Jhp0wYCfVEbjpEqC+5HgxXn5PvqRY6/X5Doon OZj7bpi5z8c3+VsvLzZyAt7HzhVPhYYvIBwZgjDhYWQRVdxy9bE260fqSxA64qhamcPA ARHlcejd4MoOKv4IkxC+jI4/VnbMCTZDgV+5YIOSqhV8oosvJPdYSY0zIlYo8T3nF3sR qWaoUpBf1KLXKEZw9IF2Rk65CaRJqTdoY/Zz6q8+zjY/AYpn/weU4033P7DENlVATyJb FAKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Iz5SxgRp9AmsPyanvIiNpsW+vmai2Z4aR3Ygzd1pADY=; b=Peq2/oDepmFMz8/5WFueryg5IqIPfo/1QkJE4Ijy3QfiNNylyaUqmf8a7Wy5lfh42S FLsvZrL3FNuNCk1ITDY4Ou153Ic+dnfqC/OtMo/iq1N8BiEDu6ANNTIP8Kqd+h+vfDi1 skiDAbezIpob80+Q0PLsv5VLc/3cNHEFPSyL9Txz3BXHQPyExEqmHBUHsY5YhID2YAAG MZYzNF7IwLNCjQv0yO9hH159yJLgLkqz5yLyOsWmOrthWy9VJauHO5RL8Zk0XkkZMiNG XdPOod9/N6MAbLNrqtxlHfFa6qLwus5JWUY46aDMcP8h6zU5YhsncoVIF0dBP0/wwtTh 0h5w== X-Gm-Message-State: APjAAAU/Mu90jM5sSHg7oyuwB5iBp3wR0Lg2ryjB1Va7AfCOxnsviwzD O0ROtOVDcVthBwomMQHyhl+yCLcnwpGxBQ== X-Google-Smtp-Source: APXvYqwfFyfHW3TpSDIYNDnI0uSYnuGLe4O/5qu6KWQvtTUxUhsnwme0SOo6DzPdymdOi8X6q/nXAw== X-Received: by 2002:a5d:65c6:: with SMTP id e6mr21383951wrw.45.1582290526636; Fri, 21 Feb 2020 05:08:46 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 52/52] target/arm: Add missing checks for fpsp_v2 Date: Fri, 21 Feb 2020 13:07:40 +0000 Message-Id: <20200221130740.7583-53-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200221130740.7583-1-peter.maydell@linaro.org> References: <20200221130740.7583-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson We will eventually remove the early ARM_FEATURE_VFP test, so add a proper test for each trans_* that does not already have another ISA test. Signed-off-by: Richard Henderson Message-id: 20200214181547.21408-11-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/translate-vfp.inc.c | 78 ++++++++++++++++++++++++++++++---- 1 file changed, 69 insertions(+), 9 deletions(-) diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c index 9e5516f208b..89133202590 100644 --- a/target/arm/translate-vfp.inc.c +++ b/target/arm/translate-vfp.inc.c @@ -555,6 +555,13 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV= _to_gp *a) int pass; uint32_t offset; =20 + /* SIZE =3D=3D 2 is a VFP instruction; otherwise NEON. */ + if (a->size =3D=3D 2 + ? !dc_isar_feature(aa32_fpsp_v2, s) + : !arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { return false; @@ -564,10 +571,6 @@ static bool trans_VMOV_to_gp(DisasContext *s, arg_VMOV= _to_gp *a) pass =3D extract32(offset, 2, 1); offset =3D extract32(offset, 0, 2) * 8; =20 - if (a->size !=3D 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -614,6 +617,13 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VM= OV_from_gp *a) int pass; uint32_t offset; =20 + /* SIZE =3D=3D 2 is a VFP instruction; otherwise NEON. */ + if (a->size =3D=3D 2 + ? !dc_isar_feature(aa32_fpsp_v2, s) + : !arm_dc_feature(s, ARM_FEATURE_NEON)) { + return false; + } + /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vn & 0x10)) { return false; @@ -623,10 +633,6 @@ static bool trans_VMOV_from_gp(DisasContext *s, arg_VM= OV_from_gp *a) pass =3D extract32(offset, 2, 1); offset =3D extract32(offset, 0, 2) * 8; =20 - if (a->size !=3D 2 && !arm_dc_feature(s, ARM_FEATURE_NEON)) { - return false; - } - if (!vfp_access_check(s)) { return true; } @@ -700,6 +706,10 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_= VMRS *a) TCGv_i32 tmp; bool ignore_vfp_enabled =3D false; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (arm_dc_feature(s, ARM_FEATURE_M)) { /* * The only M-profile VFP vmrs/vmsr sysreg is FPSCR. @@ -844,6 +854,10 @@ static bool trans_VMOV_single(DisasContext *s, arg_VMO= V_single *a) { TCGv_i32 tmp; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -873,6 +887,10 @@ static bool trans_VMOV_64_sp(DisasContext *s, arg_VMOV= _64_sp *a) { TCGv_i32 tmp; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + /* * VMOV between two general-purpose registers and two single precision * floating point registers @@ -908,8 +926,12 @@ static bool trans_VMOV_64_dp(DisasContext *s, arg_VMOV= _64_dp *a) =20 /* * VMOV between two general-purpose registers and one double precision - * floating point register + * floating point register. Note that this does not require support + * for double precision arithmetic. */ + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } =20 /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vm & 0x10)) { @@ -946,6 +968,10 @@ static bool trans_VLDR_VSTR_sp(DisasContext *s, arg_VL= DR_VSTR_sp *a) uint32_t offset; TCGv_i32 addr, tmp; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -977,6 +1003,11 @@ static bool trans_VLDR_VSTR_dp(DisasContext *s, arg_V= LDR_VSTR_dp *a) TCGv_i32 addr; TCGv_i64 tmp; =20 + /* Note that this does not require support for double arithmetic. */ + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + /* UNDEF accesses to D16-D31 if they don't exist */ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) { return false; @@ -1013,6 +1044,10 @@ static bool trans_VLDM_VSTM_sp(DisasContext *s, arg_= VLDM_VSTM_sp *a) TCGv_i32 addr, tmp; int i, n; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + n =3D a->imm; =20 if (n =3D=3D 0 || (a->vd + n) > 32) { @@ -1086,6 +1121,11 @@ static bool trans_VLDM_VSTM_dp(DisasContext *s, arg_= VLDM_VSTM_dp *a) TCGv_i64 tmp; int i, n; =20 + /* Note that this does not require support for double arithmetic. */ + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + n =3D a->imm >> 1; =20 if (n =3D=3D 0 || (a->vd + n) > 32 || n > 16) { @@ -1234,6 +1274,10 @@ static bool do_vfp_3op_sp(DisasContext *s, VFPGen3Op= SPFn *fn, TCGv_i32 f0, f1, fd; TCGv_ptr fpst; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_fpshvec, s) && (veclen !=3D 0 || s->vec_stride !=3D 0)) { return false; @@ -1388,6 +1432,10 @@ static bool do_vfp_2op_sp(DisasContext *s, VFPGen2Op= SPFn *fn, int vd, int vm) int veclen =3D s->vec_len; TCGv_i32 f0, fd; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!dc_isar_feature(aa32_fpshvec, s) && (veclen !=3D 0 || s->vec_stride !=3D 0)) { return false; @@ -2021,6 +2069,10 @@ static bool trans_VCMP_sp(DisasContext *s, arg_VCMP_= sp *a) { TCGv_i32 vd, vm; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + /* Vm/M bits must be zero for the Z variant */ if (a->z && a->vm !=3D 0) { return false; @@ -2464,6 +2516,10 @@ static bool trans_VCVT_int_sp(DisasContext *s, arg_V= CVT_int_sp *a) TCGv_i32 vm; TCGv_ptr fpst; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } @@ -2682,6 +2738,10 @@ static bool trans_VCVT_sp_int(DisasContext *s, arg_V= CVT_sp_int *a) TCGv_i32 vm; TCGv_ptr fpst; =20 + if (!dc_isar_feature(aa32_fpsp_v2, s)) { + return false; + } + if (!vfp_access_check(s)) { return true; } --=20 2.20.1