From nobody Tue Feb 10 23:13:19 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1582278552; cv=none; d=zohomail.com; s=zohoarc; b=jqnDGXHtpiNo4CnRVUfQPINSe6GjihKkMu5A/FMRJ7UKDud8oiE2sLiW//yvOk1OpuhVcLx4fEPwemImdk/bIKRnxN3SXhX3Kn0HACGTp042s/hMI/Mtnru9upnJEwcimP8PNJ8erIu5l19UY6LZeU+hqo/ozem+euHFmNdvBTE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582278552; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9hdWNw+kI7+T+71OV21hdjGHUicrsMT8bAVlDEjuPHY=; b=UZrFg1RwXZvE/sEh9qWuiZgWm+9eU4yr3sW08i2In7qBVAWrySIinkHKL0FBQHF4S0yy4e/5tFNszcRdg1paNx5PBPwX/tJPruF4FCgLdOCn2wTYDxTLLXNYVKvU9h+BUgqgmLeIOkMHLvOq+VyBYERvPEWHiwQTrR9w9l0jQnI= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582278552511383.96288133250573; Fri, 21 Feb 2020 01:49:12 -0800 (PST) Received: from localhost ([::1]:54562 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j54vm-0007vS-I1 for importer@patchew.org; Fri, 21 Feb 2020 04:49:11 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:33357) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j54sh-0003qu-MZ for qemu-devel@nongnu.org; Fri, 21 Feb 2020 04:46:00 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j54sg-00020A-On for qemu-devel@nongnu.org; Fri, 21 Feb 2020 04:45:59 -0500 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:48765) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j54sg-0001hZ-Ck; Fri, 21 Feb 2020 04:45:58 -0500 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.GqUN7u9_1582278331) by smtp.aliyun-inc.com(10.147.43.95); Fri, 21 Feb 2020 17:45:52 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1012324|-1; CH=green; DM=CONTINUE|CONTINUE|true|0.0847261-0.00699878-0.908275; DS=CONTINUE|ham_system_inform|0.0300927-0.000453369-0.969454; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03311; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=9; RT=9; SR=0; TI=SMTPD_---.GqUN7u9_1582278331; From: LIU Zhiwei To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Subject: [PATCH v5 1/4] target/riscv: add vector extension field in CPURISCVState Date: Fri, 21 Feb 2020 17:45:28 +0800 Message-Id: <20200221094531.61894-2-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200221094531.61894-1-zhiwei_liu@c-sky.com> References: <20200221094531.61894-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wenmeng_zhang@c-sky.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" The 32 vector registers will be viewed as a continuous memory block. It avoids the convension between element index and (regno, offset). Thus elements can be directly accessed by offset from the first vector base address. Signed-off-by: LIU Zhiwei Acked-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index de0a8d893a..2e8d01c155 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -64,6 +64,7 @@ #define RVA RV('A') #define RVF RV('F') #define RVD RV('D') +#define RVV RV('V') #define RVC RV('C') #define RVS RV('S') #define RVU RV('U') @@ -93,9 +94,20 @@ typedef struct CPURISCVState CPURISCVState; =20 #include "pmp.h" =20 +#define RV_VLEN_MAX 512 + struct CPURISCVState { target_ulong gpr[32]; uint64_t fpr[32]; /* assume both F and D extensions */ + + /* vector coprocessor state. */ + uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); + target_ulong vxrm; + target_ulong vxsat; + target_ulong vl; + target_ulong vstart; + target_ulong vtype; + target_ulong pc; target_ulong load_res; target_ulong load_val; --=20 2.23.0