From nobody Sat Apr 27 19:08:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1582267018; cv=none; d=zohomail.com; s=zohoarc; b=I90VJsD+uv4nuS1guVva0Qhcw4enDVq/jRaBWQqA0B0ynfTgwFClk1KsfBqmE2ahCnG01izXcN8IFk9H74TrW7rrU7hZx3Wugfb+et7KXk3wGWygswjmiUNzYKkgryBeUK3A4U7QjU/o98ABUvOkq3KxrGu3OOyDUL5nDIdcUPM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582267018; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=v/J5qGPVLdczyWp/CG4jyszQpAIX+ZVZ9IxmtKPwMGA=; b=dRJ/NR1PHhNyF+1YQwfw24IhT3z+ZtH8zD0yQjg4UY6HUTqEeAwkcyhu9cLlZEsLQATB/LC3O0ztGZT7yIhUEMFyP5LUQ7vMTAZ8J24ldjhojxx4JLw2jR1hP13UlgV+G25t5y8/CFaxjQ3zuobixjNQwYZzN7wY7pwvFCh3xPU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582267018335317.0713771427993; Thu, 20 Feb 2020 22:36:58 -0800 (PST) Received: from localhost ([::1]:52800 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j51vk-0000iL-7l for importer@patchew.org; Fri, 21 Feb 2020 01:36:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38512) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j51uZ-0007xf-3y for qemu-devel@nongnu.org; Fri, 21 Feb 2020 01:35:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j51uX-0003Lp-K9 for qemu-devel@nongnu.org; Fri, 21 Feb 2020 01:35:43 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:57174 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j51uX-0002xN-0n for qemu-devel@nongnu.org; Fri, 21 Feb 2020 01:35:41 -0500 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id AA499AC79C8CDD24B317; Fri, 21 Feb 2020 14:35:30 +0800 (CST) Received: from DESKTOP-D7EVK5B.china.huawei.com (10.173.221.29) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.439.0; Fri, 21 Feb 2020 14:35:22 +0800 From: Yubo Miao To: , Subject: [RFC v3 1/3] acpi:Extract two APIs from acpi_dsdt_add_pci Date: Fri, 21 Feb 2020 14:35:10 +0800 Message-ID: <20200221063512.1104-2-miaoyubo@huawei.com> X-Mailer: git-send-email 2.24.1.windows.2 In-Reply-To: <20200221063512.1104-1-miaoyubo@huawei.com> References: <20200221063512.1104-1-miaoyubo@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.173.221.29] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: imammedo@redhat.com, miaoyubo@huawei.com, qemu-devel@nongnu.org, xiexiangyou@huawei.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: miaoyubo Extract two APIs acpi_dsdt_add_pci_route_table and acpi_dsdt_add_pci_osc form acpi_dsdt_add_pci. The first API is used to specify the pci route table and the second API is used to declare the operation system capabilities. These two APIs would be used to specify the pxb-pcie in DSDT. Signed-off-by: miaoyubo --- hw/arm/virt-acpi-build.c | 135 ++++++++++++++++++++++----------------- 1 file changed, 75 insertions(+), 60 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index bd5f771e9b..0540234b8a 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -151,30 +151,12 @@ static void acpi_dsdt_add_virtio(Aml *scope, } } =20 -static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, - uint32_t irq, bool use_highmem, bool highmem= _ecam) +static void acpi_dsdt_add_pci_route_table(Aml *dev, Aml *scope, + int nr_pcie_buses, + uint32_t irq) { - int ecam_id =3D VIRT_ECAM_ID(highmem_ecam); - Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; int i, bus_no; - hwaddr base_mmio =3D memmap[VIRT_PCIE_MMIO].base; - hwaddr size_mmio =3D memmap[VIRT_PCIE_MMIO].size; - hwaddr base_pio =3D memmap[VIRT_PCIE_PIO].base; - hwaddr size_pio =3D memmap[VIRT_PCIE_PIO].size; - hwaddr base_ecam =3D memmap[ecam_id].base; - hwaddr size_ecam =3D memmap[ecam_id].size; - int nr_pcie_buses =3D size_ecam / PCIE_MMCFG_SIZE_MIN; - - Aml *dev =3D aml_device("%s", "PCI0"); - aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); - aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); - aml_append(dev, aml_name_decl("_SEG", aml_int(0))); - aml_append(dev, aml_name_decl("_BBN", aml_int(0))); - aml_append(dev, aml_name_decl("_ADR", aml_int(0))); - aml_append(dev, aml_name_decl("_UID", aml_string("PCI0"))); - aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); - aml_append(dev, aml_name_decl("_CCA", aml_int(1))); - + Aml *method, *crs; /* Declare the PCI Routing Table. */ Aml *rt_pkg =3D aml_varpackage(nr_pcie_buses * PCI_NUM_PINS); for (bus_no =3D 0; bus_no < nr_pcie_buses; bus_no++) { @@ -190,7 +172,6 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapE= ntry *memmap, } aml_append(dev, aml_name_decl("_PRT", rt_pkg)); =20 - /* Create GSI link device */ for (i =3D 0; i < PCI_NUM_PINS; i++) { uint32_t irqs =3D irq + i; Aml *dev_gsi =3D aml_device("GSI%d", i); @@ -210,42 +191,11 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMa= pEntry *memmap, aml_append(dev_gsi, method); aml_append(dev, dev_gsi); } +} =20 - method =3D aml_method("_CBA", 0, AML_NOTSERIALIZED); - aml_append(method, aml_return(aml_int(base_ecam))); - aml_append(dev, method); - - method =3D aml_method("_CRS", 0, AML_NOTSERIALIZED); - Aml *rbuf =3D aml_resource_template(); - aml_append(rbuf, - aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, - 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, - nr_pcie_buses)); - aml_append(rbuf, - aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_m= mio, - base_mmio + size_mmio - 1, 0x0000, size_mmio)); - aml_append(rbuf, - aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, - AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_= pio, - size_pio)); - - if (use_highmem) { - hwaddr base_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].base; - hwaddr size_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].size; - - aml_append(rbuf, - aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, - base_mmio_high, - base_mmio_high + size_mmio_high - 1, 0x0000, - size_mmio_high)); - } - - aml_append(method, aml_name_decl("RBUF", rbuf)); - aml_append(method, aml_return(rbuf)); - aml_append(dev, method); - +static void acpi_dsdt_add_pci_osc(Aml *dev, Aml *scope) +{ + Aml *method, *UUID, *ifctx, *ifctx1, *elsectx, *buf; /* Declare an _OSC (OS Control Handoff) method */ aml_append(dev, aml_name_decl("SUPP", aml_int(0))); aml_append(dev, aml_name_decl("CTRL", aml_int(0))); @@ -253,7 +203,8 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapE= ntry *memmap, aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); =20 - /* PCI Firmware Specification 3.0 + /* + * PCI Firmware Specification 3.0 * 4.5.1. _OSC Interface for PCI Host Bridge Devices * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is * identified by the Universal Unique IDentifier (UUID) @@ -298,7 +249,8 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapE= ntry *memmap, =20 method =3D aml_method("_DSM", 4, AML_NOTSERIALIZED); =20 - /* PCI Firmware Specification 3.0 + /* + * PCI Firmware Specification 3.0 * 4.6.1. _DSM for PCI Express Slot Information * The UUID in _DSM in this context is * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} @@ -316,6 +268,69 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMap= Entry *memmap, buf =3D aml_buffer(1, byte_list); aml_append(method, aml_return(buf)); aml_append(dev, method); +} + +static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, + uint32_t irq, bool use_highmem, bool highmem= _ecam) +{ + int ecam_id =3D VIRT_ECAM_ID(highmem_ecam); + Aml *method, *crs; + hwaddr base_mmio =3D memmap[VIRT_PCIE_MMIO].base; + hwaddr size_mmio =3D memmap[VIRT_PCIE_MMIO].size; + hwaddr base_pio =3D memmap[VIRT_PCIE_PIO].base; + hwaddr size_pio =3D memmap[VIRT_PCIE_PIO].size; + hwaddr base_ecam =3D memmap[ecam_id].base; + hwaddr size_ecam =3D memmap[ecam_id].size; + int nr_pcie_buses =3D size_ecam / PCIE_MMCFG_SIZE_MIN; + + Aml *dev =3D aml_device("%s", "PCI0"); + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); + aml_append(dev, aml_name_decl("_SEG", aml_int(0))); + aml_append(dev, aml_name_decl("_BBN", aml_int(0))); + aml_append(dev, aml_name_decl("_ADR", aml_int(0))); + aml_append(dev, aml_name_decl("_UID", aml_string("PCI0"))); + aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); + + acpi_dsdt_add_pci_route_table(dev, scope, nr_pcie_buses, irq); + + method =3D aml_method("_CBA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(base_ecam))); + aml_append(dev, method); + + method =3D aml_method("_CRS", 0, AML_NOTSERIALIZED); + Aml *rbuf =3D aml_resource_template(); + aml_append(rbuf, + aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, + 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, + nr_pcie_buses)); + aml_append(rbuf, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_m= mio, + base_mmio + size_mmio - 1, 0x0000, size_mmio)); + aml_append(rbuf, + aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, + AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_= pio, + size_pio)); + + if (use_highmem) { + hwaddr base_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].base; + hwaddr size_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].size; + + aml_append(rbuf, + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, + base_mmio_high, + base_mmio_high + size_mmio_high - 1, 0x0000, + size_mmio_high)); + } + + aml_append(method, aml_name_decl("RBUF", rbuf)); + aml_append(method, aml_return(rbuf)); + aml_append(dev, method); + + acpi_dsdt_add_pci_osc(dev, scope); =20 Aml *dev_rp0 =3D aml_device("%s", "RP0"); aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0))); --=20 2.19.1 From nobody Sat Apr 27 19:08:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 21 Feb 2020 01:35:42 -0500 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id A4A98B5A7F26DB493CC5; Fri, 21 Feb 2020 14:35:30 +0800 (CST) Received: from DESKTOP-D7EVK5B.china.huawei.com (10.173.221.29) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.439.0; Fri, 21 Feb 2020 14:35:23 +0800 From: Yubo Miao To: , Subject: [RFC v3 2/3] acpi:pci-expender-bus: Add pxb support for arm Date: Fri, 21 Feb 2020 14:35:11 +0800 Message-ID: <20200221063512.1104-3-miaoyubo@huawei.com> X-Mailer: git-send-email 2.24.1.windows.2 In-Reply-To: <20200221063512.1104-1-miaoyubo@huawei.com> References: <20200221063512.1104-1-miaoyubo@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.173.221.29] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: imammedo@redhat.com, miaoyubo@huawei.com, qemu-devel@nongnu.org, xiexiangyou@huawei.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: miaoyubo Currently virt machine is not supported by pxb-pcie, and only one main host bridge described in ACPI tables. In this patch,PXB-PCIE is supproted by arm and certain resource is allocated for each pxb-pcie in acpi table. The resource for the main host bridge is also reallocated. Signed-off-by: miaoyubo --- hw/arm/virt-acpi-build.c | 125 +++++++++++++++++++++++++++++++++++---- hw/pci-host/gpex.c | 4 ++ include/hw/arm/virt.h | 7 +++ 3 files changed, 125 insertions(+), 11 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 0540234b8a..2c1e0d2aaa 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -49,6 +49,8 @@ #include "kvm_arm.h" #include "migration/vmstate.h" =20 +#include "hw/arm/virt.h" +#include "hw/pci/pci_bus.h" #define ARM_SPI_BASE 32 =20 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) @@ -271,19 +273,117 @@ static void acpi_dsdt_add_pci_osc(Aml *dev, Aml *sco= pe) } =20 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, - uint32_t irq, bool use_highmem, bool highmem= _ecam) + uint32_t irq, bool use_highmem, bool highmem= _ecam, + VirtMachineState *vms) { int ecam_id =3D VIRT_ECAM_ID(highmem_ecam); - Aml *method, *crs; + Aml *method, *dev, *crs; + int count =3D 0; hwaddr base_mmio =3D memmap[VIRT_PCIE_MMIO].base; hwaddr size_mmio =3D memmap[VIRT_PCIE_MMIO].size; hwaddr base_pio =3D memmap[VIRT_PCIE_PIO].base; hwaddr size_pio =3D memmap[VIRT_PCIE_PIO].size; hwaddr base_ecam =3D memmap[ecam_id].base; hwaddr size_ecam =3D memmap[ecam_id].size; + /* + * 0x600000 would be enough for pxb device + * if it is too small, there is no enough space + * for a pcie device plugged in a pcie-root port + */ + hwaddr size_addr =3D 0x600000; + hwaddr size_io =3D 0x4000; int nr_pcie_buses =3D size_ecam / PCIE_MMCFG_SIZE_MIN; + int root_bus_limit =3D 0xFF; + PCIBus *bus =3D NULL; + bus =3D VIRT_MACHINE(vms)->bus; + + if (bus) { + QLIST_FOREACH(bus, &bus->child, sibling) { + uint8_t bus_num =3D pci_bus_num(bus); + uint8_t numa_node =3D pci_bus_numa_node(bus); + + if (!pci_bus_is_root(bus)) { + continue; + } + if (bus_num < root_bus_limit) { + root_bus_limit =3D bus_num - 1; + } + count++; + dev =3D aml_device("PC%.02X", bus_num); + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); + aml_append(dev, aml_name_decl("_ADR", aml_int(0))); + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); + aml_append(dev, aml_name_decl("_SEG", aml_int(0))); + aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); + aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); + aml_append(dev, aml_name_decl("_STR", aml_unicode("pxb Device"= ))); + if (numa_node !=3D NUMA_NODE_UNASSIGNED) { + method =3D aml_method("_PXM", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(numa_node))); + aml_append(dev, method); + } + + acpi_dsdt_add_pci_route_table(dev, scope, nr_pcie_buses, irq); + + method =3D aml_method("_CBA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(base_ecam))); + aml_append(dev, method); + + method =3D aml_method("_CRS", 0, AML_NOTSERIALIZED); + Aml *rbuf =3D aml_resource_template(); + aml_append(rbuf, + aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, + AML_POS_DECODE, 0x0000, + bus_num, bus_num + 1, 0x0000, + 2)); + aml_append(rbuf, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, + AML_MAX_FIXED, AML_NON_CACHEABLE, + AML_READ_WRITE, 0x0000, + base_mmio + size_mmio - + size_addr * count, + base_mmio + size_mmio - 1 - + size_addr * (count - 1), + 0x0000, size_addr)); + aml_append(rbuf, + aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, + AML_POS_DECODE, AML_ENTIRE_RANGE, + 0x0000, size_pio - size_io * count, + size_pio - 1 - size_io * (count - 1), + base_pio, size_io)); + + if (use_highmem) { + hwaddr base_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].base; + hwaddr size_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].size; + + aml_append(rbuf, + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, + AML_MAX_FIXED, AML_NON_CACHEABLE, + AML_READ_WRITE, 0x0000, + base_mmio_high + size_mmio_high - + size_addr * count, + base_mmio_high + size_mmio_high - + 1 - size_addr * (count - 1), + 0x0000, size_addr)); + } + + aml_append(method, aml_name_decl("RBUF", rbuf)); + aml_append(method, aml_return(rbuf)); + aml_append(dev, method); + + acpi_dsdt_add_pci_osc(dev, scope); + + Aml *dev_rp0 =3D aml_device("%s", "RP0"); + aml_append(dev_rp0, aml_name_decl("_ADR", aml_int(0))); + aml_append(dev, dev_rp0); + + aml_append(scope, dev); + + } + } =20 - Aml *dev =3D aml_device("%s", "PCI0"); + dev =3D aml_device("%s", "PCI0"); aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); aml_append(dev, aml_name_decl("_SEG", aml_int(0))); @@ -303,16 +403,18 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMa= pEntry *memmap, Aml *rbuf =3D aml_resource_template(); aml_append(rbuf, aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, - 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, - nr_pcie_buses)); + 0x0000, 0x0000, root_bus_limit, 0x0000, + root_bus_limit + 1)); aml_append(rbuf, aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_m= mio, - base_mmio + size_mmio - 1, 0x0000, size_mmio)); + base_mmio + size_mmio - 1 - size_addr * count, + 0x0000, size_mmio - size_addr * count)); aml_append(rbuf, aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, - AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_= pio, - size_pio)); + AML_ENTIRE_RANGE, 0x0000, 0x0000, + size_pio - 1 - size_io * count, base_pio, + size_pio - size_io * count)); =20 if (use_highmem) { hwaddr base_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].base; @@ -322,8 +424,9 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapE= ntry *memmap, aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_mmio_high, - base_mmio_high + size_mmio_high - 1, 0x0000, - size_mmio_high)); + base_mmio_high + size_mmio_high - 1 - + size_addr * count, + 0x0000, size_mmio_high - size_addr * count)); } =20 aml_append(method, aml_name_decl("RBUF", rbuf)); @@ -759,7 +862,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPO= RTS); acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), - vms->highmem, vms->highmem_ecam); + vms->highmem, vms->highmem_ecam, vms); if (vms->acpi_dev) { build_ged_aml(scope, "\\_SB."GED_DEVICE, HOTPLUG_HANDLER(vms->acpi_dev), diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c index 0ca604dc62..2c18cdfec4 100644 --- a/hw/pci-host/gpex.c +++ b/hw/pci-host/gpex.c @@ -36,6 +36,7 @@ #include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "qemu/module.h" +#include "hw/arm/virt.h" =20 /*************************************************************************= *** * GPEX host @@ -98,6 +99,9 @@ static void gpex_host_realize(DeviceState *dev, Error **e= rrp) pci_swizzle_map_irq_fn, s, &s->io_mmi= o, &s->io_ioport, 0, 4, TYPE_PCIE_BUS); =20 +#ifdef __aarch64__ + VIRT_MACHINE(qdev_get_machine())->bus =3D pci->bus; +#endif qdev_set_parent_bus(DEVICE(&s->gpex_root), BUS(pci->bus)); pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq); qdev_init_nofail(DEVICE(&s->gpex_root)); diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 71508bf40c..9accaf2b1b 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -140,6 +140,13 @@ typedef struct { DeviceState *gic; DeviceState *acpi_dev; Notifier powerdown_notifier; + /* + * pointer to devices and objects + * Via going through the bus, all + * pci devices and related objectes + * could be gained. + * */ + PCIBus *bus; } VirtMachineState; =20 #define VIRT_ECAM_ID(high) (high ? VIRT_HIGH_PCIE_ECAM : VIRT_PCIE_ECAM) --=20 2.19.1 From nobody Sat Apr 27 19:08:16 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1582267022; cv=none; d=zohomail.com; s=zohoarc; b=hz7hMLdkduWk5a5r5/RURoVfrS5+5vJrMmQiPAAuH5DtRCGEsr2a1fcZjsyxTvNHApSx6FebSCYpaZpVIGQee9BTuAju2yzvex/Z/hIS0hZTQpwel0vRGOxbWDQkmHog02H0VFDcP1kqz2VI+LMw5HuIXWGGQOnzgJUhsybq4Hg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582267022; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0+QgKDmBrxxKp2H8Su2nWzk5ZQi3SNXs4yNm1UISTx4=; b=CPbbhPcmYPdUHFfxFaYYJn4tL13uXoN0k6gHrqoXjcUp+4rVnsLrHmyAZ/cimdhQmKcRDo2BSfOzkQ/TWJyQuGITNvf5FuopIwQhxF2l2mar7zvkoPsQ1IOtqxsV3xjd62l1Ad6WRPoa7pgKX4ux7/8P64OBd2VhLt38Swvkfuw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582267022306108.43455299809375; Thu, 20 Feb 2020 22:37:02 -0800 (PST) Received: from localhost ([::1]:52802 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j51vo-0000uD-RH for importer@patchew.org; Fri, 21 Feb 2020 01:37:00 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38552) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j51uZ-0007xl-RJ for qemu-devel@nongnu.org; Fri, 21 Feb 2020 01:35:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j51uX-0003M6-LH for qemu-devel@nongnu.org; Fri, 21 Feb 2020 01:35:43 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:57170 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j51uX-0002xP-0l for qemu-devel@nongnu.org; Fri, 21 Feb 2020 01:35:41 -0500 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id B3AF4CA46EF783EE4248; Fri, 21 Feb 2020 14:35:30 +0800 (CST) Received: from DESKTOP-D7EVK5B.china.huawei.com (10.173.221.29) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.439.0; Fri, 21 Feb 2020 14:35:24 +0800 From: Yubo Miao To: , Subject: [RFC v3 3/3] ACPI/unit-test: Add a new test for pxb-pcie for arm Date: Fri, 21 Feb 2020 14:35:12 +0800 Message-ID: <20200221063512.1104-4-miaoyubo@huawei.com> X-Mailer: git-send-email 2.24.1.windows.2 In-Reply-To: <20200221063512.1104-1-miaoyubo@huawei.com> References: <20200221063512.1104-1-miaoyubo@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.173.221.29] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: imammedo@redhat.com, miaoyubo@huawei.com, qemu-devel@nongnu.org, xiexiangyou@huawei.com, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: miaoyubo Currently, pxb-pcie could be defined by the cmdline like --device pxb-pcie,id=3Dpci.9,bus_nr=3D128 However pxb-pcie is not described in acpi tables for arm. The formal two patches support pxb-pcie for arm, escpcially the specification for pxb-pcie in DSDT table. Add a testcase to make sure the ACPI table is correct for guest. Signed-off-by: miaoyubo --- tests/data/acpi/virt/DSDT.pxb | Bin 0 -> 34209 bytes tests/qtest/bios-tables-test.c | 54 +++++++++++++++++++++++++++++---- 2 files changed, 48 insertions(+), 6 deletions(-) create mode 100644 tests/data/acpi/virt/DSDT.pxb diff --git a/tests/data/acpi/virt/DSDT.pxb b/tests/data/acpi/virt/DSDT.pxb new file mode 100644 index 0000000000000000000000000000000000000000..4eea3192c75ff28f7054d626a93= 63ca025b6c0ad GIT binary patch literal 34209 zcmeI*cXU+szJ~D)1PGxe5PG+us9-{YGz}UAMT!L#ks?x*Dx!d5hoIPd z?}}o>iWL;GW5HgrlKbvVM&HM??^)~qbMIProvd|8p2_U*%qO!m?AgcPkRQ(HLbszg^Hd* zYT59@{GfDxK}u{$QSzH5MFX?4va_qcnOYVriD$G-YqqdX5KgQUqzA#0T0ymH9aJ-P zt=3D#;Qdf_)p=3DV$jH6t9{xXmH68P3ev)8EFlwrs(=3DX$_(9dxJh>6UU8FZi5vcVla%Bp zz50)g^-pXvw4i9XAYFAU@nN}Xb+t___n%uw)`8L z7F4goX88!*;pB+$X8&bG_2BOj*;OO*!h6xx&B+mI)uU#l*o>||BPVi3ji?#5Y(|dH z=3DoUF6C2B^h&FJPcx<}5a88su#W_0%%JtAk+ikeZ+X7unGJtJq-j+)WHX7uzKy&`9% zM$JgK8NGZ)@5mW-qGmL*8NF>rHhzu%+CS2wW@OrogM3EhZpvShs#sHrYy`MIZnvrEQ2KtQX{j^2YjIK7L z&}T&Nr!Avqbh8+KeGpGv;lrQ5@@4bw`Q^7iZ;W_0oY$Ob29%%1Indg_l(x zNW=3D>U=3D@nIzyEz+7!38n{QgZ4pwa9l7gm>7)H=3DRj93E*aK%`Pv$F zgOo;fQ|eY!1OwuQSwZ6KYWg}mXjCt}JgvH-Ycgsma)L(nQ|eVz=3Dol|?y{Zbg(iIyd zzE`=3DOuA0nnOU%j8vc92DN7u3EXJGTc)4rt-QqDz{ADgBn4&W%8;u z5?ku3m0K#qEp?A7x70yl;<{B;Wvslaj+?5K$#iE;IBQnkX3|+Rv1RhkE8STOP8|vB z9we`-<1BY7-B}yX+HlsUQ|ZoBI8!UPO#Vo8T;@)tJL|xyWB9~RukuGyhfbwC)8I^l zQ^#@cRJyY+oOR)>OQ+JEdLdztXFWJ|+~-cEJL|()AI|!8D&5%t&IWMmIMJO-cQ%Bx zA)F2ARJv2Iq0E^Mr;aP#sdQ%soEdOt(5ZB1BRCtuspC+0D&5%_&c<*yrc>$8OgJ;) z)N!jjmF{c;XA?M^(5ZB1Q#hN#spDLCD&5%(&Sr2nqf_Zly~4D|vpJkPE_SEVoh{&O z0cQ(3mF{c_XG=3DJB9PLh}J6plo3eHw^D&5%{&em}1xZ9mdcea7E4V-Q0RJyY*oNeLM zak@K|?raBVJ2>0XsdQ(1INQUi<9c^0-Kn!8+7pt0vvq*81D#5D?g8f>aO!n{JC*L- z6V5&1+>=3DhFJNJTfFF5tO!JSHX?hWVOaPCc~(w!aQ>*#*unaO!oEJC*J{5Y7YPJdjSMJ9RqFo^P|@)axpDD&48GaQ6F|4QDo; zN_Xnqo3>0Id3J?UufyD_bf?a^Y0KpCZ4R6{bSmAc^K9nq2B%)Pxl`#*on13$cR0J# zsdT5#shP6}oO+$-PNh3_Ce55Z;p|DL(w#bgX3k!4>UE(zmG0D8GjsNavp1becj{c3 zIS+zUuOr>5bf?acne$*c52jP;PMsGs=3DOJ+Fb*DR(?$p^ZbM}F=3D51mSP>KvFk`@*T$ zsqR#|Q)j-+c_^HR(y4T3KRElr*^f@8J9U=3DJoVjr3(y4T(&TW}956(O~mG0CTEpx`; zjM1rdr_N((%j7HId^q#zRJv1VugqBhX91l`cj}y#Is3!epH8Jab*9Rk1K=3DD$r_!A| zKV{B=3Da1NwX=3D}w)MGG`&2g>)+2sdG{0JPgjm=3Dv2B>XQ0e^IGl&msdT5#JDGD3oP+38 zx>IMH%vl6y5uHkR>Kv0f2g5m-PNh3_X33mG;2c7y(w)U{7QIFE$$NII47EQPZa&Qdy+?i>y0XgEjHsdVR2 za2^HcQFJQZc{H3y!+A8FN_UpQSq5hrol19(fpZL;W9U@6^B6dff%6zTmF^r1=3DU6z$ z(y4UkI5@|_IgU=3DHJCB9)SU8WRQ|V5f@3!aLeO=3DLvKw-FYIM zC&GCmol19}1m{U`oCRK(JQdDU z=3D~TM&G&oO#^E5h@?wkteR5+*7sdVS*aGnn5>2xaHIStNfa89FB>CQ9YJOj=3D%=3Dv2CM zI-JwtoKC0GoipH^0p|=3DlmF}Dg=3DS( zHk@a}c{ZI&cb)_1IdGmsr_!AZ;9LOb0y>rMTnOhvI2Y2Xbmt;C7s0uRPNh2+!?_sF z#dIp&xdhH7a4w-!>CUBaE`@U`ol19}3+K6To=3Dd0Foy*`{2In$5mF_$b&hy|rk4~jK zm&3Un&gFC}-FZHo=3DfinEol19J0Otj8UO=3DbPoh#s60p|)jmF`>#=3DSnzN(y4UkDmYic zxr$DuJ1>OuLO3s^Q|Zo&;JgUVi|ACkb2Xf+;ap9p(w!H>c`=3D+9)2VdlC2(E>=3DOuJ1 z-FYdTm%@1|ol19J2IpmPUPhc%sdVQRa9#oD6?7`yc_o}z!g(c~N_Vb- za}Atp=3Dv2CMEu3rNTuZ0Yo#k+r!&y$J(w*zzTnFbmI+gCc3eKzGyoyexJFkZGYB;Z^ zQ|Zq2aIS}QJ)KH-UIXVfa9%^F(w*1Bc`cmR(y4Ukb#Pt>=3DXG=3D{-FZEn*TZ=3D|ol1A! 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"" : "-accel kvm", - data->uefi_fl1, data->uefi_fl2, data->cd, params ? params : ""= ); - + if (data->cd) { + args =3D g_strdup_printf("-machine %s %s -accel tcg " + "-nodefaults -nographic " + "-drive if=3Dpflash,format=3Draw,file=3D%s,readonly " + "-drive if=3Dpflash,format=3Draw,file=3D%s,snapshot=3Don -= cdrom %s %s", + data->machine, data->tcg_only ? "" : "-accel kvm", + data->uefi_fl1, data->uefi_fl2, data->cd, params ? params = : ""); + } else { + args =3D g_strdup_printf("-machine %s %s -accel tcg " + "-nodefaults -nographic " + "-drive if=3Dpflash,format=3Draw,file=3D%s,readonly " + "-drive if=3Dpflash,format=3Draw,file=3D%s,snapshot=3Don %= s", + data->machine, data->tcg_only ? "" : "-accel kvm", + data->uefi_fl1, data->uefi_fl2, params ? params : ""); + } } else { /* Disable kernel irqchip to be able to override apic irq0. */ args =3D g_strdup_printf("-machine %s,kernel-irqchip=3Doff %s -acc= el tcg " @@ -960,6 +969,38 @@ static void test_acpi_virt_tcg_numamem(void) =20 } =20 +static void test_acpi_virt_tcg_pxb(void) +{ + test_data data =3D { + .machine =3D "virt", + .tcg_only =3D true, + .uefi_fl1 =3D "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 =3D "pc-bios/edk2-arm-vars.fd", + .ram_start =3D 0x40000000ULL, + .scan_len =3D 128ULL * 1024 * 1024, + }; + /* + * While using -cdrom, the cdrom would auto plugged into pxb-pcie, + * the reason is the bus of pxb-pcie is also root bus, it would lead + * to the error only PCI/PCIE bridge could plug onto pxb. + * Therefore,thr cdrom is defined and plugged onto the scsi controller + * to solve the conflicts. + */ + data.variant =3D ".pxb"; + test_acpi_one(" -device pcie-root-port,chassis=3D1,id=3Dpci.1" + " -device virtio-scsi-pci,id=3Dscsi0,bus=3Dpci.1" + " -drive file=3D" + "tests/data/uefi-boot-images/bios-tables-test.aarch64.is= o.qcow2," + "if=3Dnone,media=3Dcdrom,id=3Ddrive-scsi0-0-0-1,readonly= =3Don" + " -device scsi-cd,bus=3Dscsi0.0,scsi-id=3D0," + "drive=3Ddrive-scsi0-0-0-1,id=3Dscsi0-0-0-1,bootindex=3D= 1" + " -cpu cortex-a57" + " -device pxb-pcie,bus_nr=3D128", + &data); + + free_test_data(&data); +} + static void test_acpi_tcg_acpi_hmat(const char *machine) { test_data data; @@ -1052,6 +1093,7 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/virt", test_acpi_virt_tcg); qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem); qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp); + qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb); } ret =3D g_test_run(); boot_sector_cleanup(disk); --=20 2.19.1