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Thu, 20 Feb 2020 14:02:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1582207346; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Z6YmwN7BQesNWvl/e1ATsqXxfhRdFSw9Rf2vpl2YuV8=; b=dw+SFEAr+FiogqZdRFhjXttkM6OPzcOr3rO5dWS3mHTkb0BpdFp07sSoCHv57o+VfCqu2S wOVW9/QhkrsgH25MuUHrrVyVQ892tIb0kbZvgxqkCd6TnoGN1aBVz31HB5EHE8NjJK7mdF 3J7NrJdIL8jvYr4fHr2DZtN6EUjlvEQ= X-MC-Unique: vA59OkpDOGGTJFCk5j0PuA-1 From: Kashyap Chamarthy To: kchamart@redhat.com, qemu-devel@nongnu.org Subject: [PATCH v3 2/2] qemu-cpu-models.rst: Document -noTSX, mds-no, taa-no, and tsx-ctrl Date: Thu, 20 Feb 2020 15:02:10 +0100 Message-Id: <20200220140210.14209-3-kchamart@redhat.com> In-Reply-To: <20200220140210.14209-1-kchamart@redhat.com> References: <20200220140210.14209-1-kchamart@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, berrange@redhat.com, ehabkost@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" - Add the '-noTSX' variants for CascadeLake and SkyLake. - Document the three MSR bits: 'mds-no', 'taa-no', and 'tsx-ctrl' Two confusing things about 'mds-no' (and the first point applies to the other two MSRs too): (1) The 'mds-no' bit will _not_ show up in the guest's /proc/cpuinfo. Rather it is used to fill in the guest's sysfs: /sys/devices/system/cpu/vulnerabilities/mds:Not affected Paolo confirmed on IRC as such. (2) There are _three_ variants[+] of CascadeLake CPUs, with different stepping levels: 5, 6, and 7. To quote wikichip.org[*]: "note that while steppings 6 & 7 are fully mitigated, earlier stepping 5 is not protected against MSBDS, MLPDS, nor MDSUM" The above is also indicated in the Intel's document[+], as indicated by "No" under the three columns of MFBDS, MSBDS, and MLPDS. I've expressed this in the docs without belabouring the details. [+] https://software.intel.com/security-software-guidance/insights/pr= ocessors-affected-microarchitectural-data-sampling [*] https://en.wikichip.org/wiki/intel/microarchitectures/cascade_lak= e#Key_changes_from_Skylake Signed-off-by: Kashyap Chamarthy --- docs/system/qemu-cpu-models.rst | 57 +++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/docs/system/qemu-cpu-models.rst b/docs/system/qemu-cpu-models.= rst index a189d6a9da..946e90e1dc 100644 --- a/docs/system/qemu-cpu-models.rst +++ b/docs/system/qemu-cpu-models.rst @@ -61,15 +61,24 @@ mixture of host CPU models between machines, if live mi= gration compatibility is required, use the newest CPU model that is compatible across all desired hosts. =20 +* Intel Xeon Processor (Cascade Lake, 2019), with "stepping" levels 6 or + 7 only. (The Cascade Lake Xeon processor with *stepping 5 is + vulnerable to MDS variants*.) + + * ``Cascadelake-Server`` + * ``Cascadelake-Server-noTSX`` + * Intel Xeon Processor (Skylake, 2016) =20 * ``Skylake-Server`` * ``Skylake-Server-IBRS`` + * ``Skylake-Server-IBRS-noTSX`` =20 * Intel Core Processor (Skylake, 2015) =20 * ``Skylake-Client`` * ``Skylake-Client-IBRS`` + * ``Skylake-Client-noTSX-IBRS}`` =20 * Intel Core Processor (Broadwell, 2014) =20 @@ -182,6 +191,54 @@ features are included if using "Host passthrough" or "= Host model". Requires the host CPU microcode to support this feature before it can be used for guest CPUs. =20 +``mds-no`` + Recommended to inform the guest OS that the host is *not* vulnerable + to any of the MDS variants ([MFBDS] CVE-2018-12130, [MLPDS] + CVE-2018-12127, [MSBDS] CVE-2018-12126). + + This is an MSR (Model-Specific Register) feature rather than a CPUID fea= ture, + so it will not appear in the Linux ``/proc/cpuinfo`` in the host or + guest. Instead, the host kernel uses it to populate the MDS + vulnerability file in ``sysfs``. + + So it should only be enabled for VMs if the host reports @code{Not + affected} in the ``/sys/devices/system/cpu/vulnerabilities/mds`` file. + +``taa-no`` + Recommended to inform that the guest that the host is ``not`` + vulnerable to CVE-2019-11135, TSX Asynchronous Abort (TAA). + + This too is an MSR feature, so it does not show up in the Linux + ``/proc/cpuinfo`` in the host or guest. + + It should only be enabled for VMs if the host reports ``Not affected`` + in the ``/sys/devices/system/cpu/vulnerabilities/tsx_async_abort`` + file. + +``tsx-ctrl`` + Recommended to inform the guest that it can disable the Intel TSX + (Transactional Synchronization Extensions) feature; or, if the + processor is vulnerable, use the Intel VERW instruction (a + processor-level instruction that performs checks on memory access) as + a mitigation for the TAA vulnerability. (For details, refer to this + `Intel's deep-dive into + MDS `_.) + + Expose this to the guest OS if and only if: (a) the host has TSX + enabled; *and* (b) the guest has ``rtm`` CPU flag enabled. + + By disabling TSX, KVM-based guests can avoid paying the price of + mitigting TSX-based attacks. + + Note that ``tsx-ctrl`` too is an MSR feature, so it does not show + up in the Linux ``/proc/cpuinfo`` in the host or guest. + + To validate that Intel TSX is indeed disabled for the guest, there are + two ways: (a) check for the *absence* of ``rtm`` in the guest's + ``/proc/cpuinfo``; or (b) the + ``/sys/devices/system/cpu/vulnerabilities/tsx_async_abort`` file in + the guest should report ``Mitigation: TSX disabled``. + =20 Preferred CPU models for AMD x86 hosts ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ --=20 2.21.0