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[88.21.202.78]) by smtp.gmail.com with ESMTPSA id b67sm4594690wmc.38.2020.02.20.05.06.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Feb 2020 05:06:30 -0800 (PST) X-Inumbo-ID: d27210a2-53e1-11ea-b0fd-bc764e2007e4 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1582203995; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Vu5bnXCWmoR0uDiabSQGY0CwtpVH4vjEupEa47euXok=; b=B+e4Abv//ugZdLn38Zqbu49kfI3GmQc/vdGlllKKIzcUl6wBkv0Wl/pcH73IVlaupm4qzw ufJcmdYRMlVkfwMaYinNt/J2hto8QV6N+iqmLSUEIcAtHzGWzz7E+7PIIa51YklWgv451p rSeo7ZP4O/pxvOzG7m6qR6WICjC8UXQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/ld+m5dlIbdFkFHFURC0jskPtvz279hvl5fOCIwyBcI=; b=XitgwzLxm9XtvZL7o08PEf1bUTtJd60cqG2Irjo/j2VFhPSYIAPK5AXkBjjo0GvUDs Hgky7eBpB15YK5R0mFyXaM8jApH+fsI6nvS69eCzgyw3mzesNMWRBpfZ34GU8/cCJIYT Dhv7TvNiB0g/VVHp7Md8j2bJR3RDiEk9NYSFS5REjHdsePjs+CRsQXGjufEoAdEIWW7y AxEfuDvT4GXRY62SgJn7NDDQsXDblxPCBQEZRjCzkXCjs+goicvifGYM9g51X6Z03rcs u6Kq2sktdd4ajIIuELcbZSdp/Lz92NEcF5iXRzhMTDxxSBQCQegz3T0YaL436RPx8TX0 RHHQ== X-Gm-Message-State: APjAAAVcvNy/INCkbJCLIvhhZV6BrB3aIiohy8ECgyshlpZ72eaIsI4v LBxgPX28LlWRPj6QZkBi8bhhczHLF/p/dM66FHmuTxQKNvrol0yDBa2m4NukE6kpkl1rt9iVDco odduL+xS2nD4pAorVLTqGf83NIJI= X-Received: by 2002:adf:e781:: with SMTP id n1mr45109041wrm.56.1582203991748; Thu, 20 Feb 2020 05:06:31 -0800 (PST) X-Google-Smtp-Source: APXvYqwouSCwy3rqeENoKe0gZr/3kvydEDFXzHky1eaSJGgeUp7K/B6TN0eEopUiJDH/U8pAJl2oNQ== X-Received: by 2002:adf:e781:: with SMTP id n1mr45109010wrm.56.1582203991459; Thu, 20 Feb 2020 05:06:31 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: Peter Maydell , qemu-devel@nongnu.org Date: Thu, 20 Feb 2020 14:05:38 +0100 Message-Id: <20200220130548.29974-11-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200220130548.29974-1-philmd@redhat.com> References: <20200220130548.29974-1-philmd@redhat.com> MIME-Version: 1.0 X-MC-Unique: 2nsEbd49MZ2DVas3SsuWZg-1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Subject: [Xen-devel] [PATCH v3 10/20] Remove unnecessary cast when using the cpu_[physical]_memory API X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Dmitry Fleytman , kvm@vger.kernel.org, "Michael S. Tsirkin" , Jason Wang , Gerd Hoffmann , "Edgar E. Iglesias" , Stefano Stabellini , Matthew Rosato , qemu-block@nongnu.org, David Hildenbrand , Halil Pasic , Christian Borntraeger , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Marcel Apfelbaum , Anthony Perard , xen-devel@lists.xenproject.org, Aleksandar Rikalo , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Laurent Vivier , Thomas Huth , Eduardo Habkost , Stefan Weil , Alistair Francis , Richard Henderson , Paul Durrant , Eric Auger , qemu-s390x@nongnu.org, qemu-arm@nongnu.org, =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , John Snow , David Gibson , Igor Mitsyanko , Cornelia Huck , Michael Walle , qemu-ppc@nongnu.org, Paolo Bonzini Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) This commit was produced with the included Coccinelle script scripts/coccinelle/exec_rw_const. Suggested-by: Stefan Weil Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- scripts/coccinelle/exec_rw_const.cocci | 10 ++++++++++ hw/display/omap_lcdc.c | 10 +++++----- hw/dma/etraxfs_dma.c | 25 ++++++++++--------------- hw/scsi/vmw_pvscsi.c | 8 +++----- target/i386/hax-all.c | 6 +++--- 5 files changed, 31 insertions(+), 28 deletions(-) diff --git a/scripts/coccinelle/exec_rw_const.cocci b/scripts/coccinelle/ex= ec_rw_const.cocci index 5ed956a834..70cf52d58e 100644 --- a/scripts/coccinelle/exec_rw_const.cocci +++ b/scripts/coccinelle/exec_rw_const.cocci @@ -34,6 +34,16 @@ type T; + address_space_write_rom(E1, E2, E3, E4, E5) | =20 +- cpu_physical_memory_rw(E1, (T *)E2, E3, E4) ++ cpu_physical_memory_rw(E1, E2, E3, E4) +| +- cpu_physical_memory_read(E1, (T *)E2, E3) ++ cpu_physical_memory_read(E1, E2, E3) +| +- cpu_physical_memory_write(E1, (T *)E2, E3) ++ cpu_physical_memory_write(E1, E2, E3) +| + - dma_memory_read(E1, E2, (T *)E3, E4) + dma_memory_read(E1, E2, E3, E4) | diff --git a/hw/display/omap_lcdc.c b/hw/display/omap_lcdc.c index 6ad13f2e9e..fa4a381db6 100644 --- a/hw/display/omap_lcdc.c +++ b/hw/display/omap_lcdc.c @@ -91,9 +91,9 @@ static void omap_update_display(void *opaque) =20 frame_offset =3D 0; if (omap_lcd->plm !=3D 2) { - cpu_physical_memory_read(omap_lcd->dma->phys_framebuffer[ - omap_lcd->dma->current_frame], - (void *)omap_lcd->palette, 0x200); + cpu_physical_memory_read( + omap_lcd->dma->phys_framebuffer[omap_lcd->dma->current_fra= me], + omap_lcd->palette, 0x200); switch (omap_lcd->palette[0] >> 12 & 7) { case 3 ... 7: frame_offset +=3D 0x200; @@ -244,8 +244,8 @@ static void omap_lcd_update(struct omap_lcd_panel_s *s)= { =20 if (s->plm !=3D 2 && !s->palette_done) { cpu_physical_memory_read( - s->dma->phys_framebuffer[s->dma->current_frame], - (void *)s->palette, 0x200); + s->dma->phys_framebuffer[s->dma->current_frame= ], + s->palette, 0x200); s->palette_done =3D 1; omap_lcd_interrupts(s); } diff --git a/hw/dma/etraxfs_dma.c b/hw/dma/etraxfs_dma.c index 47e1c6df12..c4334e87bf 100644 --- a/hw/dma/etraxfs_dma.c +++ b/hw/dma/etraxfs_dma.c @@ -225,9 +225,8 @@ static void channel_load_g(struct fs_dma_ctrl *ctrl, in= t c) hwaddr addr =3D channel_reg(ctrl, c, RW_GROUP); =20 /* Load and decode. FIXME: handle endianness. */ - cpu_physical_memory_read (addr,=20 - (void *) &ctrl->channels[c].current_g,=20 - sizeof ctrl->channels[c].current_g); + cpu_physical_memory_read(addr, &ctrl->channels[c].current_g, + sizeof(ctrl->channels[c].current_g)); } =20 static void dump_c(int ch, struct dma_descr_context *c) @@ -257,9 +256,8 @@ static void channel_load_c(struct fs_dma_ctrl *ctrl, in= t c) hwaddr addr =3D channel_reg(ctrl, c, RW_GROUP_DOWN); =20 /* Load and decode. FIXME: handle endianness. */ - cpu_physical_memory_read (addr,=20 - (void *) &ctrl->channels[c].current_c,=20 - sizeof ctrl->channels[c].current_c); + cpu_physical_memory_read(addr, &ctrl->channels[c].current_c, + sizeof(ctrl->channels[c].current_c)); =20 D(dump_c(c, &ctrl->channels[c].current_c)); /* I guess this should update the current pos. */ @@ -275,9 +273,8 @@ static void channel_load_d(struct fs_dma_ctrl *ctrl, in= t c) =20 /* Load and decode. FIXME: handle endianness. */ D(printf("%s ch=3D%d addr=3D" TARGET_FMT_plx "\n", __func__, c, addr)); - cpu_physical_memory_read (addr, - (void *) &ctrl->channels[c].current_d,=20 - sizeof ctrl->channels[c].current_d); + cpu_physical_memory_read(addr, &ctrl->channels[c].current_d, + sizeof(ctrl->channels[c].current_d)); =20 D(dump_d(c, &ctrl->channels[c].current_d)); ctrl->channels[c].regs[RW_DATA] =3D addr; @@ -290,9 +287,8 @@ static void channel_store_c(struct fs_dma_ctrl *ctrl, i= nt c) /* Encode and store. FIXME: handle endianness. */ D(printf("%s ch=3D%d addr=3D" TARGET_FMT_plx "\n", __func__, c, addr)); D(dump_d(c, &ctrl->channels[c].current_d)); - cpu_physical_memory_write (addr, - (void *) &ctrl->channels[c].current_c, - sizeof ctrl->channels[c].current_c); + cpu_physical_memory_write(addr, &ctrl->channels[c].current_c, + sizeof(ctrl->channels[c].current_c)); } =20 static void channel_store_d(struct fs_dma_ctrl *ctrl, int c) @@ -301,9 +297,8 @@ static void channel_store_d(struct fs_dma_ctrl *ctrl, i= nt c) =20 /* Encode and store. FIXME: handle endianness. */ D(printf("%s ch=3D%d addr=3D" TARGET_FMT_plx "\n", __func__, c, addr)); - cpu_physical_memory_write (addr, - (void *) &ctrl->channels[c].current_d,=20 - sizeof ctrl->channels[c].current_d); + cpu_physical_memory_write(addr, &ctrl->channels[c].current_d, + sizeof(ctrl->channels[c].current_d)); } =20 static inline void channel_stop(struct fs_dma_ctrl *ctrl, int c) diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c index e4ee2e6643..c91352cf46 100644 --- a/hw/scsi/vmw_pvscsi.c +++ b/hw/scsi/vmw_pvscsi.c @@ -404,8 +404,7 @@ pvscsi_cmp_ring_put(PVSCSIState *s, struct PVSCSIRingCm= pDesc *cmp_desc) =20 cmp_descr_pa =3D pvscsi_ring_pop_cmp_descr(&s->rings); trace_pvscsi_cmp_ring_put(cmp_descr_pa); - cpu_physical_memory_write(cmp_descr_pa, (void *)cmp_desc, - sizeof(*cmp_desc)); + cpu_physical_memory_write(cmp_descr_pa, cmp_desc, sizeof(*cmp_desc)); } =20 static void @@ -415,8 +414,7 @@ pvscsi_msg_ring_put(PVSCSIState *s, struct PVSCSIRingMs= gDesc *msg_desc) =20 msg_descr_pa =3D pvscsi_ring_pop_msg_descr(&s->rings); trace_pvscsi_msg_ring_put(msg_descr_pa); - cpu_physical_memory_write(msg_descr_pa, (void *)msg_desc, - sizeof(*msg_desc)); + cpu_physical_memory_write(msg_descr_pa, msg_desc, sizeof(*msg_desc)); } =20 static void @@ -491,7 +489,7 @@ pvscsi_get_next_sg_elem(PVSCSISGState *sg) { struct PVSCSISGElement elem; =20 - cpu_physical_memory_read(sg->elemAddr, (void *)&elem, sizeof(elem)); + cpu_physical_memory_read(sg->elemAddr, &elem, sizeof(elem)); if ((elem.flags & ~PVSCSI_KNOWN_FLAGS) !=3D 0) { /* * There is PVSCSI_SGE_FLAG_CHAIN_ELEMENT flag described in diff --git a/target/i386/hax-all.c b/target/i386/hax-all.c index a8b6e5aeb8..a9cc51e6ce 100644 --- a/target/i386/hax-all.c +++ b/target/i386/hax-all.c @@ -367,7 +367,7 @@ static int hax_accel_init(MachineState *ms) static int hax_handle_fastmmio(CPUArchState *env, struct hax_fastmmio *hft) { if (hft->direction < 2) { - cpu_physical_memory_rw(hft->gpa, (uint8_t *) &hft->value, hft->siz= e, + cpu_physical_memory_rw(hft->gpa, &hft->value, hft->size, hft->direction); } else { /* @@ -376,8 +376,8 @@ static int hax_handle_fastmmio(CPUArchState *env, struc= t hax_fastmmio *hft) * hft->direction =3D=3D 2: gpa =3D=3D> gpa2 */ uint64_t value; - cpu_physical_memory_rw(hft->gpa, (uint8_t *) &value, hft->size, 0); - cpu_physical_memory_rw(hft->gpa2, (uint8_t *) &value, hft->size, 1= ); + cpu_physical_memory_rw(hft->gpa, &value, hft->size, 0); + cpu_physical_memory_rw(hft->gpa2, &value, hft->size, 1); } =20 return 0; --=20 2.21.1 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel