From nobody Tue Feb 10 02:43:14 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1582169497; cv=none; d=zohomail.com; s=zohoarc; b=PIJcSFyUZ2megeT/VWnSH07c4z6LWwqJYmVkSxrm3k9kFuN3KosQ6+fVMHg6132qk7yXS0ZTl4tNRO1x9QvkIM361kmIjArEmKdD5Q+4zuORI21W1cWvR6O7NfWBTM8NTOEFIGM+bEwEj3caOrF4ldnGSuAgEwI5sJACAzyZFno= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582169497; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xV3tATy2pxVPFDD0sPAdoS3cEhf8cCcuL36w7DixV28=; b=AfU+r0PKLBDhBGIW2fzdFDUACwoH3r14V528B9ETrnBatu7uTjnWb6uIZrI/rGtHJRZdhcv8uOlPrqiOFGc5F/8FVPB3ngsegeSBzHa5vyCSP5Y922FtmJmRnEdqNeaVUPz1R54xetaOG9dH/nNiHdCXcFQttVvQ2xTY8KB2S6A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582169497583695.4663679888745; Wed, 19 Feb 2020 19:31:37 -0800 (PST) Received: from localhost ([::1]:35368 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cYo-0001wc-U6 for importer@patchew.org; Wed, 19 Feb 2020 22:31:36 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41289) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j4cR7-0004bl-Mq for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j4cR6-0008Kk-4O for qemu-devel@nongnu.org; Wed, 19 Feb 2020 22:23:37 -0500 Received: from bilbo.ozlabs.org ([2401:3900:2:1::2]:38161 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j4cR5-0008II-Pk; Wed, 19 Feb 2020 22:23:36 -0500 Received: by ozlabs.org (Postfix, from userid 1007) id 48NKg070d5z9sSV; Thu, 20 Feb 2020 14:23:24 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1582169004; bh=RRBYOYs77/SsmZjN3ZGuK3pIJMM/GJemM7kFf49sycw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Wwif7NwtdB4TenzmNsZ+RjNOtlGou4nM59pKCANpYKw8raH90KfoJiimXDUIBO3e/ URQDR1/UQgzrkoU0gFA0o4VQH3MgVtZtrIGOfnvHPVPKEqn69MVHAww874dP+phv2Y 84iiD9NrGJ5LbmLQfqKZF9tF7mqfgmP7tiJJ2yOc= From: David Gibson To: qemu-ppc@nongnu.org, groug@kaod.org, clg@kaod.org Subject: [PATCH v5 08/18] target/ppc: Streamline calculation of RMA limit from LPCR[RMLS] Date: Thu, 20 Feb 2020 14:23:06 +1100 Message-Id: <20200220032317.96884-9-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200220032317.96884-1-david@gibson.dropbear.id.au> References: <20200220032317.96884-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, Thomas Huth , Xiao Guangrong , "Michael S. Tsirkin" , aik@ozlabs.ru, Mark Cave-Ayland , qemu-devel@nongnu.org, Igor Mammedov , paulus@samba.org, Paolo Bonzini , "Edgar E. Iglesias" , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Currently we use a big switch statement in ppc_hash64_update_rmls() to work out what the right RMA limit is based on the LPCR[RMLS] field. There's no formula for this - it's just an arbitrary mapping defined by the existing CPU implementations - but we can make it a bit more readable by using a lookup table rather than a switch. In addition we can use the MiB/GiB symbols to make it a bit clearer. While there we add a bit of clarity and rationale to the comment about what happens if the LPCR[RMLS] doesn't contain a valid value. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater --- target/ppc/mmu-hash64.c | 71 ++++++++++++++++++++--------------------- 1 file changed, 35 insertions(+), 36 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 8acd1f78ae..4e6c1f722b 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -18,6 +18,7 @@ * License along with this library; if not, see . */ #include "qemu/osdep.h" +#include "qemu/units.h" #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" @@ -757,6 +758,39 @@ static void ppc_hash64_set_c(PowerPCCPU *cpu, hwaddr p= tex, uint64_t pte1) stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80); } =20 +static target_ulong rmls_limit(PowerPCCPU *cpu) +{ + CPUPPCState *env =3D &cpu->env; + /* + * This is the full 4 bits encoding of POWER8. Previous + * CPUs only support a subset of these but the filtering + * is done when writing LPCR + */ + const target_ulong rma_sizes[] =3D { + [0] =3D 0, + [1] =3D 16 * GiB, + [2] =3D 1 * GiB, + [3] =3D 64 * MiB, + [4] =3D 256 * MiB, + [5] =3D 0, + [6] =3D 0, + [7] =3D 128 * MiB, + [8] =3D 32 * MiB, + }; + target_ulong rmls =3D (env->spr[SPR_LPCR] & LPCR_RMLS) >> LPCR_RMLS_SH= IFT; + + if (rmls < ARRAY_SIZE(rma_sizes)) { + return rma_sizes[rmls]; + } else { + /* + * Bad value, so the OS has shot itself in the foot. Return a + * 0-sized RMA which we expect to trigger an immediate DSI or + * ISI + */ + return 0; + } +} + int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx) { @@ -1006,41 +1040,6 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, targ= et_ulong ptex, cpu->env.tlb_need_flush =3D TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLU= SH; } =20 -static void ppc_hash64_update_rmls(PowerPCCPU *cpu) -{ - CPUPPCState *env =3D &cpu->env; - uint64_t lpcr =3D env->spr[SPR_LPCR]; - - /* - * This is the full 4 bits encoding of POWER8. Previous - * CPUs only support a subset of these but the filtering - * is done when writing LPCR - */ - switch ((lpcr & LPCR_RMLS) >> LPCR_RMLS_SHIFT) { - case 0x8: /* 32MB */ - env->rmls =3D 0x2000000ull; - break; - case 0x3: /* 64MB */ - env->rmls =3D 0x4000000ull; - break; - case 0x7: /* 128MB */ - env->rmls =3D 0x8000000ull; - break; - case 0x4: /* 256MB */ - env->rmls =3D 0x10000000ull; - break; - case 0x2: /* 1GB */ - env->rmls =3D 0x40000000ull; - break; - case 0x1: /* 16GB */ - env->rmls =3D 0x400000000ull; - break; - default: - /* What to do here ??? */ - env->rmls =3D 0; - } -} - static void ppc_hash64_update_vrma(PowerPCCPU *cpu) { CPUPPCState *env =3D &cpu->env; @@ -1099,7 +1098,7 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) CPUPPCState *env =3D &cpu->env; =20 env->spr[SPR_LPCR] =3D val & pcc->lpcr_mask; - ppc_hash64_update_rmls(cpu); + env->rmls =3D rmls_limit(cpu); ppc_hash64_update_vrma(cpu); } =20 --=20 2.24.1